JPS6232825B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction circuit, and more particularly to an error correction circuit that corrects read data in a storage device and generates a write check bit for rewriting.

A conventional error correction circuit includes an error correction code generator that generates an error correction code according to written data during writing, according to read data during reading, and corrected data during rewriting; an exclusive OR circuit that calculates an exclusive OR with a read check bit and outputs a syndrome when there is no writing; and a data corrector that outputs the corrected data to be corrected and written to the storage medium together with the error correction code during the rewriting.

In other words, conventional error correction circuits share an error correction code generator, and when there is a correctable error in the read data, they correct the error in the read data and read check bits, and generate an error correction code for rewriting. To generate the syndrome, a syndrome is generated from the read data read from the storage medium and the read check bit during the first error correction by an exclusive OR circuit via an error correction code generator.
Errors in read data due to the syndrome are corrected and corrected data is output. In order to correctly rewrite the information stored in the storage medium when the second code is generated, the correction data is supplied to an error correction code generator to generate an error correction code, which is rewritten together with the correction data.

Therefore, in order to correct errors in read data and generate error correction codes for rewriting,
The error correction code generator must be used twice, once for error correction and once for code generation.

A conventional error correction circuit will be described below with reference to the drawings.

FIG. 1 is a block diagram including an example of a conventional error correction circuit. A storage medium M is connected to the output side of the error correction circuit ECC, and a selection circuit S is connected via a register R to the input side. This error correction circuit
The ECC includes an error correction code generator 1, an exclusive OR circuit 2, a data corrector 3, and a register 5.

FIG. 2 is a time chart for explaining the operation of the conventional example shown in FIG.

In the case of a write operation, a write signal k instructing writing
As a result, write data a is selected by selection circuit S and output as data b. This data b, that is, write data a, is supplied to the error correction code generator 1, so the error correction code generator 1 generates the error correction code c. This error correction code c is written to the storage medium M together with the write data a.

In the case of a read operation, first in the error correction period T1,
Read data g and read check bit h read from storage medium M are stored in register R and output as read data i and read check bit j.

This read data i and read check bit j
is used to perform error correction during reading and code generation during rewriting.

First, at the time of reading, the selection circuit S receives the write signal k.
indicates reading, but rewrite signal l does not indicate rewriting. Therefore, the selection circuit S selects read data i from the supplied write data a, read data i, and correction data f and outputs it as data b.

An error correction code generator 1 generates an error correction code c from data b, that is, read data i.

The exclusive OR circuit 2 performs an exclusive OR operation on the error correction code c and the read check bit j, and outputs the syndrome d. Note that since the write signal k does not indicate writing to the exclusive OR circuit 2, the output of the syndrome d is not prohibited.

The data corrector 3 decodes the syndrome d to obtain a correction position, then corrects the data b, that is, the read data i, and outputs the correction data e. This correction data e is stored in the register 5 and output as correction data f.

Next, in the code generation period T2, the write signal k instructs writing, and the rewrite signal l instructs rewriting, so that the error correction circuit ECC enters the state at the time of rewriting. As a result, the selection circuit S selects the corrected data f
is selected and output as data b.

The error correction code generator 1 outputs an error correction code c according to data b, that is, correction data f.

Since the write signal k instructs the exclusive OR circuit 2 to write, the exclusive OR circuit 2 is prohibited from outputting the syndrome.
As syndrome d, a code indicating no error is output. Therefore, the data corrector 3
That is, the corrected data f is output as corrected data e without being corrected.

Therefore, the correction data f and the error correction code c for the correction data f are rewritten in the storage medium M.

In this way, the conventional error correction circuit uses the storage medium M
If there is a correctable error in the read data g and read check bit h read from the read data g and read check bit h, when the error in the read data and read check bit is corrected and the corrected data e and the error correction code c for rewriting are generated, the error is removed. Since the correction takes the error correction period T1 and the generation of the error correction code takes the code generation period T2, it takes the period (T1+T2) to rewrite the read data, and the error correction code generator is used twice. The disadvantage was that the control was complicated and slow.

That is, the conventional error correction circuit has disadvantages in that it takes a long time to rewrite read data and the control is complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide an error correction circuit that can shorten rewriting time and that can be easily controlled.

That is, the object of the present invention is to detect second check bit errors generated from read data in an error correction code generator for 1-bit error correction and 2-bit error detection in the 1-bit error correction 2-bit error detection method that has been most commonly used in the past. The above drawback is solved by exclusive ORing the correction code with the syndrome to generate a write check bit.
The object of the present invention is to provide an error correction circuit that can correct errors in read data and simultaneously generate a write check bit for rewriting.

The error correction circuit of the present invention includes an error correction code generator for 1-bit error correction and 2-bit error detection that generates an error correction code according to written data during writing and according to read data during reading; and a read check bit, and outputs a syndrome when the data is not written; and an exclusive OR circuit that outputs a data correction display signal when the syndrome indicates correction of the read data; a data corrector that corrects the read data according to the syndrome and outputs correction data to be written to a storage medium at the time of rewriting; and a data corrector that corrects the read data according to the syndrome and outputs correction data to be written to a storage medium at the time of rewriting; and an error correction code corrector for generating a write check bit for writing the error correction code as it is in the storage medium at the time of rewriting when the data correction display signal is not supplied. be done.

That is, the error correction circuit of the present invention detects and corrects errors in data read from a storage medium, and performs 1-bit error correction for generating a first check bit for writing and generating a second check bit from read data. An error correction code generator for 2-bit error detection, an exclusive logic circuit that generates a syndrome based on a match or mismatch between a read first check bit and a second check bit, a corrector that corrects errors in read data based on the syndrome, and a syndrome. and an error correction code corrector that inverts the second check bit and generates the first check bit for rewriting, and is configured to generate the first check bit for rewriting at the same time as correcting the read data. .

That is, the error correction circuit of the present invention includes an error correction code generator for 1-bit error correction, 2-bit error detection, which generates a first check bit for writing and a second check bit from read data, and an error correction code generator for generating a first check bit for writing and generating a second check bit from read data; an exclusive logic circuit that generates a syndrome based on the second check bit, a corrector that corrects errors in read data based on the syndrome, and an error correction code that inverts the second check bit using the syndrome and generates the first check bit for rewriting. It consists of a corrector.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram including an embodiment of the present invention. The error correction circuit ECC' shown in FIG. 3 includes an error correction code generator 1 for 1-bit error correction, 2-bit error detection, and , error correction code c
and an exclusive OR circuit 2 that generates syndrome d based on read check bit j, and data that corrects read data i using syndrome d and outputs a data correction display signal m when read data i is corrected. A corrector 3 calculates the exclusive OR of the error correction code c and the syndrome d when the data correction display signal m is supplied to generate a write check bit n, and performs error correction when the data correction display signal m is not supplied. The error correction code corrector 4 uses the code c as it is as the write check bit n.

Next, the detailed operation of the error correction circuit shown in FIG. 3 will be explained with reference to FIG. 4.

First, in the case of a write operation, since a write signal k instructing writing is supplied during the error correction period T1', write data a is selected by the selection circuit S' and data b
The error correction code c is input to the error correction code generator 1, and an error correction code c is output. Data b, that is, write data a, is input to the data corrector 3, and the write signal k
commands writing, syndrome d is not output, and data b, that is, write data a and error correction code C become correction data e and write check bit n during code correction period T2' and are written to storage medium M. It can be done.

Next, in the case of a read operation, the read data g and read check bit h read from the storage medium M during the error correction period T1' are stored in the register R;
The data is output as is as read data i and read check bit j. Since the read data i is instructed to be read by the write signal k, it is selected by the selection circuit S' and inputted to the error correction code generator 1, and the error correction code generator 1 outputs the error correction code c. This error correction code c and read check bit j are inputted to an exclusive OR circuit 2, and an exclusive OR is taken to generate syndrome d. Let us consider a case where the comparison result between the error correction code c and the read check bit j in the exclusive OR circuit 2 matches and a case where they do not match. If they match, it is determined that there is no error in the read data i, and the read data i and the error correction code c can be written to the storage medium M. In the case of mismatch, error correction is possible, that is, in the case of a 1-bit error, there are two possibilities. In the first case, read check bit
The second case is when an error occurs in read data i but no error occurs in read data i, and the second case is when an error occurs in read data i but no error occurs in read check bit j. In the first case, since no error has occurred in read data i, write check bit n
In the second case, since there is no error in the read check bit j, the read check bit j may be used as the write check bit n. When it is determined that the error is correctable due to the syndrome d, the data b, that is, the read data i, is corrected by the data corrector 3, which outputs the corrected data e and a data correction display signal m. Further, during the code correction period T2', the error correction code c is input to the error correction code corrector 4, and when the data correction display signal m is supplied, the write check bit n, which is exclusive ORed with the syndrome d, That is, a read check bit j is output. This write check bit n becomes a write check bit n for rewriting the corrected data that corrects the erroneous read data, and the corrected data and the write check bit for rewriting are generated simultaneously.

By adding an error correction code corrector to the error correction circuit of the present invention, when rewriting read data, instead of using an error correction code generator twice for reading and rewriting. Since the error correction code generator for 1-bit error correction, 2-bit error detection only needs to be used during reading, it has the effect of shortening the time for rewriting and simplifying control.

That is, the error correction circuit of the present invention is an error correction circuit that uses a common error correction code generator for 1-bit error correction, 2-bit error detection, and performs error correction by exclusive ORing an error correction code generated from read data with a syndrome. The use of a code corrector has the advantage that write check bits for rewriting read error data can be generated easily and simultaneously.

[Brief explanation of the drawing]

FIG. 1 is a block diagram including a conventional example, FIG. 2 is a time chart for explaining the operation of the conventional example shown in FIG. 1, FIG. 3 is a block diagram including an embodiment of the present invention, and FIG. The figure is a time chart for explaining the operation of the embodiment shown in FIG. ECC, ECC'...Error correction circuit, M...Storage medium, S, S'...Selection circuit, R...Register, 1...
...Error correction code generator, 2...Exclusive OR circuit, 3...Data corrector, 4...Error correction code corrector, 5...Register, a...Write data, b...
...Data, c...Error correction code, d...Syndrome, e...Correction data, f...Correction data, g
... Read data, h ... Read check bit, i
... Read data, j ... Read check bit, k
...Write signal, l...Rewrite signal, m...Data correction display signal, n...Write check bit.

Claims (1)

[Claims] 1. An error correction code generator for 1-bit error correction, 2-bit error detection, which generates an error correction code according to the written data during writing and according to the read data during reading, and exclusive use of the error correction code and the read check bit. an exclusive OR circuit that calculates a logical sum and outputs a syndrome when the syndrome is not written; and an exclusive OR circuit that outputs a data correction display signal when the syndrome indicates correction of the read data, and also outputs a data correction display signal and inputs the read data to the syndrome. Therefore, a data corrector outputs corrected data to be corrected and written to a storage medium at the time of rewriting, and when the data correction display signal is supplied, an exclusive OR is performed between the error correction code and the syndrome. an error correction code corrector that generates a write check bit for writing the error correction code as it is to the storage medium at the time of rewriting when the data correction display signal is not supplied.