JPS5841499A - Error correction circuit - Google Patents

Abstract

PURPOSE:To decrease the time for rewrite and to simplify the control, by using an error correction code corrector which takes an exclusive logical sum between an error correction code and a syndrome generated from a readout data. CONSTITUTION:A readout data (i) is inputted to an error correction code generator 1 to output an error correction code (c). The error correction code (c) and a readout check bit (j) are inputted to an exclusive OR circuit 2, where a syndrome (d) is generated. The readout data (i) is corrected at a data corrector 3, and a correction data (e) and a data correction display signal (m) are outputted. The error correction code (c) is inputted to an error correction code corrector 4, where a wirte check bit (n) taking an exclusive logical sum with the syndrome (d) is outputted, when the data correction display signal (m) is supplied. This write check bit (m) becomes the write check bit (n) for rewrite, and the corrected data and the write check bit for rewrite can be generated at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an error correction circuit, and particularly to an error correction circuit that corrects read data in a storage device and generates a write check bit for rewriting data.

A conventional error correction circuit includes an error correction code generator that generates an error correction code according to written data when writing, according to read data when rewriting, and spreads to corrected data when rewriting; An exclusive OR circuit that outputs a syndrome if the code and successive check bits are not written as 9, and I! When the fiI syndrome indicates correction of the read data, the subsequent data is corrected in accordance with the '7/drome, and the correction data is read into the storage medium together with the error correction code at the time of rewriting. and a data corrector for outputting data.

In other words, the conventional error p correction circuit generates an error correction code i
t is shared, and if there is a correctable Ap in the read data, it corrects the error in the subsequent data and the read check bit, and generates an error correction code for rewriting.
generates a syndrome from the successive data read from the storage medium and the read check bit at the time of @1 error correction through an error correction code generator using the exclusive OR circuit pressure, and corrects the error in the read data using the syndrome. output the corrected data. In order to correctly rewrite the information stored in the storage medium when the code @2 is generated, the correction data is supplied to an error correction code generator to generate an error correction code, and the correction data is rewritten along with the correction data. Write.

Then, in order to correct the error p in the read data and generate an error correction code for rewriting, K uses the error correction code generator twice, once for the error correction and once for the code generation. There must be.

A conventional error correction circuit will be described below with reference to the drawings.

FIG. 1 is a block diagram including an example of a conventional error correction circuit. The output @IIC of the error correction circuit BCC is connected to a storage medium M, and the input side pressure is connected to a selection circuit S via a register. This error p correction circuit ECC is composed of an error correction code generator 1, an exclusive OR circuit 2, a data corrector 3, and a register 20.

FIG. 2 is a time chart for explaining the operation of the conventional example shown in FIG.

In the case of a write operation, when a write signal k instructing writing is supplied, write data a is selected by a selection circuit S and output as data b. Since this data b, that is, the write data is supplied to the error correction code generator 1,
An error correction code generator 1 generates an error correction code C. This error correction code C is applied to the storage medium MK together with the write data a.
It is written down.

In the case of a read operation, first during the error correction period T1, successive data g and successive check pits h read from storage medium M are stored in register B and output as successive data i and read check bit j.

The read data i and read check bit j are used for error correction during reading and for code generation during rewriting.

First, during successive output, the write signal k instructs the selection circuit S to read, but the rewrite signal l does not instruct rewrite. Therefore, the selection circuit sti selects the read data l out of the write data a, the read data l, and the correction data f supplied to it and outputs it as the data b.

The error correction code generator l generates data b, that is, successive data 1.
An error p correction code c1 is generated from the error p correction code c1.

The exclusive OR circuit 2 performs an exclusive OR operation on the error correcting code C, the readout signal, and the bit j, and outputs the syndrome d. Note that since the write signal k does not indicate writing to the exclusive OR circuit 2, the output of the syndrome -m d is not prohibited.

The data corrector 3 decodes shift draw and mudi to obtain a correction position, then corrects data b, that is, read data kl, and outputs correction data e. This correction data e is stored in the register 5 and output as correction data f.

Next, in the code generation period T2, the write signal instructs writing, and the rewrite signal l instructs rewriting, so that the error correction circuit F20C enters the state at the time of rewriting. After this, the selection circuit S selects the corrected data f and outputs it as data b.

The error correction code generator 1 generates data b, that is, correction data f.
An error correction code C according to the following is output.

Since the write signal k instructs the exclusive OR circuit 2 to write, the exclusive OR circuit 2 is prohibited from outputting the syndrome, and the syndrome d
, a code indicating no error is output. For this reason,
The data corrector 3 outputs the data b, that is, the corrected data fi, as corrected data e without being corrected.

Therefore, the correction data f and the error correction code C for this correction data f are rewritten in the storage medium MK.

In this way, when there is a correctable error in the successive data g and read check bit h read from the storage medium M, the conventional error correction circuit corrects the error in the read data and read check pit, and corrects the corrected data e and the read check bit h. When generating the ninth error correction code C for rewriting, the error correction takes only the error correction period T1, or the generation of the error correction code takes the code generation period T2, so it is difficult to rewrite successive data. It takes a period of (Tl+T2), and since the error correction code generator is used twice, the control is complicated and slow.

That is, the conventional error correction circuit has disadvantages in that it takes a long time to rewrite successive data and the control is complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide an error correction circuit that reduces rewriting time and facilitates control.

That is, an object of the present invention is to solve the above-mentioned drawbacks by generating write check bits by exclusive ORing the second check bit error correction code generated from successive data with the syndrome in the error correction code generator. death,
An object of the present invention is to provide an error correction circuit that can generate a write check bit for rewriting simultaneously with error correction of read data Q.

The oiA, o correction circuit of the present invention includes an error correction code generator that generates an error correction code according to written data during writing and according to successive data when writing, Exclusive OR with check bit?An exclusive OR circuit that outputs a syndrome in color if it is not written, and outputs a data correction indication signal when the syndrome indicates correction of the successive data. a data corrector that corrects the successive data according to the syndrome and outputs corrected data to be written to a storage medium at the time of rewriting; and an error correction code that operates when the data correction display signal is supplied. When the data correction indication signal is not supplied, K uses the error correction code as it is at the time of rewriting l!t.
and an error correction code corrector that generates write check bits for writing to the storage medium.

That is, the error correction circuit of the present invention detects and corrects errors in data read from a storage medium, and generates a first check bit for writing and detects a second check bit from successive data. An exclusive logic circuit that generates a syndrome based on a match or mismatch between an error correction code generator and a read first check bit and second check bit, a corrector that corrects an error p in read data based on the syndrome, and a syndrome. inverts the second check bit by
and an error correction code corrector which generates a first check bit for rewriting f), and is configured to generate a first check bit for rewriting at the same time as the successive data is corrected.

In other words, the error correction circuit of the present invention includes an exclusive logic circuit that generates a syndrome by generating a first check bit for write and read data or a check bit, a corrector that corrects errors in successive data by the syndrome, and a second error correction circuit by the syndrome. invert the check bit of
and an error correction code corrector that generates a first check bit for rewriting.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

Is Figure 3 an implementation of the present invention? In the block diagram including 1Jt'',
The error correction circuit ECC' shown in FIG. A circuit 2, and a data corrector 3 which corrects successive data l according to syndrome d and outputs a data correction indication signal mf to indicate that read data l has been corrected.

The error correction code corrector 4 performs an exclusive OR of the error correction code C and the syndrome d to generate a write check signal n when the data correction display signal m is supplied.

Next, the detailed operation of the error correction circuit shown in FIG. 3 will be explained with reference to FIG.

/First, in the case of a write operation, a write signal k instructing writing is supplied during an error correction period Tl'', so write data a is selected by the selection circuit S' and an error correction code is generated as data pb. The error p-correcting code C is inputted to the device l and outputted.

Data b, that is, write data a, is input to the data corrector 3, and since the write signal k instructs writing, syndrome d is not output, and data b, that is, write data a and error correction code C are code corrected. In the period T21, the correction data C and the write check pin become n, and the storage medium M
KiF is included.

Next, in the case of a read operation, the successive data g and successive chip pit h read from the storage medium M during the error/correction period T11 are stored in the register BE, and until that time, the read data i, @out check, firing, and Output as j. Since the successive data l is read out by the write signal k, the selection circuit S
The error correction code C is selected by I and input to the error correction code generator 1, which outputs an error correction code C. The error correction code C and successive checked bits j are input to the exclusive OR circuit 2, and are exclusive ORed to generate syndrome d. If it is determined that the error is correctable due to the syndrome d, the data b, that is, the read data iVi is corrected by the data corrector 3, and the data corrector 3 outputs the corrected data e and also outputs the data correction display signal m. . In addition, the code correction period T21
When the error correction code C is input to the error correction code corrector 4 and the data correction display signal m is supplied, the error correction code C is exclusive ma! with the syndrome d. Sum is taken and 1 check bit ml
Output. This write check bit n becomes a write check pit n for rewriting the corrected data that corrects the erroneous successive data, and the corrected data and the write check pit for rewriting are generated simultaneously.

By adding an error correction code correction @, the Q error correction circuit of the present invention can replace the need to use an error correction code generator twice, once for successive data and once for rewriting, when rewriting successive data. Since the error correction code generation station only needs to be used when successive occurrences occur, the rounding time for rewriting can be shortened and the control can be made more efficient.

That is, the error correction circuit of the present invention uses an error correction code corrector that takes the exclusive OR of the error correction code generated from successive data with the syndrome in the error p correction circuit that shares the error correction code generator. This has the effect of easily and simultaneously generating write holes for rewriting erroneously read data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram including a conventional example; FIG. 2 is a time chart for explaining the operation of the conventional example shown in FIG. 1;
FIG. 3 is a block diagram including an embodiment of the present invention, and FIG. 4 is a time chart for explaining the operation of the embodiment shown in FIG. Ecc, Ecct...Error correction circuit, M...
...Storage medium, s, s'...Selection circuit, R
... Register, 1 ... Error correction code generator, 2 ... Exclusive OR circuit, 3 ... Data corrector, 4 ... error correction code corrector, 5.
...Register, a...Write data, b...Data, C
...Error correction code, d...Syndrome, e. Old...Correction data, f...Correction data, g...Read data, h. ...Reading check pit, i...Continuing data, j...
ゞ...Read check pit, k...Write signal,! ...Rewrite signal, m...Data correction display signal, n...Write check pit.

Claims (1)

[Claims] an error correction code generator that generates an error correction code according to written data when writing and according to read data when continuing;
Exclusive 81 of the error correction code and successive check bits
an exclusive OR circuit that calculates the sum of i1 and outputs a syndrome when the data is not written; and an exclusive OR circuit that outputs a data correction display signal when the syndrome indicates correction of the read data; a data corrector that corrects according to the syndrome and outputs correction data for writing one story into a storage medium at the time of rewriting, and exclusion of the error p correction code and the syndrome when the data correction cost indication signal is supplied. and an error correction code corrector that performs a logical sum and generates a write check bit for writing the error correction code as it is to the storage medium at the time of rewriting when the data correction display signal is not supplied. An error correction circuit characterized by: