JPS623323A - Conversion system for data format - Google Patents

Abstract

PURPOSE:To decrease the number of input/output holding circuits as well as the number of signals delivered among circuits, by converting a signal line into a bus and the holding circuit into a RAM and repeating the reading actions with the same RAM and also the writing actions via a switch gate circuit. CONSTITUTION:The >=2 pairs of data where the integer multiples of the number of minimum parallel bits are defined as a pair with parallel 2 bits defined as the minimum unit are written to a RAM circuit 2 as an input. The data to be converted within the circuit 2 is read out and the conversion of format is carried out for change of distribution for each OR and AND of bits or minimum unit of bits between input data or between the input data and the old input data through a logic gate circuit 1 and a holding circuit 4. Then data are written again to the circuit 2. This action is repeated by times equivalent to the number of pairs of the minimum parallel unit bits forming a pair of data. Thus the output data is held and >=1 pairs of different formats are delivered.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data format conversion method, particularly a method that inputs multiple parallel data and performs logical operations and rearrangement between bits of the data to produce output data. Regarding data format conversion method.

[Conventional technology]

A circuit diagram of a conventional data format conversion circuit corresponding to an embodiment of the present invention is shown in FIG. First, multiple inputs 8
Bit data is divided into upper 4 bits and lower 4 bits and held in a 4-bit memory path 6 for input data by control signals 101, 102, and 111 from a control signal generating circuit 10, respectively. Next, in order to convert the data format between input and output, the input data held in the 4-bit memory circuit 6 is sent to the 4-bit OR circuit 7S and the 4-bit switching gate circuit 8.
data is imported and the data format is converted. Next, the data after data format conversion is transferred to the control signal generation circuit 10.
The output data is held in the 4-bit memory circuit 9 by control signals 105, 111, and 112 from the output data. Control signals 106, 113, 11 from the control signal generation circuit 10
4, the 4-bit gate circuit 11 is switched to output a plurality of output data 8 bits at a time in a time-division manner.

In other words, the circuit configuration includes independent holding circuits on the input side and output side, and an arithmetic processing circuit for converting the data format between the input and output. needed a circuit.

[Problem that the invention seeks to solve]

The above-mentioned conventional data format conversion method has disadvantages in that a holding circuit is not provided for each parallel output data, the number of circuits is large, and the number of signals between circuits is large due to the parallel data.

Another drawback is that the circuit configuration changes every time the combination of person and output data changes.

[Means for solving problems]

According to the present invention, in a data format conversion circuit that inputs multiple bits of parallel data and converts the format according to the input data, the data input operation and the conversion output operation are asynchronous, and the minimum unit is two or more parallel bits, and the minimum unit is the parallel bit. Input two or more sets of data, each set being an integer multiple of a number, write them into a random access memory circuit, read out the converted data in the random access memory circuit,
Through the logic gate circuit and the holding circuit, format conversion is performed between the input data or between the input data and the old input data, such as bit logical sum, logical product, or arrangement change for each minimum unit parallel bit, and the data is returned to the random access memory circuit. A data format conversion method is obtained in which the write operation is repeatedly performed for the number of sets of minimum unit parallel bits constituting one set of data, and the data is held as output data, and the output of one or more sets of different format data is an enemy.

In other words, the data format conversion method of the present invention converts the signal line into a bus in order to eliminate the number of input/output holding circuits and the number of signals between the circuits, converts the holding circuit into a RAM, and converts the holding circuit into a RAM.
Measures are taken to repeat reading from and writing to through the switching gate circuit.

Further, conversion of bit positions in units of n bits and logical operations on bits are realized by repeating reading to the RAM and writing via the switching gate circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention when n=4 bits. The embodiment shown in FIG. 1 includes a 4-bit switching gate circuit 1 for switching between input data and data before format conversion, a 4-bit RkM circuit 2 for temporarily storing input (before conversion) data and output (after conversion) data. 4
Bit memory circuit 3. 4-bit operation processing and holding circuit 4
and a control iphone signal generation circuit 5.

FIGS. 2 and 3 show explanatory diagrams and time charts of format conversion in the embodiment shown in FIG. 1.

The basic operation of the embodiment shown in FIG. 1 will be explained below. 8
4 sets of bit length input data (&B, CD.

E(1)F■, E@F■) is passed through the 4-bit switching gate circuit 1 by the switching signal 11.12 from the control signal generation circuit 5 in units of 4 bits, and is transferred to the 4-bit RAM circuit via the data bus 101. In response to the write signal 19 from the control signal generation circuit 5, the data is stored in the area determined by the RAM address designation signals 15 to 18 from the control signal generation circuit 2. Next, the pre-conversion data specified by addresses 15 to 18 are read out by the read signal 20 from the control signal generation circuit 5, and held in the 4-bit memory circuit 3 by the write signal 21 from the control signal generation circuit 5. Next, addresses 15 to 1 are designated by the successive signal 20 from the control KI signal generation circuit 5.
The pre-conversion data C specified by 8 is read out from the 4-bit R, AM circuit, and the data bus 102 is input to the purely 4-bit arithmetic processing and holding circuit 4.

Here, the data stored in the 4-bit memory circuit 3 is logically summed, and the result is held in the 4-bit arithmetic processing and holding circuit 4 by the pledge signal 22 from the control signal generation circuit 5. Then, the output is passed through the 4-bit switching gate circuit 1 by the switching signal 14 from the control signal generation circuit 5, and is then sent to the 4-bit laAM circuit 2 as the area error ζ write signal 19 specified by the at 1/s specifications 15 to 18. Stored by

Here, as a result of the logical sum of the pre-conversion data A and C, data G is stored in the post-conversion memory area.

Next, in the same manner as described above, the converted data I and K are stored in the 4-bit RAM circuit 2 as a result of the logical sum of the pre-converted data E■ and E■.

Next, the pre-conversion data B designated by address designations 15 to 18 is output from the control signal generation circuit 5 by No. 13 No. 20.
The 4-bit memory circuit 3 is read by writing No. 1 21.
to hold. The output data passes through the 4-bit switching gate circuit 1 on the data bus 105 in response to the switching signal 13, and is stored in the area designated by the address 1/pass designations 15 to 18 in response to the input signal 19. Next, address specification 15
Read the post-conversion data G specified by ~18 and send the signal 20.
Then, the data is output as the upper 4 bits via the read data bus 106, and at the same time, data B held in the 4-bit memory circuit 3 is sent out as the lower 4 bits.

Next, the pre-conversion data D is read out in the same manner as described above, and output as the lower 4 bits simultaneously with the upper 4 bits of data G. In other words, here, the upper 4 bits are data A and C.
The logical sum of the lower 4 bits is output as data that changes to data B or D depending on time.

In the same way, the pre-conversion data F■ is read out and stored in the 4-bit memory circuit 3, and then the post-conversion data I is output one after another, so that data I is output as the upper 4 bits and -C data F■ is output as the lower 4 bits. .

Furthermore, the same holds true when outputting data F1 as the upper 4 bits and 1 as the lower 4 bits.

In this example, n == 4 bits and all 4 arbitrary bits are ORed, but other than 4 bits may also be used.
Even when the number of bits in a logical operation is not all bits, it is possible to convert the data format using the same concept as in this embodiment.

In this practical example, the bit configuration of input/output data is 8 bits, but the format conversion of all input/output data that is an integer multiple of 4 bits is the same, with only a change in the control signal generation circuit of this embodiment. This can be realized by circuit configuration.

〔Effect of the invention〕

As explained above, the present invention enables the format conversion of multiple input/output data having a bit configuration that is an integer multiple of n pits, all using the same circuit, which greatly reduces the number of circuits and shortens the design period. This has the effect of achieving significant shortening.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of the present invention, Fig. 2 is an explanatory diagram showing an example of data format conversion, Fig. 43 is a time chart showing the operation of Fig. 1, and Fig. 4 is a diagram of the conventional circuit. FIG. 2 is a block diagram showing an example. 1...4-bit switching gate circuit, 2...
・4-bit RAM circuit, 3...4-bit memory circuit, 4...4-bit arithmetic processing and holding circuit,
5... Control signal generation circuit. -To B and Nido-, intersection 1-mo Fig. 4

Claims (1)

[Claims] In a data format conversion circuit that inputs multiple bits of parallel data and converts the format according to the input data, the data input operation and conversion output operation are asynchronous,
In addition, two or more sets of data in which the minimum unit is two or more parallel bits and one set is an integer multiple of the minimum unit parallel bit number are input and written to the random access memory circuit, the data to be converted in the random access memory circuit is read, and the logic Through the gate circuit and the holding circuit, format conversion is performed between the input data or between the input data and the old input data, such as bit logical sum, logical product, or rearrangement change for each minimum unit parallel bit, and then written to the random access memory circuit again. A data format conversion method characterized in that an operation is repeatedly performed for the number of sets of minimum unit parallel bits constituting one data set, and the data is held as output data and one or more different format data sets are output.