JPS6233348Y2 - - Google Patents
Info
- Publication number
- JPS6233348Y2 JPS6233348Y2 JP6892880U JP6892880U JPS6233348Y2 JP S6233348 Y2 JPS6233348 Y2 JP S6233348Y2 JP 6892880 U JP6892880 U JP 6892880U JP 6892880 U JP6892880 U JP 6892880U JP S6233348 Y2 JPS6233348 Y2 JP S6233348Y2
- Authority
- JP
- Japan
- Prior art keywords
- fet
- source
- rectifying element
- gate
- bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000006378 damage Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000009429 electrical wiring Methods 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
Landscapes
- Protection Of Static Devices (AREA)
- Amplifiers (AREA)
Description
【考案の詳細な説明】
本考案は、FET保護回路、特に、GaAs−FET
への電源投入および切断時における電源電圧過度
応答などによるGaAs−FET素子の破壊を防止す
るためのFET保護回路に関する。[Detailed description of the invention] The present invention is a FET protection circuit, especially a GaAs-FET protection circuit.
This invention relates to a FET protection circuit for preventing destruction of GaAs-FET elements due to power supply voltage transient response when power is turned on and off.
一般に、FET、例えば超高周波能動素子とし
て用いられるGaAs−FETはゲート・ソース間電
圧を常に逆バイアスで使用しなければならない。
すなわち、Ｎチヤネルの場合にはゲート電位がソ
ース電位より高くなると、またＰチヤネルの場合
ゲート電位がソース電位より低くなると破壊され
てしまう。また、ゲート・ソース間電圧を逆バイ
アスとするために二種類の電源電圧が必要とな
り、この二種類の電源の投入（あるいは切断）の
順序、過渡応答、電源電圧の異常等に対して
GaAs−FETを保護するためのFET保護回路が必
要となる。 Generally, FETs, such as GaAs-FETs used as ultra-high frequency active devices, must always be used with a gate-source voltage in reverse bias.
That is, in the case of an N-channel, if the gate potential becomes higher than the source potential, and in the case of a P-channel, if the gate potential becomes lower than the source potential, it will be destroyed. In addition, two types of power supply voltages are required to reverse bias the voltage between the gate and source, and the order of turning on (or turning off) these two types of power supplies, transient response, abnormalities in the power supply voltage, etc.
A FET protection circuit is required to protect the GaAs-FET.
従来のFET保護回路は、第１図に示すように
FETのゲートとソースと直接接続されるソース
接続回路であるソース回路電源３との間に整流素
子５を逆方向バイアスが加わるように接続してゲ
ート・ソース間の逆バイアスを保つている。 The conventional FET protection circuit is as shown in Figure 1.
A rectifying element 5 is connected between the source circuit power supply 3, which is a source connection circuit directly connected to the gate and source of the FET, so as to apply a reverse bias to maintain the reverse bias between the gate and the source.
しかし、実際には、この整流素子５は第２図に
示すように順方向抵抗が存在するために、二種類
の電源の状態によつて整流素子５が順方向にバイ
アスされることがあり、この場合には、電圧降下
を生じ、GaAs−FETのバイアス状態は破壊領域
の一部に突入してしまうという欠点がある。 However, in reality, since the rectifying element 5 has a forward resistance as shown in FIG. 2, the rectifying element 5 may be biased in the forward direction depending on two types of power supply states. In this case, there is a drawback that a voltage drop occurs and the bias state of the GaAs-FET enters a part of the breakdown region.
本考案の目的は、FETに加えられる複数の電
源の投入・切断状態にかかわらず、FETの破壊
が防止できるFET保護回路を提供することにあ
る。 The purpose of the present invention is to provide a FET protection circuit that can prevent destruction of the FET regardless of whether multiple power supplies are applied to the FET.
本考案のFET保護回路は、FETのゲートとソ
ース接続回路の間に逆方向にバイアスが加わるよ
うに接続された第１の整流素子と、前記FETの
ソースと前記ソース接続回路との間に逆方向にバ
イアスが加わるように接続された第２の整流素子
を含んで構成される。 The FET protection circuit of the present invention includes a first rectifying element connected to apply a bias in the opposite direction between the gate of the FET and the source connection circuit, and a reverse connection between the source of the FET and the source connection circuit. It is configured to include a second rectifying element connected so as to apply a bias in the direction.
次に、本考案の実施例について図面を参照して
説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第３図は本考案の一実施例を示す電気結線図
で、FET８のゲートとソース接続回路であるソ
ースバイアス電源３との間に整流素子５を逆方向
バイアスが加えられるように接続するとともに、
FET８のソースとソースバイアス電源３との間
に整流素子６を順方向バイアスが加えられるよう
に接続している。 FIG. 3 is an electrical wiring diagram showing an embodiment of the present invention, in which a rectifying element 5 is connected between the gate of an FET 8 and a source bias power supply 3, which is a source connection circuit, so as to apply a reverse bias.
A rectifying element 6 is connected between the source of the FET 8 and the source bias power supply 3 so as to apply a forward bias.
このような構成により電源電圧の状態によつて
整流素子５が順方向にバイアスされて電圧降下が
生じた場合でも、整流素子６の順方向バイアスに
よる電圧降下と相殺されて、GaAs−FETなどの
FET８のゲート・ソースの電位関係は逆バイア
ス状態に保たれ破壊領域への突入を防ぐことがで
きる。 With this configuration, even if the rectifying element 5 is forward biased depending on the power supply voltage state and a voltage drop occurs, the voltage drop due to the forward bias of the rectifying element 6 is canceled out, and the voltage drop due to the forward bias of the rectifying element 6 is canceled out.
The potential relationship between the gate and source of FET 8 is maintained in a reverse bias state to prevent entry into the breakdown region.
すなわち、第３図に示すように二種類の電源電
圧の過渡応答、短絡などの電圧異常によつて整流
素子５が順方向にバイアスされた場合でも、整流
素子６が順方向にバイアスされているため、整流
素子５、および６の電圧降下が相殺して、ゲート
電位はソース電位を超えることはない。通常の
GaAs−FET回路ではドレイン電流はゲートバイ
アス回路の電流より大きいため、整流素子６の電
圧降下は整流素子５の電圧降下より大きく、ゲー
ト・ソース間電圧は充分な逆バイアスに保たれ
る。 That is, as shown in FIG. 3, even if the rectifying element 5 is biased in the forward direction due to a voltage abnormality such as a transient response of two types of power supply voltages or a short circuit, the rectifying element 6 is biased in the forward direction. Therefore, the voltage drops of rectifying elements 5 and 6 cancel each other out, and the gate potential never exceeds the source potential. normal
In the GaAs-FET circuit, the drain current is larger than the current in the gate bias circuit, so the voltage drop across rectifying element 6 is larger than the voltage drop across rectifying element 5, and the gate-source voltage is maintained at a sufficient reverse bias.
本考案のFET保護回路は、ゲート・ソース間
の逆バイアス整流素子の他にソースとソース接続
回路との間に順方向に整流素子を追加することに
より、FET破壊領域への突入の危険性をなく
し、常にゲート・ソース間の逆バイアスが確保で
きるため、破壊が防止できるという効果がある。 The FET protection circuit of this invention eliminates the risk of entering the FET destruction region by adding a forward rectifier between the source and the source connection circuit in addition to the reverse bias rectifier between the gate and source. Since the reverse bias between the gate and source can always be ensured, destruction can be prevented.
第１図は従来の一例を示す電気結線図、第２図
は第１図に示す整流素子の電圧−電流特性を示す
特性図、第３図は本考案の一実施例を示す電気結
線図である。
１……信号入力、２……信号出力、３……ソー
ス回路電源、４……ゲートバイアス電源、５，６
……整流素子、７……FET、R1，R2，R3……バ
イアス用抵抗。
Fig. 1 is an electrical wiring diagram showing a conventional example, Fig. 2 is a characteristic diagram showing voltage-current characteristics of the rectifying element shown in Fig. 1, and Fig. 3 is an electrical wiring diagram showing an embodiment of the present invention. be. 1... Signal input, 2... Signal output, 3... Source circuit power supply, 4... Gate bias power supply, 5, 6
... Rectifying element, 7... FET, R 1 , R 2 , R 3 ... Bias resistance.
Claims (1)
向バイアスが加わるように接続された第１の整流
素子と、前記FETのソースと前記ソース接続回
路との間に順方向バイアスが加わるように接続さ
れた第２の整流素子とを含むことを特徴とする
FET保護回路。 a first rectifying element connected to apply a reverse bias between the gate of the FET and the source connection circuit; and a first rectifier connected to apply a forward bias between the source of the FET and the source connection circuit; and a second rectifying element.
FET protection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6892880U JPS6233348Y2 (en) | 1980-05-20 | 1980-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6892880U JPS6233348Y2 (en) | 1980-05-20 | 1980-05-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56169559U JPS56169559U (en) | 1981-12-15 |
| JPS6233348Y2 true JPS6233348Y2 (en) | 1987-08-26 |
Family
ID=29662855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6892880U Expired JPS6233348Y2 (en) | 1980-05-20 | 1980-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6233348Y2 (en) |
-
1980
- 1980-05-20 JP JP6892880U patent/JPS6233348Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56169559U (en) | 1981-12-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3229809B2 (en) | Semiconductor device | |
| JPH0265625A (en) | Electronic circuits protected against power battery polarity reversal | |
| JPH10229639A (en) | Integrated supply protection | |
| US4581551A (en) | Input/output circuit for use with various voltages | |
| JP2001224135A (en) | Load drive | |
| US4441035A (en) | CMOS Turn-on circuit | |
| JP3022861B1 (en) | Input circuit of DC-DC converter | |
| JPH0244413A (en) | Constant current supply circuit | |
| US4725912A (en) | Power MOS loss of ground protection | |
| JP3226002B2 (en) | Circuit device having a backflow prevention circuit | |
| JPH0548021A (en) | Semiconductor protective circuit | |
| JP2525450Y2 (en) | Reverse connection protection circuit | |
| EP0519156A1 (en) | Ground loss protection device particularly for mos integrated circuits | |
| JPH0379120A (en) | Input protecting circuit | |
| JP2752680B2 (en) | Overvoltage absorption circuit of semiconductor integrated circuit device | |
| JP3192437B2 (en) | Short circuit protection circuit for power supply IC | |
| JP2658386B2 (en) | Overcurrent detection circuit | |
| JPH0613553A (en) | Semiconductor integrated circuit | |
| JP3455001B2 (en) | Semiconductor device | |
| JPS62109114A (en) | Voltage regulator | |
| JP3313324B2 (en) | Automatic switch circuit for applying power to the load with the correct polarity regardless of the connection polarity of the power supply | |
| JPS60244105A (en) | Amplifier circuit | |
| JPH0118587B2 (en) | ||
| JPH055698Y2 (en) | ||
| JPH0127286Y2 (en) |