JPS6233398A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To avoid a meaningless writing and shorten a writing time by performing only one of an erasing operation and a writing operation to a memory cell array by a control means when a logic condition of the data of a prescribed unit is specific as a result of the inspection. CONSTITUTION:All bits of a byte to write the data of one selected page in a memory cell array are erased. Bits of '0' in the data to be written in the memory cell array 1 are programmed. Thereafter, an internal writing cycle B' is completed. When all input data is '1', only an erasing operation of the memory cell array 1 is executed, and when all the input data is '0', only a program operation of the memory cell array 1 is executed. Thereby, when all the input data is '1' or '0', either one operation may be performed and the writing operation can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to an EEPROM capable of so-called page writing.

[Prior Art] EEPROM is a programmable ROM in which data can be electrically rewritten. For example, when data "1" is written, an erase operation is performed, and when data rOJ is written, a program operation is performed.

Since the EEPROM described above takes a long time to write data, it takes a long time to write data for each unit memory cell. For this reason, EEPROM employs a page write mode.

This page write mode consists of one
This is a mode in which one page's worth of data is temporarily stored in a latch means inside the EEPROM, and then the stored data is written in the memory cell array all at once.

According to this page write mode, the write time can be significantly reduced, so it is very effective for devices such as EEPROMs that require a long write time.

FIG. 2 is a block diagram showing a schematic configuration of a page-writable EEPROM. In the figure, a memory cell array 1 has a configuration in which a plurality of unit memory cells are arranged in a matrix along the row and column directions. The row address bank 77♂ is for temporarily storing a row address given from the outside (for example, the CPU).

The output of this row address buffer 3 is applied to a row decoder 4, decoded, and then applied to the memory cell array 1. Column address buffer 5 is for temporarily storing column addresses from outside. The output of column address buffer 5 is applied to column decoder 6, decoded, and then applied to column latch 7. A data input buffer 8 is connected to this column latch 7 . The data input buffer 8 is for temporarily storing data applied from the outside (data to be written to the memory cell array 1). The column latch 7 transfers the data stored in the data manual buffer 8 to the column decoder 6.
It is used to temporarily store the byte specified by . The output of column latch 7 is memory cell array 1
given to.

The control circuit 9 is for controlling the operation of each circuit included in the EEPROM.

FIG. 3 is a flowchart for explaining the operation of the EEPROM shown in FIG. 2. The operation of the EEPROM shown in FIG. 2 will be explained below with reference to FIG.

In FIG. 3, the part A surrounded by the dotted line shows an external write cycle, that is, the operation of temporarily storing data from the outside, and the part B shows the internal write cycle, that is, the operation in which data is actually stored in the memory cell array 1. This shows the operation of writing . First, regarding external write cycle A, in the first step S1, a row address input from the outside to a row address pin (not shown) is taken into the row address buffer 3, and in response to the output of the row address buffer 3, the row decoder 4 One page 2 in the memory cell array 1 is selected. Next, in step S2, a column address externally applied to a column address pin (not shown) is taken into the column address buffer 5, and upon receiving the output of the column address buffer 5, a column decoder 6 selects one byte. Next, in step S3, data provided from the outside to a data pin (not shown) is taken into the data manual buffer 8, and the output of this data input buffer 8 is converted into the 1 byte selected in step S2.

Write to column latch 7. In addition, on the actual device,
The operations of steps Sl, 82.83 are processed in parallel. Further, the operations of steps $2 and $3 are treated as one cycle, and these operations are repeated until the external write cycle is completed. Note that if only one byte of data is to be written in one selected page, the operations of steps $2 and S3 only require one cycle. When the above external write cycle A ends, the process moves to internal write cycle B.

In internal write cycle B, the EEPROM is disconnected from the outside. First, in step S5, all bits of the byte selected in step $2 in the 1 page selected in step S1 are erased regardless of the content of the input data (that is, data "1" is added to page 2).
).

Next, in step S6, a program is performed on the rOJ pit among the data written to the column latch 7 in the external write cycle A (that is, data "0" is written into the corresponding pit on the page 2). . In this way, for any input data, page 2 is first erased, and then page 2 is programmed. In addition,
Control circuit 9 controls these series of write operations.

By the above operation, all bits in a predetermined column in page 2 selected in the external write cycle are set to "1" or "
0" data will be written.

[Problems to be Solved by the Invention] Since the conventional EEPRO is configured as described above, for example, even when the input data is all "0", the selected byte is not written in the internal write cycle B. All pills
(delete "1" into ~), then write "1" to all the bits again.
0" was written. However, EEPROM
Since writing takes a very long time, it is desired to shorten the time, and it is necessary to avoid meaningless writing in the above-mentioned cases.

The present invention has been made to solve the above-mentioned problems, and its object is to provide a semiconductor memory device that can avoid meaningless writing and shorten the write time.

In order to solve the above problem, a semiconductor memory device according to the present invention is provided with a logic state detection means and a control means, and is configured to detect the logic of a predetermined unit of data before restoring the predetermined unit of data to a memory cell array. The state is detected by a logic state detection means, and as a result of this detection, if the logic state of a predetermined unit of data is a specific state,
The control means performs only one of the erase operation and the write operation to the memory cell array.

[Operation] In the present invention, when the logic state of a predetermined unit of data to be written to the memory cell array is all O or all 1, the control means performs either an erase operation or a data write operation to the memory cell array. By performing only this, unnecessary operations performed in conventional semiconductor memory devices can be omitted.

[Real Example] Hereinafter, an embodiment of the present invention will be described, but before that, an outline of this example will be explained. In the embodiment described below, in the internal write cycle, all input data is
If the input data is "1", only erasing of the memory cell array is performed, and if all input data is "0", only programming operation is performed. As a result, if all input data have the same logical state, 111J! The internal write cycle is completed by writing , and the conventional EEFROM
This eliminates the unnecessary write operations that were previously performed.

Next, a configuration of an embodiment of the present invention will be described. E
The basic circuit hItIi of the EPROM may be the same as that shown in FIG. Therefore, one embodiment of the present invention will be described with reference also to FIG. In one embodiment of the invention, the second
In addition to the configuration shown in the figure, logic state detection means shown in FIG. 2 is added. This logic state detector 〇 is for detecting the logic state of input data.

In FIG. 4, input data to be written into the memory cell array 1 is applied to the input terminal 10 in parallel Mai.

This input data is applied to column latch 7 and also to OR gates 1 to 11 and NAND gate 12. The output of OR gate 11 is applied to latch 13. The output of NAND gate 12 is applied to latch 14. A set signal is applied to these latches 13 and 14 from a set signal input terminal 15. This set signal is generated by control circuit 9 in FIG. 2, and latches 13 and 14 are set before data is input to input terminal 10.

The output of latch 13 is given to output terminal 16.

The output of latch 14 is applied to output terminal 17.

These output terminals 16 and 17 are connected to a control circuit 9.

Next, the operation of the circuit shown in FIG. 4 will be explained. Input terminal 10
If the data input to contains "1", the output of OR gate 11 becomes rl-IJ, and 7f73, which has already been set by the set signal, becomes OR gate 24.
The output signal of latch 13 is reset by the output of r
Become LJ. Furthermore, if the data input to the input terminal 10 contains "0", the output of the NAND gate 12 becomes rHJ, and the launch 14, which has already been set by the set signal, is reset by the output of the NAND gate 12. The output signal of the latch 14 becomes rLJ. That is, if all input data is rOJ, the output of latch 13 will be rHJ, and the output of latch 14 will be rLJ.

Furthermore, if the input data is all "1J", the output of latch 13 will be rLl, and the output of latch 14 will be rHJ. If the input data includes both rIJ and "0", then latches 13 and 14 will Both outputs become "L".

Therefore, depending on the level state of the output signals of the latches 13 and 14 led to the output terminals 16 and 17,
The logical state of input data can be known. The controller circuit 9 controls the operation of the internal write cycle based on the detection result of the logic state detection means shown in FIG.

FIG. 1 is a flowchart for explaining the operation of an example of the present invention. The operation of one embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, external write cycle A is similar to the conventional example shown in FIG. In internal write cycle B-,
First, in step S8, all the input data for one page loaded into the column latch 7 in external write cycle A is "1".
”. This determination is made based on the output of the logic state detection means shown in FIG. if,
If all the input data are "1", the process advances to step S9, and all pits of the byte into which 1 data is to be stored in the selected page of the memory cell array 1 are erased.

That is, "1" is written to all the relevant bits. The operation in step S9 is similar to the operation in step S5 in FIG. Thereafter, the process proceeds to step 814, and the internal 1-inclusive Nicle B- is ended.

On the other hand, if the determination in step S8 is rNOJ, the process advances to step S10, and it is determined whether all input data are "0". This determination is made based on the detection result of the logic state detection means shown in FIG. 4, similar to the determination in step S8. If all input data is rOJ,
Proceeding to step 811, all pits of the byte into which data is to be written in the selected one page in the memory cell array 1 are programmed. In other words, all pits have r
Write OJ. Thereafter, the process advances to step S''14 and the internal write cycle 8- is completed.

On the other hand, if the determination in step S10 is rNOJ, the third
The same operation as in the conventional example shown in the figure is performed.

That is, first, in step 812, all pits of a byte in which data is to be written in one selected page of the memory cell array 1 are erased.

Then, the process advances to step 813, and the data to be written into the memory cell array 1 programs the pit of rOJ. Thereafter, the process advances to step 814 and the internal write cycle B- is ended.

As mentioned above, in this embodiment, all input data is
If the input data is rOJ, only the erase vJ operation of the memory cell array 1 is performed, and if the input data are all rOJ, only the program operation of the memory cell array 1 is performed. by this,
Pointless write operations can be omitted, and the write time is
! JIIilization can be achieved. That is, in the conventional example, two steps S5 and S6 are performed depending on the content of the input data, but in this practical example, if the input data is all "1" or all "0", step It is sufficient to perform only one step, either the operation of S9 or the operation of step 811, and the I-in operation can be shortened.

[Effect of the invention 1 As described above, according to the present invention, when the input data is in a specific ethical state, the internal writing operation is completed in one time, so that the writing time can be shortened. This has the effect of increasing the number of times memory cells can be replaced.

[Brief explanation of the drawing]

FIG. 1 is a flowchart for explaining the operation of one embodiment of the present invention. FIG. 2 is a block diagram showing a schematic configuration of a conventional EEFROM. FIG. 3 is a flow chart for explaining the operation of the conventional circuit shown in FIG. FIG. 4 is a circuit diagram showing an example of logic state detection means provided in an embodiment of the present invention. In the figure, 1 is a memory cell array, and 3 is a row address buffer. , 4 is a row decoder, 5 is a column address buffer? , 6 is a column decoder, 7 is a column latch, 8 is a data manual buffer, 9 is a control circuit, 10 is an input terminal, 11 is an OR gate, 12 is a NAND gate, 13
and 14 is a latch, 15 is a set signal input terminal, 16
and 17 indicate output terminals. Agent Masu Oiwa Yushin 2 Figure 3 4 / γ-11, -no

Claims (4)

[Claims] (1) A semiconductor memory device having a non-volatile memory cell array in which data can be electrically rewritten, and in which a predetermined unit of data inputted from the outside can be collectively written into the memory cell array, logic state detection means for detecting the logic state of the predetermined unit of data before writing the predetermined unit of data into the memory cell array; contains all logic 0s or all logic 1s, only one of the operation of erasing the area of the memory cell array to which the predetermined unit of data is to be written and the operation of writing data to the area is performed. A semiconductor memory device including a control means. (2) The predetermined unit of data is input in parallel, and the logic state detection means determines whether the predetermined unit of data input in parallel includes all logic 1s or all logic 0s. The semiconductor memory device according to claim 1, comprising a logic gate. (3) The semiconductor memory device according to claim 2, wherein the logic gate includes a NAND gate and an OR gate that receive the predetermined unit of data input in parallel. (4) The logic state detection means further includes a first latch means whose state is inverted in response to the output of the NAND gate, and a second latch means whose state is inverted in response to the output of the OR gate. The semiconductor memory device according to claim 3, comprising: