JPS6233460A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the base resistance and the base width, to improve the maximum oscillating frequency and cut off frequency, and to reduce considerably the base running time and switching time, by utilizing two-dimensional carriers having high conductivity and confinement effect defined on the hetero junction interface. CONSTITUTION:By utilizing high conductivity and confinement effect in a narrow region of the two-dimensional positive hole layer 19 deined on the hetero junction interface between a second semiconductor layer 13 and a third semiconductor layer 14, for example on being applied to a HBT, the base resistance rB and the base width WB can be reduced to realize a high performance HBT. That is, since two-dimensional positive holes created in the high purity layer 13 has a reduced impurity dispersing effect, and moreover the two-dimensional freedom provided by nature reduces the dispersion, this HBT has an extremely large positive hole mobility especially at a low temperature. Thus a semiconductor device having excellent high speed and high frequency characteristic can be provided.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device that uses a conductive layer having high conductivity at a semiconductor heterojunction interface and has particularly excellent high speed and high frequency characteristics. [Background Art] In recent years, heterojunction bipolar transistors (hereinafter abbreviated as HBT) have been viewed as promising as ultra-high frequency and ultra-high speed devices. The theoretical approach of HBT is H-Kr0tl
rfrer, e.g.
Of Rumors The I Triple E (Proceedinga
of the IEEE), Volume 70, No. 1°, Page 13 (
(1982). The main features of HBTs include improved emitter efficiency and current gain, but actual HBT element structures still vary. FIG. 4 shows the structure of a typical HBT.

In FIG. 4, for example, in the case of an npn type, 1o1 is a collector electrode, and 102 is an n type substrate, such as GcAs.

103 is an n-type first conductor layer, for example GcAs, 104
105 is a p-type second semiconductor layer, for example, GaAs, and 105 is an n-type third semiconductor layer, for example, kl 0, which has a larger electron affinity than the sum of the energy gap of the semiconductor layer 104.
, 3Ga 6,7As, 106 is a pace electrode, and 107 is an emitter electrode. FIG. 5 shows an energy band diagram directly below the emitter electrode 107 in a thermal equilibrium state. Here, TS represents the energy level at the lower end of the conduction band, EF represents the Fermi level, and Ev represents the energy level at the upper end of the valence band. In the HBT shown in FIG. 4, most of the electrons injected from the emitter electrode 107 to the base layer 104 reach the collector electrode 101, whereas the holes injected from the base electrode 106 to the emitter layer 105 reach the collector electrode 101.
It is extremely small due to reflection by the emitter layer 105, which has a larger energy gap than the base layer 104. Therefore, for example, the current amplification factor hFE when grounded to an ivy is extremely large.

[Problem that the invention seeks to solve]

However, in the conventional HBT shown in FIG.
``When rB is decreased, rB increases),'' which has the drawback of limiting the performance improvement of HBT.To discuss this in detail, consider, for example, the maximum oscillation frequency 'rllllZX and switching time τS of HBT.'m,!, and te.

As is known, it is approximately given by the following equation.

Here, ft is the cutoff frequency, rB is the base resistance, Cc is the collector capacitance, and r and CL are the load resistance and load capacitance. It is also given by the base area transit time of minority carriers, town is the pace width, and horse is the diffusion constant of minority carriers (electrons in this case). Furthermore, if we pay attention to equations (1) to (3), which are almost inversely proportional to Jl- in terms of ft, FB, W
It can be seen that the reduction of B and cc is extremely important for improving the performance of HBTO. However, if the town is made smaller, rB becomes larger, so as mentioned earlier, this has the drawback of severely restricting the performance improvement of the HBT. Furthermore, it is clear that such drawbacks are common not only to npn-type HBTs but also to pnp-type HBTs.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art as described above and to provide a bipolar semiconductor device using a betero junction that has extremely excellent high speed and high frequency characteristics.

[Means for solving problems]

The present invention includes a high purity or n-type second semiconductor layer on the n-type first semiconductor layer, and a p-type third semiconductor layer having a larger sum of electron affinity and energy gap than the second semiconductor layer. , a stacked body with an n-type fourth semiconductor layer, and electrodes in ohmic contact with the first and fourth semiconductor layers of the stacked body are provided, respectively. A semiconductor device characterized in that it has a p-type first semiconductor layer, a high purity or p-type second semiconductor layer, and a p-type first semiconductor layer, a p-type second semiconductor layer, and a p-type second semiconductor layer. A laminated body of an n-type third semiconductor layer whose electron affinity is smaller than that of the semiconductor and a p-type fourth semiconductor layer, and an electrode in ohmic contact with the first and fourth semiconductor layers of the laminated body. Each of the semiconductor devices has a control electrode in contact with the second and third semiconductor layers.

[Principle and operation of the invention]

Hereinafter, the principle and specific effects of the present invention will be explained with reference to the drawings. For convenience of explanation, a specific material will be used, but it is clear that the principles of the present invention can be applied to other materials as well.

FIG. 1(α) is a schematic cross-sectional view showing an example of the basic structure of the semiconductor device of the present invention.

In Figure 1 (α), 11 is a high resistance board, 12
is the n-type first semiconductor 1.13 *'High purity or n
14 is a p-type third semiconductor layer having a larger sum of electron affinity and energy gap than the second semiconductor 13, and 15 is an n-type fourth semiconductor layer, which are stacked in order. It is what was done. Reference numeral 16 denotes a control electrode formed on the third semiconductor layer 14. Furthermore, ohmic electrodes 17 and 18 are formed on the first semiconductor layer 12 and the fourth semiconductor layer 15, respectively.

Figure 1 (b)! In the structure according to the present invention shown in FIG. 1 (α), this is an example of an energy band diagram directly below the electrode 17 in a state of thermal equilibrium. , Ev are the same as those explained in FIG.

The basic principle of the present invention is that the two-dimensional hole N19 formed at the heterojunction interface between the second semiconductor layer 13 and the third semiconductor layer 14 has high conductivity and a confinement effect within a narrow region. For example, when applied to HBT using
In other words, the two-dimensional holes formed in the high purity layer 13 are known. Yoe, special KT: Juni,) San. For example, holes in GaAs have an extremely large hole mobility, especially at low temperatures, because scattering is reduced due to the two-dimensional nature of the inherent degree of freedom. in the case of,
μh at room temperature: 400cl/V ・μh at S 77
It increases dramatically to z4000dVv・8. In addition, the hole surface density p8 of this two-dimensional hole layer varies depending on the carrier density and film thickness of each semiconductor layer, but is about lX10%.
” is possible. Furthermore, since the wave spread of this two-dimensional hole is extremely small, about 100, in other words, the hole is confined in the triangular potential well at the hetero interface, so the effective base width is It is expected that this will greatly contribute to the reduction of

Now, in order to reduce τ8, the effective base width WB-s
When the thickness is set to oo A, a RO considering the sheet resistance R8 of the base region is given by the following equation.

lRO= (tPsμh)
(4) Here, t is the amount of charge of the electron. In the case of the conventional structure shown in FIG. 4, when the town = 500 people, there is a depletion layer width due to the rabbit junction, so the effective width of the second semiconductor layer 104, which becomes the base layer, is a 7-cube density of about lX10crL. (base layer 104) and 5 x 10”
Assuming a donor density (emitter layer 105 and collector layer 103) on the order of cm', the number is estimated to be about 300. Also.

Considering that the hole mobility in a semiconductor with high acceptor density is significantly lower than in the case of high purity, for example, if p-type GaAs is used for the base layer 104, μh
It will be 100 cr L'V・S in the evening. Therefore, & in the conventional structure is estimated to be about 20. On the other hand, in the present invention, when R2''=16 and Ω10,77 at room temperature, R8
It is clear that the sheet resistance R0 of the base region, and therefore the base resistance rB, is greatly improved by the present invention. Furthermore, since the town can be made smaller compared to the town value (≧100OA) that is often used in conventional structures, τB can be significantly improved from equation (3). Since the hole layer 19 senses the potential barrier at the heterojunction interface, the confinement effect is high, and therefore it is almost ideal.
・2','a''-,X □The minority carriers are accelerated and τB can be further reduced.

As explained above, the present invention significantly improves rB and town, and therefore improves the characteristics in both 'mczx and τB. Therefore, it is possible to obtain a nine-handed conductor device with excellent high speed and high frequency characteristics. it is obvious.

In the above explanation, the so-called np
Although the description has been made regarding the n-type, the principles of the present invention can be similarly applied to the so-called pnp-type, in which holes serve as minority carriers.

FIG. 2(α) is a schematic cross-sectional view showing an example of the basic structure of a pnp type semiconductor device according to the present invention.

In FIG. 2 (α), 21 is, for example, a high resistance substrate, 22
25 is a p-type first semiconductor layer, n is a high-purity or p-type second semiconductor layer, U is an n-type third semiconductor layer whose electron affinity is smaller than that of the second semiconductor layer 4, and 25 is a p-type semiconductor layer. 26 is a control electrode, and 27 and 28 are ohmic electrodes.

FIG. 2(b) is an example of an energy band diagram of ゛.-1..' directly under the electrode 27 in a thermal equilibrium state in the structure according to the second invention shown in FIG. 2(α). Here, 29 is a two-dimensional electronic layer, and Ec, EF, and Bv are the same as those explained in FIG. 1(b) and FIG. 5.

It goes without saying that the semiconductor device according to the present invention has basically the same principles, operations, and effects as the semiconductor device according to the first invention of the npn type described above.

〔Example〕

Examples of the present invention are shown below.

(Example 1) In FIG. 1 (α), a high-resistance GcLAs substrate 11 and a donor impurity density of 5×10
An n-type kl with a film thickness of about 5000mm and about 1101II"
oJsGα. , 711As in the second semiconductor layer 13 with an impurity density of 1×10 LIlcriL3 or less and a film thickness of about 5
00 people, MA80 molar ratio X becomes 0.25 at the interface with the first semiconductor layer 12, gradually decreases toward the third semiconductor layer 1411i1, and becomes zero at the interface with the third semiconductor layer 14. , -xAS in the third semiconductor layer 14 with an acceptor impurity density of about 2×1♂53 and a film thickness of about 500 mm.
The fourth semiconductor layer 15 is made of large p-type Al163 [with] 0.7As, and is made of n-type M with a donor impurity density of about 5×1σ7♂ and a film thickness of about 5,000. J [Yes]. , As, noodle Ge/Ni electrodes were used for the ohmic electrodes 17 and 18, and an AuZn electrode was used for the control electrode 16. In this embodiment, the energy band diagram directly under the electrode 17 in a thermal equilibrium state is the same as that shown in FIG. 1(b).

In this embodiment, for example, the ohmic electrode 17 is
The emitter electrode of T and the ohmic electrode 18 are operated as collector electrodes. The base resistance r in this example,
is significantly improved compared to the conventional example, and the maximum oscillation frequency f! 1
Regarding rlGX, the frequency increased to approximately 15 GHz compared to approximately 10 GHz or less in the conventional example. Further, τ3 and τ8 were significantly improved due to the reduction in moths mentioned above and further due to the accelerating potential gradient of the semiconductor layer 13.

Incidentally, the order of the layer structure in this embodiment shown in FIG. 14. Even in a structure with a high-purity or n-type second semiconductor layer 13 and an n-type first semiconductor layer 12, I(BT operation is possible) although rB is slightly higher than the above-mentioned stacked structure. In terms of emitter injection efficiency, it is desirable that the fourth semiconductor layer 15 has a larger energy gap than the third semiconductor 14.

In this embodiment, an ohmic electrode made of AuZn was used as the control electrode 16, but it is clear that HBTBT operation is possible in principle by using a Schottky electrode made of M, for example.

(Example 2) Next, Example 2 of the present invention will be described. A schematic cross-sectional view of the structure in this example is shown in FIG.

This example uses a QI0LAa substrate 32 with a donor impurity density of about 5×1018♂ and a QI0LAa substrate 32 with a donor impurity density of about 5
AA film thickness of 3000 people at about Q"cm"! l, J.G.K.
Lo, 7As 33 and impurity density I X1015c
i3 or less, the film thickness is about 500, and the molar ratio of AJAs is A.
l. JGα. ,,0.3 at the interface with As33, and the upper layer is All,...,Ga. , 7Aa 35 side, and becomes zero at the interface)-1,Ga1
-, AJI34 and impurity density of 1×101scIiL
A10.3 (<, 7As 3
5, acceptor impurity density is about 3x1♂63, film thickness is about 400 people, AJ, 3Gao,, As 36, donor impurity density is about i11Xl018cat3, film thickness is 2
000^, and the molar ratio y of AlAs is Mo, 3 [present]. ,
0.5 at the interface with 7A836, and the upper layer of GaA
Saki G gradually decreases toward s38 even and becomes zero at the interface.
a, -yAs 37 and donor impurity density 5 X10
GcLAs with a film thickness of 300OA at about “cit” 3
g, and AuGa/Au electrodes for the ohmic electrodes 31 and 4o laminated on the lower and uppermost layers of the laminate.)
An electrode made of AuZn is used as the control electrode 39 formed on the d16.3GcL6.7Al 36.

In this example, when 40 is operated as the emitter electrode of the HBT and 31 is used as the collector electrode, fm and fm are further improved compared to Example 1 to approximately 18 GHz.

This is because the introduction of the so-called spacer layer 35 reduces impurity scattering and increases the two-dimensional hole mobility, and the provision of two pace electrodes 39 reduces F) rB. and improves the effective donor impurity density on the emitter side, and also improves the base layer 36 on the emitter electrode side.
This is due to the fact that the emitter layer 37 near the base layer is made of a material that has a larger sum of electron affinity and energy gap than the previous one, thereby increasing the emitter injection efficiency.

It is clear that in this embodiment as well as in the first embodiment, the HBT operation is possible even with a layer structure inverted from that shown in FIG.

(Embodiment 3) Next, one embodiment of the second invention of the pnp type will be described.

The schematic cross-sectional view of the structure in this example is the same as that in FIG. 2 (, x).
A8 substrate, acceptor impurity density is 5×101 in 22
P-type Ml with a film thickness of about 5,000 people at about 6 crrr'',
JGα. ,? llAl5, the impurity density is 1× at '23
101sciL3 or less, film thickness 500 people, molar ratio of Mh
The donor impurity density becomes 0.5 at the interface with M, O, As, 22, gradually decreases toward the 24 side, and becomes zero at the interface with U. 2×
1O18cr! N-type M, 3G with a film thickness of about 500 people
a. , As, the acceptor impurity density is 5X at 25
A p-type M with a film thickness of about 1.017cm3 and 5oooA. Day ≧. , 6-, the ohmic electrodes 27 and 4 are made of AuZn.
In this embodiment, an electrode made of AuGa/Ni is used as the control electrode 26, and the energy band diagram directly under the electrode 27 in a thermal equilibrium state is the same as that shown in FIG. 2(b).

Example Q When applied to HBT, pace resistance r.

Since the mobility and areal density of the two-dimensional electron layer 29, which is responsible for A reduction in τ8 can be achieved.

Incidentally, in the present invention, a structure similar in principle to the structure shown in FIG. 3 can be realized as in the case of the first invention (npn type). Furthermore, even with a structure in which the order of the layer structure shown in FIG. 2 (α) is reversed, the operation can be performed. Furthermore, in order to improve the emitter injection efficiency, it is preferable that the fourth semiconductor layer 25 has a larger energy gap than the third semiconductor layer, and the control electrode 26 may be a Schottky electrode or H
BT operation is possible.

〔Effect of the invention〕

As described above, according to the present invention, by using a two-dimensional carrier having high conductivity and a confinement effect formed at the heterojunction interface, the pace resistance and base width can be reduced, thereby increasing the maximum oscillation frequency and cutoff. This has the effect of realizing an ultra-high frequency/ultra-high speed element that has great advantages such as an improvement in frequency and a significant reduction in pace running time and switching time.

[Brief explanation of drawings]

FIG. 1(α) is a schematic cross-sectional view showing an example of the basic structure of the semiconductor device of the present invention, FIG. 1(b) is its energy band diagram, and FIG. 2(α) is another example of the present invention. FIG. 2(b) is a schematic cross-sectional view showing the energy band diagram, FIG. 3 is a schematic cross-sectional view showing another example, and FIG. 4 is a schematic cross-sectional view showing the structure of an example of a conventional semiconductor device. The cross-sectional view, FIG. 5, is its energy band diagram. 11 and 21... High resistance substrate, 12... N-type first
semiconductor layer, 22...p-type first semiconductor layer, 13.
...High purity or n-type second semiconductor layer, 23...High purity or p-type second semiconductor layer, 14...p-type third semiconductor layer, 24...n-type Third semiconductor layer, 15...
- N-type fourth semiconductor layer, 5... P-type fourth semiconductor layer, 16 and 26... Control electrodes, 17, 18, 27 and housing... Ohmic electrode, 19... 2-dimensional hole layer, 29...2-dimensional electron layer Fig. 1 (α) Fig. 1 (b) Fig. 2 (α) Fig. 3 Fig. 5

Claims (2)

[Claims] (1) An n-type first semiconductor layer, a high-purity or n-type second semiconductor layer, and a p-type third semiconductor layer that has a larger sum of electron affinity and energy gap than the second semiconductor. and an n-type fourth semiconductor layer, each having an electrode in ohmic contact with the first and fourth semiconductor layers of the stack, and in contact with the second and third semiconductor layer. A semiconductor device characterized by having a control electrode. (2) a p-type first semiconductor layer, a high-purity or p-type second semiconductor layer, an n-type third semiconductor layer whose electron affinity is smaller than that of the second semiconductor, and a p-type fourth semiconductor layer. a laminate with semiconductor layers of the laminate, electrodes in ohmic contact with the first and fourth semiconductor layers of the laminate, respectively, and second and third semiconductor layers.
A semiconductor device comprising a control electrode in contact with a semiconductor layer.