JPS6233464A - thin film transistor - Google Patents

Abstract

PURPOSE:To cause carrier confinement effect of the hetero junction, to reduce the trap probability, and to attain the high speed response, by laminating in multi-layers thin film layers having different forbidden band width. CONSTITUTION:An opening 11a is bored through a substrate 11 with etching, and SiO2 is deposited to form a black, on which a multi-layer thin film 13 is deposited with a plasma CVD method using glow discharge deposition. The end of the multi-layer thin film 13 is etched away by about 20Angstrom from the underside of the opening 11a, and at this portion Al is evaporated to form a source electrode 12. Thereafter, at the side at which every layer of the multi-layer thin film 13 is developed, an SiO2 film 16 is formed with electron beam evaporation. Al is evaporated thereon to form a gate electrode 17, and then the multi- layer thin film is etched away on the top and the side of the block. Last, on the top of the multi-layer thin film 13 being remained, Al is evaporated to form a drain electrode parallel to the substrate plane, providing a thin film transistor.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a four-star thin film register.

(Prior art and its problems) Figures 5(a), 5(b), and 5(c) show thin film transistors (TPT) that are generally known in the past.
The main materials in a) are recrystallized silicon, poly, and silicon, in (b) amorphous silicon, and in (c) CdSe. However, each of these thin film transistors has the following problems.

(a) Recrystallized silicon, polysilicon TPT When fabricating with this material, first, it is difficult to form a film at low temperatures (below 400° C.). This requires an expensive substrate made of a heat resistant material such as single crystal silicon or quartz. It is also necessary to create a silicon film with few structural defects similar to single-crystal silicon, but when trying to deposit a film over a large area in order to simultaneously manufacture many thin film transistors, there are many strains and defects that affect the electrical properties. It will happen. Therefore, at present, only about 6-inch wafers can be manufactured, and the cost per TPT is high.

(b) Amorphous silicon TPT Amorphous silicon can be formed into a film at a low temperature and over a large area, and is widely used in solar cells, sensors, etc. However, when used as a thin film transistor, since amorphous silicon has a low mobility, the structure shown in FIG. 5(b) provides a fast response. Furthermore, when carriers move from the source to the drain, they are diffused, increasing the probability of trapping and changing the characteristics over time. Furthermore, when a high electric field is applied, structural changes occur at the electrode interface and in the thin film, resulting in changes in characteristics.

(c) CdSe T F T CdSe can be formed into a film at a low temperature and over a large area, but Cd and Se are easy to separate due to the manufacturing method, and furthermore, it reacts strongly with oxygen, making process control difficult.

In addition, the mobility is small and there are many traps, so the response is fast.
Stability is an issue.

The present invention solves the problems of the prior art described above and provides a high-speed, highly stable thin film transistor.

(Means for solving the problem) In order to solve the above problem, a source electrode or a drain electrode is provided on the substrate, and a layer is placed on the source electrode or drain electrode so that the laminated surface is substantially perpendicular to the surface of the substrate. At least two or more types of thin films with different forbidden band widths are laminated in a multilayer structure of at least three layers so that thin films of the same type are not adjacent to each other, and a drain is placed on top of the layer so as to be approximately parallel to the surface of the substrate. An electrode or source electrode is provided, and a gate electrode is provided via an insulating layer on the side surface where each layer of the multilayer board 1 is exposed.

(Function) A heterojunction potential well is formed by laminating multiple thin film layers with different forbidden band widths, and as a result, carriers are attracted by the electric field and conduct in the layer with a narrow forbidden band width.
There is no diffusion towards adjacent layers.

At this time, assuming that the carrier lifetime is τ and the drift mobility is μ, the μτ product becomes an important factor in the response speed, and the above action increases τ, making high-speed response possible. Further, since the applied high electric field is distributed to each layer and the electric field applied to each layer is reduced, structural changes and crystallization due to the high electric field do not occur. Furthermore, since the vertical conduction of the thin film is utilized, the channel length can be shortened, making it possible to achieve higher speeds.

(Example) Embodiments will be described in detail below based on the drawings.

FIG. 1 shows an embodiment of the present invention, in which 1 is a substrate, 2 is a source electrode formed on the substrate 1, and 3 is a multilayer thin film, which includes at least two types of thin films with different forbidden band widths. The thin films of the same type are laminated in a multilayer structure of at least three layers so that they are not adjacent to each other (in this example, the thin films are made of three layers of two types: an a layer, a b layer, and an a layer). This multilayer thin film 3 is laminated so that its laminated surface is substantially perpendicular to the substrate surface. 4 is a drain electrode formed on the top of the multilayer thin film 3, substantially parallel to the substrate surface; 5 is an insulating layer; 6a;

6b is an insulating layer formed on the side surface where each layer of the multilayer thin film 3 is exposed, and is provided substantially perpendicular to the substrate surface.

7a and 7b are gate electrodes provided on the outside of the insulating layers 6a and 6b, respectively.

In addition, in the above structure, an intermediate layer may be inserted between the multilayer thin film 3 and the source electrode 2 and between the multilayer thin film 3 and the drain electrode 4 to obtain ohmic properties.6 Also, after forming the thin film transistor, Apply a passivation film to cover the entire area to prevent moisture, oxidation, etc.
may be formed.

The substrate 1 is preferably made of an insulating material, such as inorganic materials such as glass and ceramics, and organic materials such as polyimide. Alternatively, a conductive material subjected to insulation treatment may be used.

The thin films of the multilayer thin film 3 having different forbidden band widths may be crystalline or amorphous. In the case of crystals, the materials must have relatively similar lattice constants.

Therefore, as a combination, Cd5-Cu2S, Cd5-
CdTc.

Cd5-InP, CdTe-Cu2Te, Cd5-
CuInS2. CdS-CuInSe2. Cd5
-CuInTe, , Cd5-CuGaSe2. C
u2Te-CdTe, Cd5e-ZnTe, Cd
5-3i etc. are good. Furthermore, by using a combination of amorphous and crystalline materials, the lattice constant can be relaxed to some extent.

Amorphous (a- is used as a symbol) materials include a-5,i: H(F)a-5e, a-Ge:
II(F) etc., Cd5-a-5i: H
CuInSe-a-5e, CufnSe-a-5i
: Combinations such as H are good. The combination of amorphous materials is a-5e-a-5j: H+ a-3
ixC1-,: If-a-3i: It.

a-5i, N1-x: II-a-3i: II,
a-3ixOL-++: H-a-Si: H, etc. are preferable.

AQ is used as the source electrode 2 and drain electrode 4.

Mo, 11. Ni, Cr, Au, and Ag can be used.

The insulating layers 6a and 6b between the multilayer thin film and the gate electrode include 5402+ 513N4+ SiC, TjOZI
Examples include Tl1N41 Tic and the like.

As the gate electrodes 7a and 7b, Ale Mo, v
, N1pCr, Au, and Ag can be used.

Further, as an intermediate layer inserted to obtain ohmic properties between the multilayer thin film 3 and the source electrode 2 and train electrode 4, a layer having the same composition as the multilayer thin film 3 and lowered in resistance by doping can be used.

FIG. 2 shows a band model in which films with different forbidden band widths are laminated in multiple layers. Crystal - Crystal, Amorphous, - Fine,
Both amorphous-amorphous combinations have their own conductivity types, and these conductivity types are P-type, N-type,
It can be divided into i-types, and the combinations of conductivity types are P-type-N-type, P-type-1 type, and N-type-P type.

There are N type-J type, I type-1 type, etc., and each band model is shown in FIGS. 2(a) to 2(e), respectively. In addition to this combination, P type-P type and N type-N type may be used. Et...
is a layer with a wide forbidden band width, and Eg-z is a layer with a narrow forbidden band width.

EF is at the Fermi level, and the 8-layer film thickness and bJfi1 film thickness are the same.

Film thickness per layer with different forbidden band widths is 100 to 1000
The total thickness of the multilayer thin film 3 is 0.1 to 10 μm.
, preferably 0.3 to 2 μm. The thickness of the insulating layers 6a and 6b between the multilayer thin film and the gate electrode is 500°.
1 μm is good, preferably 1000 to 5000
Good people. The thickness of each electrode is preferably 1000 to 5000.

In addition, the channel length between the source and drain is 1000 ~
Between IO μm is good, preferably 5000 A to 3 μm
It is best between. The channel width is preferably between 1 and 100μ.
Preferably it is between 2 and 20 μnn.

Next, a specific example including a manufacturing method will be shown. Pyrex glass was used as the substrate, and a-5 was used as the film with different forbidden band widths.
An amorphous semiconductor of x: H-a-5xxNz -x: H was used. a-5i:H is a material with a narrow forbidden band width, and a-5i, N, .:H is a material with a wide forbidden band width. a-3i: H is an N-type semiconductor with a lattice constant of about 4 and a forbidden band width of 1.7 eV, a-3iJ, -
, : ! l has a lattice constant of approximately 4 and a forbidden band width of 2.3eν
It is an N-type semiconductor, and is a combination of N-type and N-type. First, as shown in FIG. 3(a), a hole 11a is formed in the substrate 11 by etching, and SiO□ is deposited to form a block I5. Thereon, as shown in FIG. 3(b), a multilayer thin film 13 was deposited by plasma CVD using glow discharge decomposition. This multilayer thin film forming method will be described in detail later. next.

As shown in FIG. 3(c), the multilayer thin film 1 is opened from the bottom of the hole 11a.
Remove the edge of 3 by etching about 20 people, and then apply A to that part.
A source electrode 12 is formed by depositing g. Thereafter, as shown in FIG. 3(d), a 5in2 film 16 is formed by electron beam evaporation on the side surface where each layer of the multilayer thin film 13 is exposed, and AN is evaporated thereon to form a gate electrode 17. Next, as shown in FIG. 3(e), the multilayer thin film on the top and side surfaces of the block is removed by etching, and finally, as shown in FIG.
As shown in f), a drain electrode 14 parallel to the substrate surface was formed on the remaining multilayer thin film 13 by vapor deposition of AN to obtain a thin film transistor.

A method for forming the multilayer film 13 will be explained based on FIG. 4.

This device has two chambers, an A chamber 111 and a B chamber 110. First, open the valves 118 and 121 and turn on the rotary pumps 122 and 124. CA chamber 111. B chamber 11
0 & 10-”Torr pressure, valve 1], 8.1
21 is closed, and then valves 125, 119, and 120 are opened to bring chambers A and B to a pressure of 10-' Torr using rotary pump 126 and diffusion pump 123. Then, close valves 119 and 120.

First, the sample 116 is set so as to face the high-frequency electrode 112 in the A chamber 111 in parallel, and the valves 106 and 108 are opened, and the main stopper 102 and N113 of the SiH4 cylinder 100 are opened.
Open the main valve 103 of the cylinder 101 and connect the flow meter 10.
4 to maintain the flow rate of S i H4 at 20 cc, and adjust the flow meter 105 to maintain the flow rate of N11. The flow rate of 10
0 cc, adjust the valve 118 to maintain the pressure in chamber A 111 at l Torr, and turn on the high frequency power source 114 to 20 v
The high frequency electrode 112 generates a discharge. a-3j
xN, -x: After 100 H films are deposited on the substrate 116,
Turn off the high frequency power supply 114 and close the valve 1.06.108. Next, the motor 109 is rotated and the sample is transferred to the B chamber 11.
0 and set it parallel to and facing the high frequency electrode 113. Open the valve 107 and adjust the flow meter 104 to 20cc, and adjust the valve 121 to open the B chamber 110.
While maintaining the pressure at I Torr, the high frequency power source 115 is turned on and adjusted to 20 til, causing discharge at the high frequency electrode 113.

a-3i: After 100 H films are deposited on the substrate 116,
Turn off the high frequency power supply 115 and close the valves 107 and 121. The above operation was repeated alternately in chambers A and B, and a-8iwN: II films and a-5i: II films were alternately deposited on the substrate by 100 people each, and a-5i, N, -:
21 layers of H film and 20 layers of a-5i:It film were deposited for a total film thickness of 4100 layers.

As a result of measuring the characteristics of the thin film transistor obtained as described above, the gate voltage was 20 V, and the drain voltage was 1.
Apply 5V and get 1,, = IX10"' (A), I, F, = 2X10
-"(A), Io-/IOF+"; 105, which was sufficient for a thin film 1-transistor, high-speed characteristics were obtained, and it was stable with no change over time.

(Effects of the Invention) As described above, according to the present invention, by laminating multiple thin film layers with different forbidden widths, a carrier confinement effect of a heterojunction is produced, and as a result, the trap probability is reduced, and a high speed response becomes possible. Further, the high electric field applied to the multilayer film is distributed to each layer, and the electric field per layer is reduced, so that structural changes can be prevented. In addition, since it utilizes the longitudinal conduction of the thin film, and it is easy to thin the thin film by gradually etching it from the top, it is possible to use channel lengths of several thousand people.
Even in a thin film with low mobility, carriers can move between the source and drain in a short time, enabling higher-speed operation. Due to the above synergistic effect, a high speed and highly stable thin film transistor can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a thin film transistor according to an embodiment of the present invention, FIGS. 2(a) to (e) are diagrams showing band models for combinations of various conductivity types of multilayer thin films, and FIG. 3 is a diagram showing a specific example. FIG. 4 is a diagram illustrating the example manufacturing method, and FIGS.
) and (c) are block diagrams of conventional thin film transistors, respectively. 1...Substrate, 2...Source electrode, 3...
Multilayer thin film, 4... drain electrode, 5, 6a,
6b...Insulating layer, 7a, 7b... Gate electrode. Figure 1 (a) (b) (c) Figure 2 (a) (b) (c) (d) (e) (4 poisonous N'♂) Figure 3 (a) (b) (c)
(d) (e) (f)OL O Fifth cause (a) (b) (c)

Claims (3)

[Claims] (1) Either a source electrode or a drain electrode is provided on a substrate, and at least two types of electrodes having different forbidden band widths are placed on top of the source electrode or drain electrode so that the laminated surface is substantially perpendicular to the surface of the substrate. The thin films are laminated in a multilayer structure of at least three layers so that thin films of the same type are not adjacent to each other, and one of a source electrode and a drain electrode is placed on top of the thin film so as to be substantially parallel to the surface of the substrate. 1. A thin film transistor characterized in that a gate electrode is provided on a side surface where each layer of the multilayer thin film is exposed, with an insulating layer interposed therebetween. (2) The thin film transistor according to claim (1), wherein at least one kind of the multilayer thin film is amorphous silicon containing at least one kind of hydrogen atoms, deuterium atoms, and halogen atoms. (3) An intermediate layer exhibiting ohmic characteristics with the multilayer thin film and electrode material is provided between the multilayer thin film and the source electrode, and between the multilayer thin film and the drain electrode. Thin film transistor.