JPS6233476A - Field effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain the FET of little short-channel phenomenon and accordingly to obtain the FET of good operation characteristics by providing a high- concentration and low-resistance layer which is close to a gate electrode and extends to the under part of a source electrode in only the source electrode side of the ate electrode. CONSTITUTION:On a semi-insulating GaAs substrate 11, Si<+> ions are implanted by using, e.g., a predetermined photoresist pattern as a mask to coat the surface with an SiO2 film, after which annealing in nitrogen atmosphere is done to form an N-type GaAs layer 12. An SiO2 film 21 as the first substance is so arranged that its end plane is located in the part where a gate electrode is to be formed. Next, a WN film 22 which is to be a gate electrode is deposited over the whole surface by sputtering. By etching the WN from a vertical direction of the wafer, a WN electrode (gate electrode) 13 of about 0.5mum thickness and 0.5mum height is formed on the side plane of the first substance (SiO2). Si<+> ions are implanted and a heat treatment is made to form an N<+> region 16 close to the WN electrode. Furthermore, the unnecessary first substance (SiO2) is removed and ohmic electrodes of source 14 and drain 15 electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a field effect transistor (FET) and a method for manufacturing the same.

[Conventional technology]

FIT is essential in TL as an analog amplification element in the UHF to microwave band and as a switching element for high-speed digital circuits, and has been extensively researched and developed and put into practical use. Among them, the GaAa 7a Sitky barrier date type FET, that is, the GaAg MESFET, which uses a GaAa semiconductor layer as the active layer and uses a metal-semiconductor contact (Shigyitky contact) as the ff-) electrode, has a 7M knee.
＋ , ＾−−P ++−＋＋−＋＋＋＋＋lNh++
+'1% 817n field? -4'P+A has attracted attention as an ultra-high-speed switching element, and integrated circuits (ICs) using it are also being actively researched for practical use.

FIG. 3(A) shows a schematic cross-sectional view of the structure of a GaAs MIIESFET.p) A GaAs semiconductor layer 12 is formed by ion-implanting, for example, St 2 onto a semi-insulating substrate 11, and a GaAs semiconductor layer 12 is formed on it. Thick key gate electrode 1
3, source 14 and drain 15 electrodes. IC using such GaAs MESFET (GaA@IC)
To increase the speed, the basic element GaAa MESF
The characteristics of ET itself, especially the transconductance (gm
), it goes without saying that improvement is essential. The most effective method for improving gm is to reduce the parasitic resistance (source resistance) between Y and source. To achieve this, a structure is known in which a high concentration region (n+ region 16) is formed by selective ion implantation using the gate electrode 13 as a mask, as shown in FIG. 3(ω).

[Problem that the invention seeks to solve]

However, in this structure, ions, such as Sl, implanted to form the n-region diffuse laterally during the heat treatment process for activation, increasing the effective carrier density under the gate electrode and causing extreme If so, the source,
It has the disadvantage of shorting the drains. This phenomenon is called a short channel phenomenon, and is a major drawback of the FET having the structure shown in FIG. 3(B).

The present invention is intended to eliminate the above-mentioned drawbacks of the conventional GaAs MESFET, and its purpose is to provide a field-effect transistor in which the above-mentioned short channel phenomenon is suppressed and a method for manufacturing the same.

[Means for solving problems]

The present invention provides a MESF in which a gate electrode with a barrier contact and source and drain electrodes with an ohmic contact are provided on an n-type semiconductor layer formed on a semi-insulating substrate.
In ET, y-toiI! Only on the source electrode side of the pole,
A field effect transistor is provided with a high concentration, low resistance layer that is close to the gate electrode and extends below the source electrode, and a film made of the first material is provided in a predetermined region on the n-type semiconductor layer, and then a gate is formed over the entire surface. By depositing a second material (metal) that will become an electrode and etching the second material by anisotropic dry etching from the perpendicular direction of the wafer, the side surface of the first material is etched. A step of leaving the second material as a gate electrode, and using the left second material (gate electrode) and the first material as a mask, highly concentrated ions are applied to the n-type semiconductor layer KJ.
selectively implanting and activating the implanted ions; removing the first material; and on both sides of the gate electrode.
This method of manufacturing a field effect transistor includes the step of forming source and drain electrodes at a predetermined distance from a gate electrode.

[Principle/effect]

What is the meaning of the field effect transistor in the present invention? Since the region is formed only on the source side of the gate electrode, the short channel effect can be reduced compared to the structure shown in FIG. 3 (in which n+ regions are formed on both sides of the gate electrode). Especially for GaAa MESFETs 71/,'/-
7-WtVIft "■:/Vkaih)ノHノS-to'1l
R1 (7') k , changes in vth due to shortening of the gate length can also be prevented. - From the point of view of the force characteristic CQrn), the source resistance is sufficient because the source electrode side <#in region is provided./" .

On the other hand, regarding the manufacturing method, the key point is to form the n region in a self-aligned manner only on the source side of the fine (usually 1 μm or less) gate electrode, and then implant ions into the drain side of the ff-) electrode. It has been realized to automatically place a substance to prevent this.

〔Example〕

FIG. 1 is a diagram showing an embodiment of a GaAs MESFET according to the present invention. In the figure, reference numeral 12 denotes an NFI semiconductor layer. For example, Sl ions are implanted at an acceleration energy of 50 ksV and a density of 4 x 10"7 cm2, and then heated at 800°C for 20 minutes in a nitrogen atmosphere. The gate electrode 13 is formed on a refractory substrate 11. The gate electrode 13 is made of tungsten nitride (WN), and the gate length and gate metal thickness are both 0.5 μm.Gate electrode 1
An n region 16 is provided on the source electrode side of 3 in contact with the gate electrode 13, the source electrode 14 is provided on the n region 16, and the drain electrode 15 is provided on the f-to electrode 13 in a region opposite to the source electrode 14. It is provided 0.5 μm apart from 13.

Next, an example of a method for manufacturing an FET having the above structure will be described with reference to FIG. First, in Figure 2 (G), semi-insulating G
-A 50 keV of Sl is applied onto the aAa substrate 11 using, for example, a predetermined photoresist pattern as a mask.

The pn-type GaAs was implanted under the conditions of 4 X lO"/cJ, and then the surface was covered with a 5i dioxide (8102) film with a thickness of 20001.2 mm, and then annealed at 800 °C for 20 minutes in a nitrogen atmosphere to form pn-type GaAs. A layer 12 is formed.Next, in FIG.
(thickness: 0.5 μm). Specifically, this can be achieved by depositing 5i02 with a thickness of 0.5 μm on the entire surface by the CVD method and then performing four-turning using the usual photolithography technique. 5io2 etching solution diluted 7
Tusric acid (HF) is preferred. Next, a WN film 22 which will become a gate electrode is deposited in sectors to a thickness of 0.5 μm over the entire surface (FIG. 2(C)). Next, in the same figure (D), for example, C
By etching WN from the vertical direction of the wafer using reactive ion etching (Rxg) using F4 gas, a layer of about 0.5 μm is etched on the side surface of the first material (S10□).
WN with thickness and height of 0.5μm! ! A pole (4"-to electrode) is formed.

Next, in the same figure @), change S- to ioo keV, 2
10", and by performing the same heat treatment as before, an n region 16 is formed close to the JWN electrode. Furthermore, in C) of the same figure, the unnecessary first material ( S10□) is removed and the ohmic properties of the source 14 and drain electrodes 5 are provided with poles using the usual method.
A GaAs MESFET with the structure shown in the figure is completed. In addition,
In this example, a heat treatment step for forming a single layer of n-type GaA, and ? Although the heat treatment step for forming the region was performed separately, it is also possible to omit the former and form the n-type GaAa layer (activation of the implanted ions) by the heat treatment at the time of forming the n+ region. In addition, a dielectric (S) is used as the first substance.
In FIG. 2(F'), a metal such as At may be used as long as it can be selectively removed while leaving the second material (gate metal). Furthermore, although the first substance is removed after the heat treatment in the n+ region in this embodiment, it goes without saying that the first substance may be removed in a previous step.

FIG. 4 shows the relationship between gate length and threshold voltage measured in a GaAs MESFET according to the present invention and a conventional GaAs MESFET having the structure shown in FIG. 3. In the FET according to the present invention, the dependence of the threshold voltage on the gate length is extremely small, and the short channel effect is suppressed! It is clear that 1ilJ has been used.

〔Effect of the invention〕

As described above, according to the present invention, a field effect transistor with small short channel phenomenon can be obtained, and the operating characteristic 1c
It has the effects that all 6E FETs can provide.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of an FET according to an embodiment of the present invention, FIGS. , 03) is a cross-sectional view showing the structure of a conventional GaAg MESFET, and FIG. 4 is the result of measuring the relationship between gate length and threshold hold voltage for the GaAs MESFET according to the present invention and the conventionally structured Kamushika 5FET. FIG. 11... Semi-insulating substrate, 12... n-type GaAa layer,
13...Gate electrode, 1=1...Source electrode, 15
...Drain electrode, 16...n region. Fig.2

Claims (2)

[Claims] (1) On an n-type semiconductor layer formed on a semi-insulating substrate,
In a Schottky barrier gate type field effect transistor, which is provided with a gate electrode made of a Schottky contact, and source and drain electrodes made of ohmic electrodes, only the region on the source electrode side of the gate electrode is provided with a gate electrode close to the gate electrode and a source electrode made of ohmic electrodes. A field effect transistor characterized by having a high concentration, low resistance layer extending all the way to the bottom. (2) A step of forming a film made of a first material in a predetermined region on the n-type semiconductor layer, and then depositing a second material (metal) that will become a gate electrode on the entire surface, and a step in the vertical direction of the wafer. a step of etching the second material by anisotropic dry etching to leave the second material only on the side surface of the first material film to form a gate electrode; and a step of leaving high concentration ions in the second material. a step of selectively implanting the second material (gate electrode) and the first material as a mask; a step of removing the first material; 1. A method for manufacturing a field effect transistor, comprising the step of forming source and drain electrodes at intervals.