JPS6233623B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system restart method for establishing a normal system when a system failure occurs in an online system such as an electronic switching system.

Conventionally, when establishing a normal system in the event of a system failure, a complex restart processing program is required as software in order to select the normal system from various system configurations corresponding to the emergency state.

Furthermore, when establishing a normal system, the initial
The program is loaded from the external file memory to a fixed address in the memory, and therefore, depending on the type of external file memory, it takes time to load the program, which has the disadvantage that online system service is interrupted for a long time.

An object of the present invention is to simplify the restart processing program in software and to provide a method that greatly shortens the time required to restart the service of an online system that does not require constant loading of an initial program.

The automatic system restart method of the present invention is applicable to the system 0 system and system 1 system of the duplexed data processing device when a system failure occurs in a data processing device with a fully duplexed configuration consisting of a central control unit, a main storage device, a channel device, and an external file memory. an emergency circuit that automatically reconfigures a normal system including means for specifying one of the above, a timing circuit for initializing the data processing device, and a counter circuit that indicates the number of activations of the emergency circuit; When the count value of the counter circuit is within a specified value, the program is operated from a fixed address in the main memory, and when the count value of the counter circuit is greater than the specified value, the program is loaded from a specified external file memory. It consists of:

Next, the present invention will be explained in detail with reference to the drawings.
FIG. 1 shows a conventional duplex data processing device. In the figure, the 0-system central control device 20, the 1-system central control device 21, the 0-system channel device 30, and the 1-system channel device 31 are completely duplicated. However, the main storage devices 10 to 14 adopt an (n+1) redundant configuration for economical purposes. The normal operation when a failure occurs in a system is, for example, when a failure occurs in the 0 system, the emergency circuit 60 is activated and attempts to configure a normal system with the 1 system. In other words, for the external file memory, the 1st system external file memory controller 41 and the external file memory 51
is selected, and since the main storage device is of the (n+1) type, one of the plurality of main storage devices 10 to 14 is selected. For example, assume that the main storage device 10 is selected. (The selection of the main memory device at this time is determined by the emergency state, and the emergence state is updated every time the emergency circuit is activated). Next, a program for restarting the system is transferred from the external file memory 51 to the main storage device 10.
A fixed amount of data is loaded into a fixed address under the control of the central control unit 21 and channel device 31 of the system. The loaded program must perform restart processing to start up the system, continue online processing of the system, and detect which device is at fault. Since n out of (n+1) main storage devices are used to perform such processing, complex processing is required to detect a faulty device. Furthermore, considering the economic efficiency of external file memory, slow file memories such as cartridges are used, so it takes about 1 minute to load the program from the cartridge to the main memory.
It takes 1.5 minutes. (Because we also guarantee rewind time). In other words, online processing is interrupted during this time.

FIG. 2 shows an embodiment of a duplex data processing apparatus according to the present invention. One of the differences from conventional duplex data processing devices is that the main storage device also has a redundant configuration of the 2n system, making it fully duplex. That is, it has a 0-system main storage device 10 and a 1-system main storage device 11. Therefore, there are only two system configurations in the event of a system failure: the 0 system and the 1 system.
A 0-system data processing device consisting of a 0 external file memory control 40 and an external file memory 50, a main storage device 11, a central control device 21, a channel device 31, an external file memory control 41, and an external file memory 51. It is limited to two ways: with a 1-series data processing device. Establishment of a normal system by the restart program is therefore simplified.

Furthermore, with regard to the interruption of online service due to the time required to load the program from the external file memory to the main storage device, means for eliminating this interruption time will be described in detail with reference to FIG. FIG. 3 is a block diagram of one embodiment of the emergency circuit.
a and 600b are logically summed in a logical sum circuit 601,
This sets the holding flip-flop 603. This holding flip-flop outputs an emergent signal 603a during the emergent operation and is applied to the timing circuit 604 for the emergent operation.
04b, 604c, 604d, and 604f are generated. In addition, the emergence signal 603a is given to a counter circuit 606 which indicates the number of times the emergence is activated via a differentiating circuit 605.
At 06, this overflow signal 606a sets a holding flip-flop 607 which is a repeat emergency signal source. The output of the differentiating circuit 605 is applied to a 1-bit counter circuit 608 which designates the 0 system or 1 system, and generates a 0 system or 1 system instruction signal 608a.

This 0-system and 1-system instruction signal 608a distributes the output of the emergency circuit to the 0-system and 1-system.

The emergency circuit receives a reset signal 600e from the console and a repeat emergency reset signal 600 that can be specified by the program.
d and further reset by an emergency reset signal 600c from the microprogram.

When a failure occurs in the system, an emergency flip-flop 603 is set, and a timing circuit 604 sequentially generates a signal for initialization. That is, the signal 60 first puts both the 0-system and 1-system data processing devices into a system reset state (a state in which various controls are reset, registers are cleared, and the microprogram is stopped).
4a is ANDed with the system designation signal 608a in the AND circuits 611 and 612, and a system reset signal 611 is sent to the data processing devices of the 0 system and 1 system.
a, 612a. At the next timing, a signal 604b for selecting a clock is similarly applied to AND circuits 613 and 614. Clock selection signals 613a, 614 for both data processing devices
It is sent as a. Furthermore, at the next timing, a signal 604c is output to set the processor mode of both systems to active (ACT) and standby (SBY), and in the same way, AND circuits 615, 616, 617, 618
The ACT setting signal 615a,
616a and SBY setting signals 617a and 618a, which are sent to both data processing devices.

Counter circuit 6 indicating the number of emergency activations
06 performs counting using the output obtained by differentiating the output of the holding flip-flop 603, which continues to be set during the emergency operation, in the differentiating circuit 605. The counter circuit 606 outputs a signal 606b when the count value exceeds a certain specified value. For example, if the counter circuit is composed of 4 bits and the specified value is 7 times, the signal 606b becomes 0 until the 7th time, and the signal 606b becomes 1 when the number of times is 8 or more.

The timing circuit 604 further outputs an initial program load (IPL) instruction signal 604.
d is created, and if the number of activations of the emergence is within 7 times, the AND circuits 621 and 62
2, and signals 621a and 622a that transfer control to a fixed address in the main memory are sent to both data processing devices. For example, when the number of activations of the emergence is 8 or more, the AND circuits 623 and 62
IPL which is logically ANDed by 4 and instructs the initial program load from external file memory.
Instruction signals 623a, 624a are sent to both data processing devices.

That is, when a failure occurs, the program runs from the main memory for the first seven times, but when the failure occurs eight times or more, the program is loaded from the external file memory and starts running.

Normally, when passing control to a fixed address in main memory,
Alternatively, if the loading of the program from the external file memory to the main memory is successful, the microprogram issues a signal 600c to reset the emergency mode, and the emergency mode holding flip-flop 603 and the timing circuit 60
Reset 4. However, if the loading of the program from the external file memory to the main memory ends unsuccessfully, the timing circuit will not be reset, so the signal 604f will be reset at a preset timing.
is output and Emergence is started again.

When the counter circuit 606 that counts the number of emergency activations overflows, the holding flip-flop 607 is set and the AND circuit 61
Signals 619a, 6 logically ANDed by 9,620
20a and is sent to both data processing devices, which can be read by a program. This signal can also be programmed to reset the reset signal 600.
Counter circuit 606 and holding flip-flop 607 are reset by sending out d. Further, when an emergency reset is performed from the console, a signal 600e is sent to the holding flip-flops 603 and 60 included in the emergency circuit.
7 and all control circuits are reset.

As explained above, the automatic system restart method of the present invention simplifies the restart processing program in software and has the effect of greatly shortening the interruption time of online services.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional duplex data processing apparatus, and FIG. 2 is a block diagram of an embodiment of the duplex data processing apparatus of the present invention. In the figure, 10 to 14...Main storage device, 20...Central control unit of 0 system, 21...Central control unit of 1 system, 30
...0 system channel device, 31...1 system channel device, 40...0 system external file memory controller, 41...1 system external file memory controller, 50...0 system external file memory, 51 ...1 system external file memory, 60...
...Emergency circuit. FIG. 3 is a diagram showing an embodiment of the emergency circuit according to the present invention. In the figure, 601, 602, 609, 610...OR circuit, 603, 607...Holding flip-flop,
604...Timing circuit, 605...Differentiating circuit, 606, 608...Counter circuit, 611~
624...AND circuit, 600a to 600e...
Emergence circuit input signals, 611a to 62
4a...Emergency circuit output signal, 603
a...emergency signal, 604e...clock signal, 604a to 604f...timing output signal, 609a, 610a...reset signal,
606a...Emergency repeat signal, 6
06b...Emergency standard value overflow signal, 608a...0 system, 1 system designation signal.

Claims (1)

[Claims] 1 Central control unit, main memory unit, channel unit,
In a data processing device with a fully duplex configuration consisting of an external file memory, the method includes means for specifying either system 0 or system 1 of the duplex data processing device in the event of a system failure, and automatically reconfigures a normal system. It has an emergency circuit, a timing circuit for initializing the redundant data processing device, and a counter circuit that indicates the number of activations of the emergency circuit, and when the count value of the counter circuit is within a specified value, the main memory An automatic system restart method characterized in that a program is run from a fixed address in the counter circuit, and when the count value of the counter circuit is greater than or equal to a specified value, the program is loaded from a designated external file memory.