JPS6233678B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a sample-and-hold circuit that samples and holds an input signal, which is often used in the input section of an A/D converter.

FIG. 1 is an electrical circuit diagram showing an example of a conventional sample-and-hold circuit. During sampling, that is, when the input signal Vin is applied to the input terminal 1 with the switch S1 closed, the capacitor C1 is charged by the amplifier A1. During hold, switch S1 is turned off, and the voltage across capacitor C1 charged during sampling is output as output Vout via buffer amplifier A2. (The above switch S1 is S/H (sample/hold) from the terminal.
Controlled by command signals. ) In a sample-and-hold circuit with such a configuration, if the input offset voltage of amplifier A1 is Vos ₁ , the output is
Vout becomes Vout = Vin - Vos ₁ , which causes an error by the input offset voltage. Therefore, in order to obtain a sample-and-hold circuit with sufficient accuracy, an expensive amplifier with a small input offset voltage and a small temperature coefficient is required.
In addition, it is difficult to integrate such a high-performance amplifier and switch circuit as one unit, so IC
There has never been a good sample-and-hold circuit implemented as such.

The present invention has been made in order to solve the above problems, and an object of the present invention is to realize a sample-and-hold circuit in which the input offset voltage of the amplifier does not appear as an error in the output.

In order to achieve the above object, the first gist of the present invention is to provide an input terminal to which an input signal is applied, a first switch whose one terminal is connected to this input terminal, and a first switch to which an input signal is applied. a first operational amplifier having the other terminal of the switch applied to its non-inverting input terminal; a capacitor having one end connected to the inverting input terminal of the first operational amplifier and the other end connected to a common; a second switch connected between one end and the output terminal of the first operational amplifier; a first resistor whose one end is connected to the output terminal of the first operational amplifier; a second operational amplifier whose other end is connected to its inverting input terminal; a second resistor which connects the inverting input terminal and output terminal of the second operational amplifier; a third switch connecting an associated output to the non-inverting input terminal of the first operational amplifier.

The second gist of the present invention is to provide an input terminal to which an input signal is applied, a first switch whose one terminal is connected to the input terminal, and a first switch to which an input signal is applied.
a first operational amplifier, the other terminal of which is applied to its non-inverting input terminal;
a first capacitor connected to the inverting input terminal of the operational amplifier and having the other end connected to a common; a second capacitor connected between the one end of the first capacitor and the output terminal of the first operational amplifier; a first resistor having one end connected to the output terminal of the first operational amplifier; a first switch having the other end connected to the first resistor; and a fourth switch. a second operational amplifier whose other end is connected to its inverting input terminal; a second resistor whose other end is connected to the output terminal of the second operational amplifier and the other end of the first resistor; a second capacitor connecting the inverting input terminal and the output terminal of the operational amplifier; and a third capacitor connecting the output terminal of the second operational amplifier and the non-inverting input terminal of the first operational amplifier. The circuit consists of a sample-and-hold circuit equipped with a switch.

The present invention will be explained below based on the drawings.

FIG. 2 is an electrical circuit diagram showing one embodiment of the present invention. 11 is an input terminal to which the input signal Vin is applied, S11 is a first switch whose one end is connected to this input terminal 11, and A11 is this first switch S.
the first whose non-inverting input terminal is connected to the other end of 11;
C11 is a capacitor (for charging) whose one end is connected to the inverting input terminal of this first operational amplifier and the other end is connected to a common (for charging), and S12 is a capacitor between the one end of this capacitor C11 and the first operational amplifier. A second switch R1 connected between the output terminal of A11 has one end connected to the first operational amplifier A11.
A12 is a second operational amplifier whose other end is connected to its inverting input terminal, and R2 is the inverting input terminal of this second operational amplifier A12. A second resistor S13 is a third switch that connects the output terminal of the second operational amplifier A12 and the non-inverting input terminal of the first operational amplifier A11. 12 is the switch S11, S
This is an S/H command input terminal to which an S/H (sample and hold) command signal for controlling S12 and S13 is applied.

During sampling, switches S11 and S12 are closed by the S/H command signal, and switch S13 is opened. At this time, the inverting input terminal and the output terminal of the amplifier A11 are connected to form a non-inverting amplifier with a gain of 1. Since the inverting input terminal and the non-inverting input terminal of the amplifier A12 are connected through the resistor R1, both ends of the resistor R1 have the same potential, and as a result, no current flows through the resistor R1, resulting in a state equivalent to an open circuit. Therefore, the amplifier A12 has a feedback resistor R
A non-inverting amplifier with a gain of 1 having a gain of 2 is constructed.
When input voltage Vin is applied to input terminal 11, capacitor C11 is charged by amplifier A11 according to the input voltage. When charging is completed, the charging voltage Vc of the capacitor C11 becomes Vc=Vin- _Vos11 (1), where the input offset voltage of the amplifier A11 is _Vos11 .

During hold, switches S11 and S12 are opened by the S/H command signal, and switch S1
3 is closed. At this time, the amplifier A12 has a resistance R
1 and R2 together form an inverting amplifier with a gain of -1 (when R1=R2). Amplifier A11 and A
The entire loop including A12 constitutes a non-inverting amplifier (referred to as A) with a gain of 1, and the non-inverting input terminal of the amplifier A11 is the inverting input terminal of the non-inverting amplifier A (since it is inverted by the amplifier A12). Therefore, the inverting input terminal of amplifier A11 becomes the non-inverting input terminal of non-inverting amplifier A (for the same reason as above). That is, the charging voltage Vc of capacitor C11
is applied to the non-inverting input terminal of non-inverting amplifier A composed of amplifiers A11 and A12, and
The output voltage Vout, which is fed back to the inverting input terminal of the output terminal, is balanced via the input offset voltage. In other words, Vout=Vc+Vos ₁₁ (2). Here, by substituting equation (1) into equation (2), Vout=Vin−Vos ₁₁ +Vos ₁₁ =Vin. i.e. the input offset voltage of the amplifier
Vos ₁₁ is canceled, and an output voltage Vout that accurately corresponds to the input voltage Vin can be obtained.

Figures 3 1 to 5 are samples of the above configuration.
This shows a time chart of each part of the hold circuit, and shows the case where the input voltage Vin changes from Vin1 to Vin2. Vos ₁₂ is amplifier A12
is the input offset voltage of As shown in FIG. 3, the input offset voltage of the amplifier appears in the output voltage Vout during sampling, but it is canceled and does not appear during hold. Offset during the sample interval can be eliminated by adjusting the offset voltage of either amplifier.
Since this offset can be observed as a rectangular wave when the input is 0, adjustment is easy.

According to the sample-and-hold circuit having such a configuration, the influence of the input offset voltage of the amplifier does not appear on the output during the hold period, so there is an advantage that an inexpensive amplifier with poor offset characteristics can be used.

In addition, the hold capacitor C11 is connected to the amplifier A1.
1 loop, the charging time is shortened. Furthermore, since high-speed amplifiers with poor offset characteristics can be used as the amplifiers A11 and A12, high-speed operation of the sample-and-hold circuit as a whole can be easily realized.

Also, since amplifier A12 is in the loop, gain errors are less of a problem, so large open loop gains are not required.

Furthermore, since the requirements for (the performance of) the amplifiers A11 and A12 are moderate, there is an advantage that they can be easily integrated into ICs by adopting a configuration such as a CMOS operational amplifier, for example.

Furthermore, since the input and output of the sample and hold circuit are buffered, connection with other circuits is easy.

FIG. 4 is an electrical circuit diagram showing a second embodiment of the present invention. The same parts as in the first embodiment (FIG. 2) are given the same reference numerals, and their explanation will be omitted. In this embodiment, the second
A second sample and hold circuit is added to the output side of the circuit shown in the figure. Assuming that the entire sample and hold circuit of this embodiment is SH1, in the added second well-known sample and hold circuit SH2, S21 is a switch whose one end is connected to the output terminal of the amplifier A12, and C22 is a switch whose one end is connected to the switch S2.
1 and the other end is connected to the common (for charging), A23 is the capacitor C22
A non-inverting buffer with a gain of approximately 1, the input terminal of which is connected to the one end of the buffer, may be a simple one such as a source follower. The output of buffer A23 is fed back via the switch S13.

Switch S21 closes during the hold period of sample/hold SH1 (of the S/H command signal),
Capacitor C22 is charged by the offset-free output voltage from amplifier A12. During the sample period of SH1, the switch S21 is opened, and the output based on the charging voltage of the capacitor C22 charged during the hold period is output from the buffer A.
It is output from 23. As a result, as shown in the time chart of FIG. 3, the output Vout of the sample-and-hold circuit becomes the same voltage output in both the sample period and the hold period without being affected by the offset.

In addition to the above-mentioned advantages of the first embodiment, the sample-and-hold circuit configured in this manner has the advantage that offset adjustment is not required.

In the embodiment shown in Fig. 4, if you want to obtain a gain between Vin and Vout, by inserting a resistor circuit as shown in Fig. 5 on the output side, Vout = R _A + R _B / R _B Vin (t −1) can obtain the output expressed as (Vin(t
-1) means the previous sample).

FIG. 6 is an electric circuit diagram showing a third embodiment of the present invention, in which an inverting amplifier including amplifier A12 in the first embodiment is provided with an output hold function. Similar to FIG. 4, the same parts as in the embodiment of FIG. 2 are designated by the same reference numerals, and their explanation will be omitted. In the figure, S31 is a switch inserted between the resistor R1 and the inverting input terminal of the amplifier A12, and C32 is a capacitor (for charging) connecting the output terminal of the amplifier A12 and the inverting input terminal.

Switch S31 is closed during the hold period of the S/H command signal, and capacitor C32 is connected to amplifier A12.
is charged corresponding to the offset-free output voltage. In the sample period, the switch S31 is opened, and the output based on the charging voltage of the capacitor C32 charged in the hold period is sent to the amplifier A1.
Output from 2. A sample of such a configuration
According to the hold circuit, the second embodiment (Fig. 4)
As in the case of , it is possible to obtain an output without the influence of offset over both the sample period and the hold period, as shown in the time chart shown in FIG. 3.

The advantages of this embodiment are the same as those of the first embodiment, but in this case, the non-inverting input terminal of amplifier A12 is connected to the common, so depending on the input voltage, the output level of amplifier A11 can be large. As a result, the operating speed may be somewhat limited.

By applying the resistor circuit shown in FIG. 5 to the cases of FIGS. 2 and 6 in the same way as the case of FIG. 4 (connecting one end of resistor R _A to operational amplifier A12), Vin and Gain can be obtained between Vout.

As described above, according to the present invention, a sample and hold circuit in which the input offset voltage of the amplifier does not appear as an error in the output can be realized with a simple configuration. It also has excellent advantages such as the use of inexpensive amplifiers, high-speed operation, and easy integration into integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram showing an example of a conventional sample-and-hold circuit, FIG. 2 is an electric circuit diagram showing a first embodiment of the present invention, and FIG. 4 is an electrical circuit diagram showing a second embodiment of the present invention, and FIG. 5 is an electrical circuit diagram showing a modification of the embodiment shown in FIG. 4. The circuit diagram, FIG. 6, is the third embodiment of the present invention.
FIG. 1, 11...Input terminal, Vin...Input signal, S
1, S11, S12, S13, S21, S31...
...Switch, A1, A2, A11, A12...Operation amplifier, C11, C22, C32...Capacitor, R1, R2...Resistor, SH2...Second sample-and-hold circuit.

Claims (1)

[Claims] 1. An input terminal to which an input signal is applied, a first switch whose one terminal is connected to this input terminal, and whose other terminal is connected to its non-inverting input terminal. a first operational amplifier connected to the inverting input terminal of the first operational amplifier; a capacitor having one end connected to the inverting input terminal of the first operational amplifier and the other end connected to a common; the one end of the capacitor connected to the output terminal of the first operational amplifier; a second switch connected, a first resistor having one end connected to the output terminal of the first operational amplifier, and a second operational amplifier having the other end connected to the inverting input terminal of the first resistor. And this second
a second resistor connecting the inverting input terminal and the output terminal of the operational amplifier; and a second resistor connecting an output related to the output of the second operational amplifier to the non-inverting input terminal of the first operational amplifier. Sample/hold circuit with 3 switches. 2. The sample and hold circuit according to claim 1, wherein a second sample and hold circuit is inserted and connected between the output terminal of the second operational amplifier and the third switch.
hold circuit. 3. An input terminal to which an input signal is applied, a first switch having one terminal connected to this input terminal, and a first operational amplifier to which the other terminal of the first switch is applied to its non-inverting input terminal. and a first capacitor having one end connected to the inverting input terminal of the first operational amplifier and the other end connected to the common;
a second switch connected between the one end of the first capacitor and the output terminal of the first operational amplifier; and a first resistor, one end of which is connected to the output terminal of the first operational amplifier. , a fourth switch to which the other end of the first resistor is connected to one end thereof, a second operational amplifier to which the other end of the fourth switch is connected to its inverting input terminal, and the second operational amplifier a second resistor connected to the output terminal of the second operational amplifier and the other end of the first resistor; and a second resistor connected to the inverting input terminal of the second operational amplifier and the output terminal of the second operational amplifier.
and a third switch connecting the output terminal of the second operational amplifier and the non-inverting input terminal of the first operational amplifier.