JPS6233679B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an ultraviolet erasable memory device that facilitates the formation of redundant circuits for improving yield.

In the field of memory, capacity increases are occurring at a rapid pace, and in order to meet this market demand, there have been major changes in design technology, wafer manufacturing technology, etc. EPROM with ultraviolet irradiation erasable floating gate structure
For example, in terms of design technology, 2K bits had 2 elements/bit, whereas 8K bits and above had a 1 element/bit configuration. Furthermore, as manufacturing technology advances in miniaturization, the channel length of memory transistors is becoming smaller as the number of bits increases, and for 64K bits, it has been reduced to about 3.0 μm. To meet the demand for even larger capacity, there is no other way in terms of design technology, and the only way is to push for further miniaturization.

However, this comes with a reduction in yield (the ratio of good IC chips to manufactured IC chips). That is, if the capacity is increased without miniaturization, the chip area will increase, the proportion of manufacturing defects per chip will increase, and the yield will decrease. Further, if miniaturization is carried out, manufacturing defects of a size that has not been a problem in the past become a problem, which lowers the yield.

To eliminate this problem, it would be possible to create defect-free manufacturing technology, but it is not easy. Redundant circuit technology is a technology that focuses on this point.

This is a technology devised by IBM's Sakalay and others, and similar ideas have been announced by other companies. It incorporates circuitry containing redundant memory elements that can repair defective memory elements.
This is a technology that configures memory ICs. The majority of ICs that are found to be defective in wafer state tests have very small defects, with most defects ranging from one to several bits. Therefore, if these defective bits are repaired using a repair circuit, the yield will increase dramatically.

The present invention has been made in consideration of the above points, and relates to an ultraviolet irradiation type nonvolatile memory device, and is aimed at easily realizing a redundant circuit for the above-mentioned repair. below,
First, a conventional example will be explained with reference to FIGS. 1 to 3, and then the present invention will be explained.

FIG. 1 shows, as a conventional example, a block diagram of a memory IC that includes redundant circuits in the row direction. In this figure, 1, 2, and 3 are address buffers, and for input signal A _p , A _p and
Creates an in-phase signal and an inverted signal, such as _p . Reference numerals 4, 5, and 6 are address program control circuits, which can program the address so that when an address containing a defective transistor is selected, a spare transistor is accessed. Reference numeral 7 denotes a use determining circuit that determines whether or not to use a redundant circuit for repair. Further, 8 is a spare second memory element group provided for repair, and 9 is a block of the regular first memory element group. Also, the transistors Q ₁ , Q ₂ , Q ₃ ,
_Q4 is an enhancement type field effect transistor, and _Q5 is a depletion type field effect transistor. In addition, the following Q ₁ ~
_Q5 is simply called a transistor.

Next, this operation will be briefly explained.

First, consider that there is a defective bit, its row address is detected, and that it is to be repaired. First, the use determination circuit 7 is activated, the output A is set to "L", and the transistor _Q4 is turned off. When output A is “H”, line B is at ground level, but when output A is “L”, transistor Q ₅
acts as a negative terminal on the power supply _Vcc side of transistors Q ₁ , Q ₂ , and Q ₃ . The inputs to the transistors Q ₁ , Q ₂ , Q ₃ are programmed into the address program control circuits 4 , 5 , 6 for the address inputs A _p , A _i , . . . A _o so that they correspond to the row address of the defective bit. By applying this, all bits can be set to "L" when a defective bit address is input. As a result, the line B is pulled up by the transistor _Q5 and becomes "H", and the spare second memory element group 8, which is the spare row, is selected. At this time, in order to prevent double selection of a line containing normal defective bits and a spare line, the signal of line B is also input to the input of the decoder so as to inhibit the line containing defective bits.

Next, the contents of the use determination circuit 7 and the address program control circuits 4, 5, and 6 will be described. Conventional fuses are normally used in these circuits. An example of the use determining circuit 7 is shown in FIG. This circuit has the function of setting the output A to "H" when repair is not necessary and "L" when repair is necessary. When repair is required, the enhancement type transistor is activated by setting terminal G to “H”.
Q ₁₃ is turned on and fuse F ₂ is cut off, which causes the depletion type transistor Q ₁₄ as a pull-down load to operate and output A to become "L". Output A
becomes “L”, transistor Q ₄ in FIG. 1 is turned off, and the address to be repaired is transferred to transistors Q ₁ ,
As mentioned above, it becomes active from Q ₂ and Q ₃ .

When repair is not required, the terminal G is set to "L" or left open, and the transistor _Q15 causes the output A to become "H".

Next, address program control circuits 4, 5, and 6 will be described. FIG. 3 shows an example thereof, which corresponds to the address program control circuit 5 of FIG. In FIG. 3, transistors Q ₆ , Q ₇ , Q ₈ , Q ₉ , Q ₁₀ are
It is an enhancement type field effect transistor, and Q ₁₁ and Q ₁₂ are depletion type transistors (hereinafter, both are simply referred to as transistors). Input C is a signal that is set to "L" when a defective address is programmed by these circuits, and set to "H" at other times. Also, terminal D ( _Vpp )
is a power supply terminal to which a high voltage of about 21 to 25V is applied only when repair is required, _Vcc is a circuit power supply of about 5V, and _INV1 and _INV2 are inverters.

Now, if the defective address is A _i = "L", then "L" is input to input C because A _i = "L" and _i = "H". At this time, transistor Q ₇ is turned on and point E becomes "L", so transistor Q ₈
remains off and fuse _F1 cannot be cut. At this time, the fuse _F1 has a pull-up effect, and the point F becomes "H", turning on the transistor _Q10 and turning off the transistor _Q9 . At this time, the output a _i is _i
becomes.

Further, when A _i = "H", _i = "L" and when the input C becomes "L", the point E becomes "H", the transistor Q ₈ is turned on, and the fuse F ₁ is cut off. If fuse _F1 is blown, point F is the transistor
Due to the pull-down effect of _Q12 , it becomes "L", turning off transistor _Q10 and turning on transistor _Q9 . This no longer changes even if the input C becomes "H". In this case, a _i =A _i . In other words, to summarize, if A i is "0" when inputting C to "L", that is, at the time of address programming, only when A _i is "0" after programming, that is, after input C becomes "H". _i becomes “0”,
When the input C is input, if the signal A _i is "1", the output _{a i becomes} "0" only when the signal A i is "1". In other words, if the same address that has been programmed is input, the output will be
_i becomes "L", and at this time, transistors Q ₁ , Q ₂ , and Q ₃ in FIG. 1 turn on, line B becomes "H", and the spare row of the second memory element group 8 becomes selected. In this way, address program control circuits 4 to 6 using fuses F ₁ and F ₂
The defective bit is repaired by adding a redundant memory element, that is, a second memory element group 8.

Now, a drawback of the conventional memory device described above is that it uses a fuse. The current for cutting a fuse can vary depending on the manufacturing process, and it is well known that if it is not well controlled, a blown fuse may bond again, causing reliability problems.

The present invention has been made in view of the above points, and is based on a floating gate field effect transistor manufactured in the same wafer manufacturing process as that used to form memory elements, and a control circuit for repairing defective bits. That is, in the example above,
It is used in the use determination circuit 7 and the address program control circuits 4 to 6 in place of fuses.

4a and 4b are circuit diagrams for explaining the principle of the present invention. FIG. 4a is a circuit using a field effect transistor having a floating gate for memory used in this invention, and FIG. This is a conventional circuit compared with FIG. 4a. The conventional circuit of FIG. 4b can be replaced by the circuit of FIG. 4a.
In Fig. 4a and b, Q ₁₆ , Q ₁₇ , and Q ₁₉ are ordinary enhancement type field effect transistors;
_F3 is a fuse, and _Q18 is a floating gate field effect transistor. Now, in order to disconnect the fuse _F3 shown in FIG. 4b, it is sufficient to input "H" to the input terminal and turn on the transistor _Q16 .
To achieve a similar effect for Figure 4a, first,
A high voltage, for example 21-25V, is applied to the terminal _Vpp (which shall also represent the voltage at the same time). In this state, “H” is applied to terminal J (this level is also as high as 21
A level signal of V to 25 V) is applied. Then, 21V is applied to the gate of transistor _Q18 , and about 15 to 18V is applied to the drain, and due to the breakdown phenomenon near the drain, the floating gate FG
A charge is injected into the The injected charges will remain here unless erased by irradiation with ultraviolet light or the like. After doing this, change the voltage _Vpp to 5V
When lowered to a voltage in the vicinity, transistor Q ₁₈ is completely off, producing the same effect as blowing fuse F ₃ in FIG. 4b.
Transistor _Q19 is a series load transistor for efficiently injecting charge into transistor _Q18 .

FIG. 5 shows an embodiment of the present invention corresponding to FIGS. 2 and 3 using the circuit shown in FIG. 4b above.

In FIG. 5, when there is a defect in the memory and repair is required, a high voltage is applied to the input terminal G after raising the voltage _Vpp to a level of 21 to 25V. This will turn on transistor _Q13 and
Charge is injected into the floating gate of _Q22 . If charge is injected, the transistor _Q22 will be completely turned off when the voltage of _Vpp is lowered to around 5V. If repair is not required, leave input terminal G open to connect pull-down load transistor Q ₁₅
is activated, the input terminal G is at the "L" level, that is, the transistor _Q13 is turned off, and the output A is at the "H" level.

In FIG. 6, the voltage at the terminal V _pp is set to 21 to 25 V during programming. By setting the input C to "L", the transistor Q ₇ is turned on and off according to the input A _i (i.e., _{the i} input). When input A _i is “H” and transistor Q ₇ is off,
A voltage close to V _pp is applied to point E, and transistor Q ₈
turns on. As a result, charge is injected into the floating gate of transistor _Q20 , and when the voltage of _Vpp is lowered to around 5V, transistor _Q20 is completely injected.
is in the off state. After that, input A _i is “H”
The output _i becomes "L" only when Conversely, when input C is set to "L", input A _i is set to "L", input _i is "H", transistor Q ₇ is turned on, and point E is at "L" level. Therefore, transistor Q ₈ remains off and no change occurs to transistor Q ₂₀ . Therefore,
Transistors Q ₂₁ and Q ₂₀ remain as load transistors for transistor Q ₈ . After this, even if input C is set to "H", point E will always be "L",
Point F is always "H" and transistor _Q10 is turned on. At this time, after input C becomes “H”,
Only when the input A _i is "L", the output _i is "L". In this way, the output i becomes "L" only when the address to be programmed with the input C set to "L" is input after _programming , and the circuit shown in FIG. 3 is replaced.

In this way, the circuits in Figures 5 and 6 are similar to those in Figures 2 and 6.
It can be replaced with the circuit shown in FIG. 3, eliminating the need for fuses.

Now, there is a big problem in using the above-mentioned additional circuit for repair using the floating gate type field effect transistor as an ultraviolet irradiation type memory. That is, when erasing memory information, the memory transistor information in the use determination circuit 7 and the address program control circuits 4 to 6, that is, the information of the transistors Q ₂₀ and Q ₂₂ in FIGS. 5 and 6 in the above example, is It also means erasing it. Therefore, when using a floating gate type field effect transistor in a repair circuit, it is necessary to change the matrix-like memory element and ultraviolet erasure time, i.e., it is very difficult to erase.
Must be at least an order of magnitude longer, or must be non-erasable.
It is necessary to ensure that the transistors Q ₂₂ and Q ₂₀ in FIGS. 5 and 6 do not lose (or do not easily lose) information due to ultraviolet light.

In this method, for example, an aluminum film may be deposited only on these transistors Q ₂₀ and Q ₂₂ .

Figure 7 shows the location 2.5cm from the memory transistor.
It shows the erasing characteristics with and without an aluminum film when irradiated with a germicidal lamp with a wavelength of 2537 Å, indicating that it can fully fulfill this role.

FIG. 8 is an enlarged plan view of the circuit shown in FIG. 6 realized by an N-channel silicon gate process.
The same reference numerals are used for the same parts as those in the figure.
In this figure, 10 is polysilicon, 11 is a diffusion layer,
12 is a floating gate, 13 is an aluminum film,
14 is a contact region of the polysilicon diffusion layer. The floating gate 12 of the floating gate field effect transistor is made of an aluminum film 13.
completely covered.

As explained in detail above, the present invention provides an ultraviolet erasable memory device having a defective bit repair function, in which conventional fuses are replaced by a field effect memory device having a floating gate manufactured in the same process as the semiconductor substrate. Since transistors are used, it is possible to realize an ultraviolet erasable memory device in which defective bits can be repaired at a high yield using conventional manufacturing techniques. Furthermore, the field effect memory transistors used at least in the use determination circuit and the address program control circuit are configured such that the ultraviolet irradiation time necessary to erase the information written therein is controlled by the ultraviolet irradiation time required to erase the information written therein. Since the ultraviolet irradiation time is more than an order of magnitude longer than the time required to erase information written in two memory element groups, the use decision circuit and address program control circuit can be used even when erasing information in matrix-shaped memory elements. There is an advantage that the information in the field effect memory transistor used in the process is not erased, and the function of the additional circuit for repair can always be performed.

[Brief explanation of the drawing]

Fig. 1 shows an example of a block diagram of a memory device having a defective bit repair function, Fig. 2 shows a conventional example of the use decision circuit in the block diagram of Fig. 1, and Fig. 3 also shows an address program block diagram. Figures 4a and 4b are circuit diagrams for explaining the principle of the present invention. Figures 5 and 6 are circuit diagrams illustrating an embodiment of the present invention. Figure 7 is a diagram showing a conventional example of a control circuit. FIG. 8 is a diagram showing an example of the erasing characteristics of a floating gate field effect transistor.
FIG. 2 is an enlarged plan view of main parts when applied to the circuit shown in the figure. In the figure, 1 to 3 are address buffers, 4 to 6 are address program control circuits, 7 is a use determination circuit, 8 is a second memory element group, 9 is a first memory element group, 10 is polysilicon, 11 12 is a diffusion layer, 12 is a floating gate, 13 is an aluminum film, 14 is a contact region, Q ₁ to Q ₂₂ are transistors, A _i and _i are inputs, and _i is an output. In addition,
The same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1 A first memory element group using field effect transistors having floating gates that can erase information by irradiation with ultraviolet rays arranged in a matrix, and a malfunctioning transistor in this first memory element group. In some cases, a second group of memory elements using field effect transistors having floating gates arranged in a spare matrix, which are accessed by selecting this address, and the second group of memory elements are used. In the memory device, the memory device includes a use determination circuit that determines whether or not to use the memory device, and an address program control circuit that controls access to the address of the spare second memory element group when the use determination circuit operates. The determination circuit and the address program control circuit are configured using field effect memory transistors having floating gates, and the field effect memory transistors used in at least the use determination circuit and the address program control circuit are configured to have a field effect memory transistor having a floating gate. The ultraviolet irradiation time required to erase information is configured to be at least one order of magnitude longer than the ultraviolet irradiation time required to erase information written in the first and second memory element groups arranged in a matrix. An ultraviolet erasable memory device characterized by: