JPS623370A - Multiplication accumulation circuit - Google Patents

Abstract

PURPOSE:To shorten the arithmetic time by storing arithmetic input data by means of two input registers and an auxiliary register which receives the output of one of both input registers and therefore eliminating the need to obtain the initial accumulation value. CONSTITUTION:When a quadratic equation Y=AX<2>+BX+C is obtained, two variable values X<2> and X are supplied to an input register 7 from a host processor (not shown here) via an input terminal 2 prior to an arithmetic operation. Both values X<2> and X are supplied to an input register 8 and an auxiliary register 14 via an input terminal 3. These registers 8 and 14 store three constant values A, B and C in total. Then an arithmetic command signal (a) is supplied from the outside via a control terminal 1 and a scan circuit 5 reads out the contents c1-c5 of a program memory 6 to which an arithmetic sequence is previously incorporated with the timing of a scan signal (b) and advances the arithmetic process. While the register 14 discontinues the replacement of the storage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a multiplication/accumulation circuit that processes digital signals at high speed using multipliers and adders/subtractors.

[Prior art and its problems]

The multiply-accumulate circuit is ΣXt *yi and F=AxBfC
It is mainly applied to fast Fourier transform (FFT) and digital filter processing in information processing devices and medical equipment that require the execution of mathematical expressions such as matrix operations and vector operations.

As a conventional multiplication/accumulation circuit of this type, one is known that performs arithmetic processing using a multiplier that multiplies two pieces of arithmetic data and an adder/subtracter that accumulates the output of this multiplier and outputs the accumulated output to the outside.

An example of such a conventional multiplication/accumulation circuit is shown in FIG. 3. Its operation will be explained with reference to the operation time chart of FIG. 4. Here, we use a quadratic equation (Y=AX2
+BX+C) is given as a -example.

Here, l is a control terminal, 2 and 3 are input terminals, 4 is an output terminal, 5 is a scan circuit, 6 is a program memory, and 7
and 8 is an input register, 9 is a 0 register, 10 is a selection circuit, 11 is a multiplier, 12 is an adder/subtractor, and 13 is an output register.

First, prior to the calculation, the same number of variable values and constant values are input to the two input registers 7.8 from the outside (not shown, for example, a host processor) via their respective input terminals 2.3. 0 Next, when an arithmetic command signal a is input from the outside via the input terminal l, the scan circuit 5 reads out the contents 01 to C5 of the program memory 6 in which an arithmetic sequence has been incorporated in advance, and proceeds with the arithmetic processing. .

In the multiplier 11, the variable value of the input register 7.8 is multiplied by the constant value, and in the adder/subtractor 12, the output d of the multiplier 11 is multiplied by the 0 register 9 selected by the selection circuit 10.
Alternatively, addition and subtraction with the output e of the adder/subtractor 12 are repeated a certain number of times until the formula is completed, and the calculation result f
is output to the output terminal 4 via the output register 13, and the process is completed. Table 1 shows the calculation process for quadratic equations.

Table 1 However, in such a multiplication accumulation circuit, a 0 register 9 is provided as hardware for storing O in order to obtain the initial value of accumulation, and an extra value (
1) and perform auxiliary arithmetic processing, such as CXl+0, which increases the computation time. In particular, when formulas are processed continuously, this extra processing accumulates, further prolonging the computation time, which has the disadvantage of reducing the processing efficiency of the circuit.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiplication/accumulation circuit that can eliminate the above-mentioned drawbacks and shorten calculation time. , 1 [Summary of the Invention] In order to achieve the above object, the present invention stores calculation input data 1 using two input registers and an auxiliary register that receives the output of one of the input registers, and stores the operation input data 1 in the auxiliary register. cumulative to
゛Reduced calculation time by memorizing initial values
1. Let me have some free time.

[Embodiments of the invention]

The following is a detailed description of the invention with reference to the drawings.
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An embodiment of the present invention is shown in FIG.
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The time chart is shown in Figure 2.

Here, the same parts as in FIG. 3 are denoted by the same reference numerals, and the explanation thereof will be omitted. In the present invention, the output of one input register 8 is supplied to the auxiliary register 4.

Stores the cumulative initial value input at the beginning. The output of the auxiliary register 4 is supplied to the selection circuit 10.

The control signals C2 to C5 from the program memory 6 are input to the input registers 7 and 8, the selection circuit 10, and the multiplier 11, respectively.
, adder/subtractor 12. It is supplied to the output register 13.

Next, as an example of arithmetic processing, we will use the quadratic equation (Y=AX
2+BX+C) as an example, the operation of the multiplication/accumulation circuit shown in FIG. 1 will be explained.

First, prior to calculation, calculation data arranged according to a mathematical formula is transferred from an external device 1, for example, a host processor (not shown), to an input register 7 via an input terminal 2, and input two variable values x2.
and X are supplied to the input register 8 and the auxiliary register 14 via the input terminal 3, and a total of three constant values A&B and C are stored in these registers 8 and 13. As a result of this input operation, the two constant values A and B that were input later are held in the input register 8, and the cumulative initial value C that was input first is stored in the auxiliary register 14.

Next, when an arithmetic command signal a as shown in FIG. 2 is input from the outside via the control terminal l, the scan circuit 5
At the timing of the scan signal shown in FIG. 2, the contents C8 to C5 of the program memory 6 in which the calculation sequence has been previously incorporated are read out, the calculation processing is proceeded, and the auxiliary register 14 stops updating the memory. What is the process of this calculation process?

As shown in FIG. 2, in the multiplier 11, input registers 7.
8 variable value X2. Multiplication of X by constant values A and B AX2
, BX, the adder/subtractor 12 performs addition/subtraction between the output d of the multiplier 11 and the auxiliary register 14 (selected only at the first operation) selected by the selection circuit 1O or the output e of the adder/subtractor 12 in parallel, and the formula is The operation result f from the adder/subtractor 12 is output to the output register 1, which is repeated a certain number of times until completion.
3, and is output to the output terminal 4 to complete the calculation. Table 2 shows the calculation process for quadratic equations.

Table 2 In the present invention, as shown in Table 2, the calculation time can be shortened by storing the initial value of accumulation, which was conventionally calculated, in the auxiliary register 14 before calculation.

〔Effect of the invention〕

As is clear from the above, according to the present invention, calculation input data is stored using two input registers and an auxiliary register that receives the output of one of the input registers.
There is no need to calculate the initial value of accumulation, which has the effect of shortening the calculation time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is an operation time chart of the embodiment shown in FIG. 1. FIG. 3 is a block diagram showing an example of a conventional multiplication/accumulation circuit. 1 is an operation time chart of a conventional multiplication/accumulation circuit. ! ...Control terminal. 2.3...Input terminal, 4...Output terminal, 5...Scan circuit, 6...Program memory, 7.8...Input register,'-:・9...O register, lO...selection circuit, 11... multiplier,
12...addition/subtraction device, 〉To 69 month freezing o C dimension fBB, 2 pro, 70 Fig. 1 - h deaf - (d -o θ, θ (() Q
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Claims (1)

[Claims] 1) A circuit that multiplies and then accumulates calculation data input from the outside, comprising: two input registers that store the calculation data;
a storage circuit configured with an auxiliary register that stores the output of one of the two input registers, a multiplier that multiplies the outputs of the two input registers, and an adder/subtractor that accumulates the output of the multiplier and the cumulative value. and a selection circuit that selects either the output of the auxiliary register or the output of the adder/subtractor, a program memory that controls the storage circuit and the arithmetic circuit, and the contents of the program memory. What is claimed is: 1. A multiplication/accumulation circuit, comprising: a scan circuit for reading out a control circuit; 2) The multiplication and accumulation circuit according to claim 1, wherein the auxiliary register stores an initial accumulation value.