JPS6234420A - Combinational logic circuit - Google Patents

Abstract

PURPOSE:To provide a combinational logic circuit with different logical functions in the application of a normal source voltage and in the application of a higher source voltage by using NMOS type transistors (TR) which have different threshold values as program elements. CONSTITUTION:The 1st MOS TRs T1-T8 which operate with both the 1st potential and the 2nd potential higher than the 1st potential and the 2nd MOS TRs TH1 and TH2 which do not operate with the 1st potential and operate with the 2nd potential are provided as MOS TRs arranged at intersections of input signal lines and output signal lines. The normal source voltage is the 1st potential and the MOS TRs having a normal threshold value operate, but when the source voltage rises from the 1st potential to the 2nd potential, the MOS TRs having a higher threshold value begin to operate to obtain a logical function different from that in the application of the 1st potential.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to improvements in integrated circuits, and more particularly to improvements in combinational logic circuits.

[Conventional technology]

FIG. 2 shows an example of the circuit configuration of a conventional decoder, and Table 11 and Table 2 on the next page are truth tables of the decoder in normal mode and test mode, respectively.

In FIG. 2, 1 and 2 are input signal lines for inputting input data a and b, 3 is an input signal line for inputting control data t, 4.5.6 is inverted input data i,
1. Input signal lines 11 to I3 are input signal lines for inputting τ, and inverters input input data a, b and control data t and output inverted input data d, b, t.
7.8, 9.10 are output signal lines for outputting inverted output data τ, d, e, r, 11.12, 13.14 are outputs for outputting output data c, d, e, f Signal line,
■4 to I7 are inverters for inputting inverted output data τ, d, τ, and below and outputting output data c, d, ゛e, f, G is ground, T1 to TIO are NMO5 type transistors for programming, 2 is a power supply, and R is a load element for adjusting the through current flowing from the power supply 2 to the ground G when the programming NMOS transistors T1 to T10 are in a conductive state. The gates of NMOS transistors T1 to TIO are connected to either input signal lines 1, 2.3 or input signal lines 4.5.6, and their drains are connected to output signal lines 7, 8, 9.
．． 10, and its source is grounded.

Next, the operation of this combinational logic circuit will be explained.

Initially, it is assumed that a voltage, for example 5V, is applied to the power supply (2), the control data t is logically rLJ, and the mode is normal mode. At this time, the programming NMOS transistor T9. whose gate is connected to the input signal line 3. T.I.
O is always in a non-conducting state. Here, input data a, b
When both become rLJ, the programming NMOS transistors T3 and T whose gates are connected to the input signal line 1.2
4. T7. T8 becomes non-conductive. Furthermore, since the inverted data a and b are both in the rHJ state by the inverter It, 12, the gate is connected to the input signal 'fIIA4. Programming NMO8 type transistor Tl, T connected to 5
2. T5. T6 becomes conductive, and a through current flows from the power source 1 to the programming NMO8 type transistor T1. T2. T
5. Flows to ground G through T6. As a result, the inverted output data τ5 becomes rLJ, and the inverter I
4.15.17, output data c, d, f become "H". Also, a program N with a gate connected to the input signal line 1.2.3 and a drain connected to the output signal line 9
MOS type transistor T3. Since T8 and TIO are in a non-conducting state, the inverted output data τ is r
becomes HJ, and the output data e becomes "L".

Next, assume that input data a and b remain rLJ, control data t becomes rHJ, and the test mode is entered. At this time, the programming NMOS transistor T9. whose gate is connected to the human input signal line 3. By newly turning on TIO, the inverted output data c, d, e, f
are both rLJ, and the output data c, d, e, f are rH
Become J.

Output data c, d, which is similarly found for all logical values of input data a, b and control data t,
Truth tables representing the logical values of e and f are shown in Table 11 and Table 2 on page 3. Table 1 is for the normal mode, and Table 2 is for the test mode.

[Problem that the invention seeks to solve]

Conventional combinational logic circuits are configured as described above, so, for example, if you want to realize different logic functions by switching between two modes, normal mode and test mode, in large-scale LSIs, etc., control data is used for input. There is a problem in that a large number of input signal lines 3 and programming NMOS type transistors are required, resulting in a large area.

The present invention has been made in view of these points, and its purpose is to easily switch modes without requiring an input signal line for control data, without increasing area, and to enable different logic. The objective is to obtain a combinational logic circuit that can realize functions.

[Means for solving problems]

In order to achieve such an object, the present invention provides an MO8 type transistor arranged at the intersection of an input signal line and an output signal line, which has a first potential and a second potential higher than the first potential.
A first MOS type transistor that operates at either potential and a second MOS type transistor that does not operate at the first potential but operates at a second potential are provided.

[Effect]

In the present invention, the normal power supply voltage is the first potential, and a MOS transistor with a normal threshold is operating, but when the power supply voltage reaches a second potential higher than the first potential, A MOS type transistor with a high threshold voltage begins to operate and has a logical function different from that when the first potential is applied.

Furthermore, by returning the second potential to the first potential, the original logic function is restored.

〔Example〕

FIG. 1 shows an embodiment of a combinational logic circuit according to the present invention. In FIG. 1, THI and TH2 are programming NMOS type transistors having a high threshold value (in this embodiment, the value is 6.times.). In FIG. 1, the same or equivalent parts as in FIG. 2 are given the same reference numerals. The programming NMOS type transistors T1 to T8 have a normal threshold value (in this example, the value is IV), and their gates are connected to either the input signal line 1.2 or the input signal line 4.5, Its drain is the output signal line 7, 8,
9.10, and its source is grounded. NMOS transistors THI and TH2 are NM
They are connected in the same way as the OS type transistors T1 to T8.

Next, the operation of this combinational logic circuit will be explained.

Initially, it is assumed that the voltage of the power supply V is a first potential, that is, a normal voltage (in this embodiment, the voltage value is 5 V), and the mode is normal mode. At this time, the change in potential of input data a, b and inverted input data D, A is from "0" to "5"■
NM for programs with high thresholds.
OS type transistors THI and TH2 are always non-conductive.

Here, when the input data a and b both become "L", the program NM whose gate is connected to the input signals 'ai and 2
OS type transistor T3. T4. T7°T8 becomes non-conductive. In addition, since the inverted input data a and b are both rHJ by the inverters 1 and 2, the programming NMOS transistor Tl whose gate is connected to the input signal line 4.5.

T2. T5. T6 becomes conductive and the through current connects to the power supply ■
Programming NMOS type transistors TI, T2 . T5. Flows to ground G through T6. As a result, the inverted output data τ, end, end is rLJ
The output data c, d, f become "H" by the inverter I4.15.17. Further, a programming NMOS type transistor T3. having a gate connected to the input signal lines 1 and 2 and a drain connected to the output signal line 9 and having a normal threshold voltage. Since T8 is in a non-conducting state, the inverted output data τ becomes rHJ due to the power supply V, and the output data e becomes rLJ.
become.

Next, input data a and b remain at rLJ, and the power supply
, that is, a potential higher than the normal potential (in this embodiment, the value is 8 V) to enter the test mode. At this time, since the potential changes of the input data a, b and the inverted input data i, τ are from "0" to "8"■, the programming NMOS type transistor TH with a high threshold value
I, TH2 becomes operational. Therefore, the programming NMOS transistors THI and TH2 with high threshold values whose gates are connected to the input signal line 4.5 are newly turned on, and the inverted output data τ2d, e, f are rLJ
and the output data c, d.

e, f becomes rF(J.

A truth table representing the logical values of output data c, d, e, and f similarly determined for all the logical values of input data a and b is shown in Table 32 and Table 4 on the next page.

Table 3 is for the normal mode, and Table 4 is for the test mode. If input data t is excluded, Table 3 is exactly the same as Table 1, and Table 4 is exactly the same as Table 2. That is, this combinational logic circuit has the same function as a conventional combinational logic circuit.

As described above, by using NMOS type O3 transistors with different threshold values as programming elements, it is possible to provide a combinational logic circuit with different logic functions when a normal power supply voltage is applied and when a higher power supply voltage is applied. . - Although only the decoder circuit has been described in the above embodiment, it may be used for an AND array or OR array of a programmable logic array or a memory cell array of a read-only memory, and the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As explained above, the present invention operates as a MOS transistor placed at the intersection of an input signal line and an output signal line at both a first potential and a second potential higher than the first potential. a first MO8 type transistor;
A second MOS that does not operate at the potential but operates at a second potential.
By providing a type transistor, different logic functions can be obtained with one combinational logic circuit simply and without increasing the area by simply changing the externally applied power supply voltage according to the normal mode and the test mode.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a combinational logic circuit according to the present invention, and FIG. 2 is a circuit diagram showing a conventional combinational logic circuit. 1.2, 4.5... Input signal line, 7-14...
Output signal line, It, 12. ih~17...Inverter, T1~T8. THI, TH2... NMOS type transistor for programming, ■... Power supply, R...
Load element, G...Ground.

Claims (1)

[Claims] an input signal line arranged in a first direction; an output signal line arranged in a second direction; a gate connected to the input signal line and a drain connected to the output signal line; A combinational logic circuit that has a MOS transistor arranged at an intersection with a signal line, and realizes an arbitrary program depending on whether the MOS transistor is present at the intersection of the input signal line and the output signal line, The MOS transistor has a first MOS transistor that operates at either a first potential or a second potential higher than the first potential.
A combinational logic circuit comprising an OS type transistor and a second MOS type transistor that does not operate at the first potential but operates at the second potential.