JPS6235579A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the productivity of a semiconductor device having preferable and stable characteristics by first epitaxially growing a buffer layer as an N-type, and thermally etching the surface before growing other semiconductor layers. CONSTITUTION:An N-type GaAs buffer layer 2 is grown, for example 2X10<17>cm<-3> of impurity density and approx. 0.2mum of thickness. Then, before an I-type GaAs channel layer 3, an AlGaAs electron supplying layer 4 and an N-type GaAs cap layer 5 are grown on the layer 2, a substrate 1 grown with the layer 2 is contained in the front chamber of an MBE device, in which As atmosphere of approx. 10<-8>-10<-7>Torr is, for example, set, and thermally etched at 750 deg.C for approx. 3min. According to this method, the epitaxial growth of the layer 2 is separated from the grown of other semiconductor layer to select the growing method, and the influence to the energy level of the buffer layer of the boundary level caused by the substrate surface can be suppressed by setting the buffer layer to N-type of low density.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a method for manufacturing a semiconductor device using two-dimensional electron gas as a channel, in which a buffer layer is epitaxially grown as an n-type buffer layer, and the surface of the buffer layer is grown epitaxially before the growth of other semiconductor layers. By thermally etching the semiconductor device, the productivity of the semiconductor device with good and stable characteristics is improved.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for manufacturing a semiconductor device using a two-dimensional electron gas as a channel by spatially separated doping.

Gallium arsenide (G
The practical application of compound semiconductors such as the aAs) system is progressing, and the impurity doping region and the carrier movement region are spatially separated, and high mobility devices such as heterojunction field effect transistors, which use two-dimensional electrons as carriers, are being developed. Semiconductor devices are being developed.

The channel layer where this two-dimensional electron gas is accumulated often doubles as a buffer layer between it and the substrate, and conventionally it has been necessary to make it extremely thick compared to the semiconductor layer in the active region, and the epitaxial growth process This has become a huge burden.

[Conventional technology]

An example of the structure of the heterojunction field effect transistor is shown in FIG.

In this conventional example, a non-doped i-type GaAs layer 13 is formed on a semi-insulating GaAs substrate 11, an aluminum gallium arsenide (^1xGa+-, As) masonry 4 having a smaller electron affinity, and an impurity concentration of, for example, 2×10111LJ″f
n-type GaAs [15] of about f is provided. This i
The type GaAs layer 13 functions as a buffer layer and a channel layer as will be described later, the Δ-IGaAs layer 14 serves as an electron supply layer, and the n-type GaAs layer 15 serves as a cap layer.

In the GaAs layer 14, for example, a region with a thickness of about 5 nm near the interface with the i-type GaAsJi 13 is undoped,
Other regions contain donor impurities with a concentration of about 2XIO"cm-3, and electrons transferred from this layer to the i-type GaAs layer 13 form a two-dimensional electron gas 13e near the heterojunction interface.N-type Source and drain electrodes 16 are provided on the GaAs layer 15, and the n-type GaAs layer 15 between these two electrodes is selectively etched, and a gate electrode 17 provided in contact with the AlGaAs layer 14 is used to remove the two-dimensional electron gas 13e. Transistor operation is performed by controlling the surface concentration of .

The energy level of the conventional heterojunction field effect transistor as explained above is as shown in FIG. It is stored in the energy level well of the conduction band.The bending of this energy level is determined by the forbidden band width and the Fermi level E of the semiconductor single crystal that constitutes the semiconductor single crystal.

[Problem that the invention seeks to solve]

The energy level shown in FIG. 4 fa) is when the i-type GaAs layer 13 serving as the buffer layer has a sufficient thickness of, for example, about 0.8 μm or more. i-type GaAsJi13
As shown in Figure 4 (bl), if the
The lowest part of the conduction band near the interface between the layer 13 and the AlGaAs layer 14 is above the Fermi level E, and no two-dimensional electron gas 13e is accumulated.

This is because an interface level is formed at the interface between the semi-insulating GaAs substrate 11 and the i-type GaAs buffer layer 13, and the energy level of the entire non-doped i-type GaAs layer 13 is raised due to this interface level. It is. It is believed that the formation of such an interface state is due to the fact that the vicinity of the surface of the substrate 11 has become p-type due to adhesion of impurities such as carbon (C), oxygen (0□), or disordered crystals. It is being

Precise semiconductor stacked structures such as heterojunction field effect transistors are conventionally manufactured using the molecular beam epitaxial growth method (MBE).
However, most of the required growth time is occupied by the buffer layer, and there is a need for a means to improve the throughput of epitaxial growth.

Furthermore, while a semiconductor layer is grown thickly by the MBE method, a characteristic large surface defect called an oval defect tends to gradually increase.
Improvements are needed from this point as well.

[Means for solving problems]

The above problem is solved by epitaxially growing an n-type semiconductor buffer layer on a semi-insulating compound semiconductor substrate, and then performing a vacuum heat treatment to etch the surface of the buffer layer, without exposing it to the atmosphere. This problem is solved by the method of manufacturing a semiconductor device according to the present invention, in which a required semiconductor layer including a non-doped i-type semiconductor channel layer in which gas is accumulated is epitaxially grown on the buffer layer.

[For production]

According to the present invention, the epitaxial growth of the buffer layer is separated from the growth of other semiconductor layers, and the growth method thereof is selected;
Furthermore, the influence of interface states caused by the substrate surface on the energy level of the buffer layer is suppressed by making the buffer layer n-type with a low concentration.

Although the surface of the buffer layer is once exposed to the atmosphere, the interface states generated between the buffer layer and another semiconductor layer grown thereon are suppressed by thermal etching of the surface of the buffer layer.

By separating the epitaxial growth of the buffer layer in this way, it becomes possible to select, for example, the vapor phase growth method for the buffer layer, and the MBE method for the channel layer, electron supply layer, etc. Throughput can be easily improved, and oval defects peculiar to the MBE method can also be suppressed.

The interface states between the substrate and the buffer layer and between the buffer layer and the channel layer are suppressed as described above, and a conduction band well is formed deeper than the Fermi level near the interface between the channel layer and the electron supply layer, resulting in a high surface concentration. Two-dimensional electron gas is accumulated.

〔Example〕

The present invention will be specifically explained below using examples.

FIG. 1 is a schematic side sectional view showing the process order of an embodiment in which the present invention is applied to a heterojunction field effect transistor, and FIG. 2 is a diagram showing its energy level.

Refer to FIG. 1 fat: An n-type GaAs buffer layer 2 is grown on a semi-insulating GaAs substrate 1 to, for example, an impurity concentration of 2XIO"c+n-' and a thickness of about 0.2 .mu.m by a vapor phase epitaxial growth method.

As a vapor phase epitaxial growth method, for example, a chloride method using metallic Ga- as a gallium (Ga) source and arsenic trichloride (AsCh) as an arsenic (As) source, or trimethyl gallium (Ga (CH3) 3) as a Ga source, Metal-organic pyrolysis vapor phase growth method using arsine (AsH3) as an As source (
MOCVD method) etc. are applied.

See FIG. 1(b): On the n-type GaAs buffer layer 2,
Non-doped) type GaAs channel layer 3, AlGaA
The s-electron supply layer 4 and the n-type GaAs cap layer 5, ? I
Epitaxial growth is performed using the BE method.

To perform this growth, first, the substrate 1 on which the buffer layer 2 has been grown is chemically cleaned using a conventional technique, and then placed in the front chamber of an MBE apparatus, and once evacuated to, for example, about 10-'' Torr, the substrate 1 is heated to a temperature of 10-8 to 10- Thermal etching is performed by heating to a temperature of about 750° C. for about 3 minutes in an atmosphere of about 1000 Torr.

This substrate 1 is moved into a growth chamber while maintaining a vacuum state, and the growth temperature is 680° C. and the growth rate is GaAs 1.0 μm.
/h, 81GaAs 1.4μn+/h, non-doped i-type GaAs channel rri3 has a thickness of about 1100n,
Alo, zGao, Js electron supply layer 4 is made of silicon (S+
) n-type region 4 with a doping temperature of about lXl0''c+n-3
The n-type GaAs cap layer 5 is grown to a thickness of about 10 nm.

See FIG. 1 fc): source and drain electrodes 6 and gate electrodes 7 are provided on the semiconductor substrate by conventional techniques;
A heterojunction field effect transistor device is completed.

The energy level in this example is as shown in Figure 2, and the temperature is 7.
At 7K, the areal concentration of the two-dimensional electron gas 3e is approximately 5X
10"cm-", electron mobility approximately 9 XIO' cm2
/ν, S, the thickness of the buffer layer in the conventional structure is 1.
It showed almost the same value as when it was set to about μm.

The epitaxial growth time per wafer in this example is as follows:
The growth by OCVD method took about 5 minutes, the growth by MBIE method of the i-type GaAs channel layer 3 to n-type GaAs cap layer 5 took about 10 minutes, and the thickness of the conventional structure was about 0.8 minutes.
Compared to the approximately 40 minutes required to grow the i-type GaAs buffer layer 13 to n-type GaAs cap layer 15 by the MBE method, a significant reduction in the required time and an improvement in productivity were realized.

Although the above description uses a GaAs/AlGaAs-based heterojunction field effect transistor as an example, the present invention is not limited to this, and may be applied to other semiconductor materials such as InGaA.
Similar effects can be achieved by applying the present invention to other semiconductor devices using s/AlGaAs, InP, etc., or using two-dimensional electron gas as a channel.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to manufacture heterojunction field effect transistors, etc., which use two-dimensional electron gas as a channel with good characteristics, with high productivity, and this invention has a great effect on promoting their practical application. can get.

[Brief explanation of drawings]

Fig. 1 is a schematic side sectional view of the process order of an embodiment of the present invention related to a heterojunction field effect transistor, Fig. 2 shows its energy level, and Fig. 3 shows a conventional example of a heterojunction field effect transistor. FIG. 4 is a diagram showing an example of energy levels in the conventional example. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n-type GaAs buffer layer, 3 is a non-doped i-type GaAs channel layer, 3e is a two-dimensional electron gas, 4 is an AlGaAs electron supply layer, 4a is a non-doped spacer area , 4b is an n-type region, 5 is an n-type GaAs camp layer, 6 is a source and drain electrode, and 7 is a gate electrode. (Ku) I Z Conventional example o) R type split front view 3 Mouth conventional combination! J's Kinorohi guide crisis ρJ mouth Qin 4 Ta

Claims (1)

[Claims] An n-type semiconductor buffer layer is epitaxially grown on a semi-insulating compound semiconductor substrate in advance, a vacuum heat treatment is performed to etch the surface of the buffer layer, and then two-dimensional electron gas is accumulated without exposure to the atmosphere. 1. A method of manufacturing a semiconductor device, comprising epitaxially growing a required semiconductor layer including an i-type semiconductor channel layer on the buffer layer.