JPS6235747A - Network controller ring signal self-test circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a self-test circuit for a network control unit (NCU), and particularly to a self-test circuit for a call signal of a network control unit, which is suitable for finding the cause of trouble in the field. Regarding test circuits.

[Background of the invention]

Conventionally, a self-test function of a network control unit (NCU) has not been installed mainly because of the high cost. However, as the social impact of line troubles increases and costs decrease, the need for NCU self-test functions increases. Without this NCU self-test function, it would be impossible to determine whether the problem is with the line or the NCU package, which would tend to delay response times.
This is thought to be a way to quickly determine whether the U package is normal or abnormal, or the first step in troubleshooting the line.

[Purpose of the invention]

The purpose of the present invention is to identify the function of a network control unit (NCU) that controls the interface (line) with a switch by using a simulator or switch other than the NCU. Some functions of N
An object of the present invention is to provide a self-test circuit for a calling signal of a network control unit (NCU) that can be added to a CU to easily check the function of the control unit without using any external equipment other than the NCU.

[Summary of the invention]

The present invention is necessary, in part, because the network control unit (NCU) performs its functions by transmitting and receiving signals to and from the exchange, and if the NCU has some of the functions of the exchange, self-testing is possible. In addition to importing into the functional NCU of the exchange,
Second, even during a test, unrelated signals should not be given to the exchange to make it perform switching operations, so the network is equipped with a self-test function by separating the line and NCU with a relay when performing a test. This is a self-test circuit for the control device's call signal.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 5.

FIG. 1 is a block diagram showing an embodiment of a self-test circuit for a network control unit (NCU) calling signal (CCL signal) according to the present invention. In FIG. 1, 1 is a modem circuit, 2 is a transformer, 3 is a relay, 4 is a U link, 5 is a line, 6 is an NCU circuit, 7 is a CL detection circuit that detects a CL double signal, 8
is a test switch that generates a test signal to start tect,
9 is a CL control circuit that provides control timing for this self-test circuit; 10 is a CL generation circuit that generates a CL multiplied signal (16HE call signal) necessary for the incoming call operation of the NCU; 1
1 is a CL determination circuit that determines whether the CL detection result is normal or abnormal; 12 is a display circuit that displays the CL determination result; and 13 is a relay. Note that the modem circuit 1 to CL detection circuit 7
The components up to this point constitute a built-in modem/NCU package consisting of a conventional modem section and NCU@, and the components from the test switch 8 to the display circuit 12 constitute a CL double signal self-test circuit added according to the present invention. 14 is C from line 5
↓The double signal 15 is the CL detection signal, 16 is the test signal, 1
7 is a control pulse, 18 is a CL determination enable signal, and 19 is a CL multiplied signal from the CL generation circuit 10.

First, the conventional circuit portion will be explained. Figure 2 is C of Figure 1.
3 is a detailed circuit diagram illustrating an L detection circuit 7. FIG. In FIG. 2, 20 is a capacitor, 21 is a resistor, 22 and 23 are photodiodes, 24 and 25 are phototransistors,
26 is a resistor, 27 is a resistor R1, 28 is a resistor R2, 29 is a capacitor C1, and 30 is a buffer. 61 is a CL multiplied AC signal (DC cut signal), 32 is a CL detection signal (balance input signal), and 15 is a CL detection signal (buffer output signal). FIG. 5 is a time chart when the CL detection circuit 7 of FIGS. 1 and 2 detects the CL signal 14 from the line 5.

With this configuration, when the network control device shown in FIG. 1 receives a call, it receives a CL double signal calling signal (14) from the exchange (not shown) through the line 5. This C↓ signal 14 is sent from the line 5 to the CL detection circuit 7 by evacuating the link 4 and the relay (LE 21) 1s and the relay (CML'I 5), and from this CL detection circuit 7, the CL detection signal 15 is output.Here, the details of the detection operation of the CL detection circuit 7 are explained in the second section.
This will be explained with reference to the figures and FIG. Line X of line 5 in Figure 1 has a DC voltage of 48■ with line Y as a reference,
The CL signal 14 input from this is 4 as shown in FIG.
The signal is a 16H2 DC signal superimposed on an 8V DC signal. This CL signal 14 is an alternating current CL multiplied signal (DC cut signal) 6 in which the direct current is cut off by the capacitor 20 and resistor 21 of the CL detection circuit 7 in FIG. 2 as shown in FIG.
It becomes 1. Note that this CL signal 31 continues for 1 second and then
It is an AC signal that pauses for seconds.

The photodiodes 22 and 23 in FIG. 2 are connected in parallel in opposite directions so that current flows even when the alternating current CL signal 51 of k is positive or negative.

As a result, when the AC CL signal 31 is input for 1 second, a current flows through the photodiode 22 or 23, so a current flows through the phototransistor 24 or 25, and the phototransistor 24 or 25 is turned on. , the collectors of the phototransistors 24 and 25 go from the high level of +5V of the collector power supply voltage to the low level. Therefore, the CLL output signal (buffer input signal) 32 of the input to the buffer 30 from the collector via the resistor 27, 28 and the capacitor 29 and the CLL output signal (buffer output signal) 15 of the output of the buffer 30 are as shown in FIG. becomes low level. Next, AC CLL No. 6
1 is at rest for 2 seconds, the CLL output signal (buffer input signal) 62 is lower than the low level as shown in At this time, R of the integrating circuit is adjusted so that the CLL output signal (buffer output signal) 15 does not rise to a high level and maintains a low level as shown in FIG.
1C1 time constant is set. In this manner, when the CLL signal 14 is input from the line 5, the CLL output circuit 7 outputs a CLL output signal (buffer output signal) 150-1 level signal.

Next, a self-test circuit added according to the present invention will be explained. FIG. 4 is a block diagram illustrating the CLL control circuit 9 of FIG. 1. In FIG. 4, 66 is a hexadecimal counter and 64 is a timer.

Note that the control pulses 17 and C of the output of the CLL control circuit 9
The time charts of the LL fixable signal (timer output signal) 18 are shown in the following time charts of FIG. 5 and FIG. 6, respectively. Figure 5 (A) and (B) are the CLL in Figure 1.
1A and 1B are a block diagram and a time chart thereof, respectively, illustrating a raw circuit 10. FIG. In FIGS. 5(A) and (B), 35 is a 16H2 oscillation circuit, and 66 is a low-pass filter L.
PF and 5y are transformers. 38 is an output signal of the 16 Hz oscillation circuit 35, and 59 is an output signal of the low-pass filter 66. FIG. 6 is a time chart of the C↓ determination circuit 11 shown in FIG.

With this configuration, the test switch 8 of the C'L signal (calling signal) self-test circuit added to the network control device shown in FIG.
5 (8) from the ternary counter 66 of the CLL control circuit 9 in FIG. 4 by the test signal 16 (FIG. 6).
At the same time, the timer 53 outputs a timer output signal 18 as shown in FIG.
7 is a signal that is at a high level for 1 second and at a low level for 2 seconds as shown in FIG. 5(A). Thus, when the control pulse 17 is at a high level for 1 second, the 16H2 transmission circuit 34 of the CLL generation circuit 10 of FIG.
The output signal of pulse 6 of z is output, and the control pulse 17
When is at a low level for 2 seconds, the output signal 68 of the 16H2 oscillation circuit 35 is at a low level.

This output signal 38 is passed through a low-pass filter 56 such as the one shown in FIG.
An output signal 39 is obtained. After passing through the transformer 37, this output signal 69 is applied with a DC voltage of 30V from the package, so that the output signal 69 has a DC voltage of 30V with respect to the line Y.
1 on a DC signal as shown in Figure 5(B) with V
6H2 AC signal σ) outputs CLL number 19.

Note that the CLL number 14 from the actual circuit 5 is an AC signal with a DC voltage of 48V;
CLL No. 19 from the LL raw circuit 10 is tested as an AC signal having a pancage DC voltage of 30V as follows.

On the other hand, when the above test switch 8 is turned on, the above test signal 16 (Fig. 6) causes the CLL control circuit 9 of Fig. 1 to turn on the relay (Y-11) 13 (the connection is not shown). . Therefore, the CLL number 19 output from the above C↓ generation circuit 10 passes through the relay (4J1) 13 and the relay (CML) 3 and is input to the CLL output circuit 7. This input CLL number 19 is first The CLL output signal (buffer output Signal) 15 should be output. When the test switch 8 is turned on, the test signal 16 as shown in FIG. 6 causes the CLL control circuit 90 control timer 34 in FIG. is output. This CLL determinable signal starts from 3 seconds after the test switch 8 is turned on and the test signal 16 in FIG. 6 becomes low level until the test switch 8 is turned off and the test signal 16 becomes high level. This indicates that there is a CL judgment judge by the CLL constant circuit 11 between this level and the frontage level. During this time, the CL signal 1
The CLL output signal 15 of the CLL output circuit 8 which detected 9 is the sixth
As shown in the figure, if it is low level as shown in Fig. 6, the C
The Cb determination circuit 11 can determine that the LL output circuit 7 is normal, and if it is at a high level, it is abnormal. The judgment data by this CLL constant circuit 11 is sent to the display circuit 12, and the judgment result is displayed.

In this way, according to this embodiment, the call signal CC of the exchange
By incorporating a part of the L signal generation circuit into the network control device package, the function of the CL output circuit inside the pancase can be easily checked without using external equipment, allowing for faster troubleshooting. It will be done.

〔Effect of the invention〕

As explained above, according to the present invention, a self-test circuit for the call signal of the network control device is included, and an internal test can be executed when the line is disconnected, so that it is easy to isolate the fault or defective location. This has the effect of shortening troubleshooting time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a self-test circuit for a call signal of a network control device according to the present invention, FIG. 2 is a detailed circuit diagram of the CL detection circuit shown in FIG. 1, and FIG. 4 is a block diagram of the CLL output circuit 9 in FIG. 1, and FIG. 5 (A), CB) is the C↓ generation circuit 1 in FIG. 1.
0 and its time chart. FIG. 6 is a time chart of the CLL constant circuit 11 of FIG. 1...modem circuit, 2...transformer, 3...relay, 4...
... U link, 5 ... line,
6...NCU circuit, 7...CLL output circuit, 8...test switch, 9...
...CL control, control circuit, 10...CLL raw circuit, 11...CLL constant circuit, 12...
...Display circuit, 13...Relay, 14...Call signal (CCL signal), 15...
...CLL output signal, 16...Test signal, 17...Control pulse, 1B...
...CLL fixed signal, 19...CL double signal

Claims (1)

[Claims] a paging signal generation circuit that generates a paging signal necessary during the incoming call operation of the network control device; a test switch that generates a test signal that inputs the paging signal and starts a test;
a calling signal detection circuit that detects the calling signal; a judgment circuit that judges whether the detection result is normal or abnormal; a display circuit that displays the judgment result; and the calling signal generation circuit and the judgment circuit that use the test signal. A self-test circuit for a call signal of a network control device, comprising a control circuit that provides control timing for a network control device, and capable of self-testing the call signal detection circuit by generating the call signal inside the network control device.