JPS6235974A - Controller for image forming device - Google Patents

Abstract

PURPOSE:To execute ordinary processing while waiting for individual processor by providing plural processors to make parallel processing and providing independent timer in each processor. CONSTITUTION:N (8 units) of processors are provided in a parallel processor controller 412. As the longest execution time of a CPU 20 that makes general processing is 4musec, '4' is put in a counter and bus acquisition is waited for. When acquired, a ROM 203 is accessed by address value to each processor in a dual port RAM 411 and instruction is read. As the instruction of a parallel processor is made to 2 byte fixed length, it can be fetched within a fixed time (1Xsec). Time is adjusted to make the counter '0', data are processed and time is adjusted to make to 8mus as a whole, and then (n) for designating processor is changed, and above-mentioned procedure is repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a control device for an image forming apparatus that controls the execution timing of a sequence of a plurality of process means that execute image formation.

Problems to be solved> With the development of microcomputers, the image forming load, which used to be controlled by relay sequence circuits and logic circuits combining logic ICs, has come to be realized by microcomputer program control. Ta.

Then, with the introduction of microcomputers, the parallel control of each image forming load was changed.
Virtual parallel control has been realized by time-sharing control using program control.

However, time-sharing control using a program is not suitable for control that requires high-speed response.

For this reason, the control of these parts has been handled by assigning one microcomputer to one load, or by adding dedicated hardware circuits.

These will be explained using a copying machine as an example.

FIG. 2 is a block diagram of a copying machine to which the present invention can be applied. The original is slit-illuminated by an original illuminating means 100 such as a fluorescent lamp, and an image of the original is formed on a photosensitive drum 108'' by a zoom lens 107. At this time, the original reflected light is reflected from the first mirror lot, the second mirror 102, and the third mirror 1.
03, zoom lens 107, fourth mirror 104, fifth mirror 105. The photosensitive drum 10 via the sixth mirror 106
Guided by 8.

As the photosensitive drum 108 rotates in the direction of the arrow, the document illuminating means 100 and the first mirror 101 move in the direction of the arrow. And at this speed, the second mirror 102 and the third
Mirror 103 moves in the direction of the arrow. This is light H+
This is to keep the length y of 109 constant.

After the first mirror 101 has moved by the length of the document, it is switched to backward movement and returned to its original position. Note that the leading edge position of the document and the main position of the first mirror can be detected by the image leading edge sensor 110 and the scanning home position sensor 111.

Around the photosensitive drum 108, a negative charger 112, a blank exposure illuminator 113, a developer 114, and a transfer charger 11 are installed.
5, separator 116, cleaner 117. A static eliminator 118 is provided. An electrostatic latent image formed by a potential change depending on the light intensity at the image point of the slit-exposed document is developed, and the image is transferred onto copy paper. The copy paper is ejected by the conveying means 119 via the fixing device 120.

This copy paper is placed in one cassette 121 or the lower cassette 12.
2, one sheet is picked up by the paper feed roller 123 or the paper feed roller 124, and the paper is temporarily stopped at the position of the registration roller 125.

The first mirror lot moves in the direction of the arrow, and the image tip sensor 11
0, the time at which the leading edge of the document is imaged is detected, and the leading edge of the copy paper at this time is determined by determining the time at which the image forming position of the photosensitive drum 108 rotates to the position of the transfer charger 115. The time is adjusted so as to move to the position of the transfer charger 115, and the registration roller 125 is rotated to align the image on the copy paper 1-.

Conventionally, a device control microcomputer has been used to control the operations of the copying machine described above.

For example, Intel's 8049 and 8051 fall under this category. For the sake of simplicity, a conventional control circuit for controlling the scanning of the optical system and the feeding of copy paper is extracted and shown in FIG.

In the figure, reference numeral 201 denotes a device control microcomputer, which is connected to a RAM 202 and a ROM 203 via an external bus 203. Inside the microcomputer 201, a CPU 210, a RAM 211, an input port 212
, an output coupler 213 , a programmable oscillator 214 , and the like are connected via an internal bus 215 .

The input port AO of the input boat 212 is input from the scanning home position sensor 110, via the IU buffer 220,
The signal SHP is input, and the boat AI receives the image tip sensor 1.
11 via the input buffer 221, and the boat A2 receives the signal PRE from the paper sensor 126 immediately before the registration roller 215 via the input buffer 222.
G is input.

The signal SHP changes from 0 to 1 when the document illumination means 100 is at the basic position, and the O1 signal ST changes from 0 to 1 when the document illumination means 100 reaches the position where the leading edge of the document is imaged otherwise. At the position, it becomes O. Signal PR
EG is l when there is copy paper immediately before the registration roller 125, and O otherwise.

Original illumination means lOO and first mirror 101. 2nd mirror 1
02, the third mirror 103 is driven by a DC motor M2. In order to perform stepless magnification as has been done recently, reduction and enlargement in the main scanning direction are handled by the zoom lens 107, and reduction and enlargement in the sub-scanning direction are carried out by changing the scanning speed of the document. For this speed adjustment, the DC motor M2 is controlled by the microcomputer 201 via the scanning motor controller 230. Port CO is an output terminal of programmable oscillator 214, and controls the DC motor M2 by comparing this oscillation frequency with a scanning speed target. Then, the rotation speed of the motor is detected by encoder E,
This is fed back and the scanning motor controller 230 controls the speed of the motor M2 so as to keep the DC motor M2 at a speed according to the speed lf control signal Fs. By setting the signal FW at port BO to 1, the motor is rotated in a direction in which the document illumination means 100 and the like move forward, and by setting the signal RV at port BL to 1, the motor is rotated in a direction in which the document illumination means 100 and the like move backward. The brake is applied by setting the signal BRK of B2 to 1.

A signal MM is output from the port B3 and is connected to the main motor Ml via the main motor driver 231. The main motor is the photosensitive drum 108 and paper feed roller 123
, 124, registration roller 125, and other driving parts other than the scanning system. When the signal MM is set to 1, the main motor Ml rotates at a constant speed, and when the signal MM is set to 0, it is stopped. Poe hB4. B5 is the signal PICI, P
IC2 is output and connected to clutches CL1 and CL2 via hammer drivers 240 and 241, respectively.

Clutches CLI and CL2 each correspond to paper feed rollers 123
It controls the rotation and stopping of ゜124, and the signal PI
When CI and PIC2 are each set to 1, the paper feed roller rotates, and when set to 0, it stops.

signal REG is output to hammer driver 2
It is connected to clutch CL3 via 42. The clutch CL3 controls the rotation and stopping of the registration roller 125. When the signal REG is set to 1, the registration roller 125 rotates, and when the signal REG is set to 0, the registration roller 125 is stopped.

In addition to this, the control objects of the copying machine include rotation of the developing device, application of stop 1-1 developing bias, voltage application to each charger, on/off of the static eliminator, driving of the zoom lens, display on the operating section, and manual key control. There are many others, but I have omitted them.

FIG. 4 shows an example of a program for operating the CPU 210 and controlling the copying machine with such a configuration.

In step 3301, RAM 202 and internal RAM 21
Assign the initial value of variable 1 and initialize the copying machine.

In step 5302, the display on the operation panel and the manual processing of keys are performed. Analyzes the operator's instructions and displays the instructions and the status of the copying machine.

In step 3303, the electrophotographic process such as a charger and a developer is controlled.

In step 3304, copy paper feeding control is performed.

In step 5305, scanning control of the document illumination means and the like is performed in synchronization with the feeding of copy paper.

Then, in step 5306, a stepping motor used for moving the zoom lens, etc. is driven, and then the process returns to step 5302 to repeat these processes.

In order to control the copying machine in this way, a plurality of processes are performed in a time-divided manner.

In such a case, when performing operation display processing,
When the document illumination means passes the document leading edge position, the time for detecting the document leading edge position is delayed until it is the turn of the scanning system processing, which delays the rotation start time of the registration roller 125, and the copy paper The screen position may shift forward. For this purpose, for detecting the leading edge position of the original, the input is input to the interrupt input terminal, interrupting the CPU, etc., to forcibly inform the CPU 210 of the leading edge position of the original, and from that time the registration roller 125 starts rotating. It was necessary to devise a way to calculate the .

The above example shows that a deviation of several milliseconds adversely affects the operation of the device.
Control cannot be achieved by completing each process in step 6 before proceeding to the next step. In particular, since steps 8303 to 5305 originally proceed simultaneously, simultaneous processing is required. Therefore, it is necessary to select either to operate steps 8302 to 5306 under a basic program such as a real-time monitor program, or to write steps 5303 to 5305 together in one program. In the former case, the time required to switch the processing of each step, that is, the overhead is large, and the efficiency of CPU utilization is reduced. In the latter method, the program becomes complicated, and as the amount of the program increases due to the limited performance of the device, the number of program errors increases and the program requires a large amount of time.

Even when time-sharing processing is performed using the former real-time monitor, if an attempt is made to control a stepping motor or the like by a program, noise may occur if the program is not started at regular intervals. For this reason, such programs must be executed using fixed-time interrupt processing, and even with an increase in the number of such interrupt processing, high-priority processing is
Because other processes have to wait during the time that the process is being performed, high-speed parallel processing cannot be achieved, and stepping motor and scanning motor control is now entrusted to another microcomputer, making it difficult to exchange information between microcomputers. Due to the increase in overhead caused by frequently working on programs under a real-time monitor, the proportion of CPU processing other than the original control operation increases, and the hardware becomes correspondingly large, causing an increase in costs. It has become.

Furthermore, in order to improve responsiveness, programs are becoming increasingly complex due to extensive use of interrupt processing or special program structures, which increases the time it takes to depack programs and increases the overall development time. They are being forced to pay increased costs.

The present invention eliminates the drawbacks of the conventional example described above, and provides an image forming apparatus that can guarantee high-speed response for a plurality of control objects at the same time even though it is program-controlled, and that also facilitates program creation. The purpose is to provide a control device.

<Example> FIG. 1 is a control circuit diagram of a copying machine according to an embodiment of the present invention.

In the figure, 401 is a device control microcomputer, which is configured on an l chip. Conventionally, internal path 215
Although the internal RAM 211 and I10 ports of the CPU 210 are connected to the internal bus 215, a parallel processor controller 412 is connected to the internal bus 215 via a dual-baud RAM 411. Further, an input port 212 , a port 213 and a programmable oscillator 214 are connected to the parallel processor controller 412 .

Here, the dual port RAM 411 can be read and written by the CPU 210 and can also be read and written by the parallel processor controller 412. And dual port RAM41
1 is divided by the register areas of multiple processors.
The parallel processor controller 412
Processing by a plurality of processors is executed according to the values of the register areas of these processors.

Now, from the point of view of the CPU 210, the RAM 211 is from address 008 to address 7FH (in decimal, it is address 127, but the address will be shown in hexadecimal from now on), dual port) RAM
411 is 80) (addressed to 128 bytes from address to FF address.

Here, 8 bytes from address 808 to address 87H are defined as a register for processor O, and 8 bytes from address 88)(address 8FH are defined as a register for processor I. Similarly, from address B8H to BFHF2O
Up to 3 bytes and 8 bytes each are defined as registers for processors 2 to 7, respectively.

Of the 8-byte area allocated for each processor, the last 2 bytes are used as a program counter. For example, in the case of processor 1, address 8EH is the -L 8 bits of the program counter, and address 8FH is the lower 8 bits of the program counter. Then, the parallel processor controller 412 fetches 2 bytes of 16-bit data for each processor from processor O to processor 7 as instruction data, and the program counter increments by 2. By doing this, the lowest bit of the program counter, i.e. processor 0
Bits HO to H7 in each of the processors 7 are defined as halt instruction bits, and when these bits are 1, instructions of the corresponding processors are not fetched and executed.

Also, from COH address of dual port RAM411 to FF
The area up to address H is defined as a memory area commonly used by processors O to 7.

By defining the memory as described above and having the parallel processor controller 412 execute the processing of the sequential processors in a time-sharing manner, the CPU 2. A plurality of independent processors operate in parallel under the I/O.

Hereinafter, an example will be described in which the CPU 210 is modeled on Intel 8051 and the control microcomputer 401 is configured.

The CPU 210 is an 8-bit machine, and the instructions have a variable length of 1 to 3 bytes. and 1
In the case of the basic tarokku of 2MH2, 1 psec is the unit of execution, and the total instruction time is 17
It takes an integral multiple of zsec. Furthermore, instruction fetching is performed twice in 1 μSec by dividing 1 psec into two, and reading and writing of the RAM area is performed once every lpsee. At this time, for example, when fetching a 1-byte length instruction, the instruction is fetched and executed in the first half of 1iLsee, and the next instruction is fetched in the second half of Igsec.
The instruction data fetched in the second half is discarded, and the instruction is fetched and executed again in the first half of the next lμsec. That is, no matter how long the instruction is or how long the execution time is, the external bus access is executed in an integral multiple of 1 gsec. For example, a program as shown in FIG. 5 is executed as shown in FIG.

Step 3601 moves the contents of register 2 to the A register, step 602 adds 5 to the contents of the A register, step 5603 increments the contents of the data pointer register, and step 5604 addresses the contents of the data pointer register. Write the contents of the A register to RAM. The machine language at this time is 1 byte, which consists of 2 digits, 16
EAH, 24H when expressed in base numbers.

Q5H, A3H, and FOH are 5 bytes in total.

The execution time of steps 5601 and 5602 is Igsec, and the execution time of steps 5603 and 5604 is 2 ksec. The state of bus access at this time is as shown in FIG. In the first half of period α0, instruction EAH in step 5601 is fetched, and in the second half, instruction 24H in step 5602 is fetched. This 24
H is ignored, fetched again in the first half of the next period α1, 05H is fetched in the second half, and execution is also performed in period α1.

Instruction A3H in step 5603 is fetched in the first half of period α2, but since it requires 2JLSeC to execute, instruction FOH in step 5604 is fetched three times in total during the second half of period α2 and period α3, but all are ignored. . In the first half of period α4, FOH is fetched again, and in the second half, the next instruction is fetched. Since step 5604 writes RAM data, no instruction fetch is performed during period α5, and an external bus is used to write RAM data.

Note that the periods α0 to α5 are all If, 1 μsec when a 12 MHz clock is used.

All instruction sets in the Narayu 1j processor controller 412 have a fixed length of 2 bytes. Then, the execution unit time of the CPU 210 (i p, s e
c) allows one instruction to be fetched.

In this way, the CPU 210 and the parallel processor controller 412 are configured to use the ROM 202 connected to the external bus 204 via the external bus interface 413 in a time-sharing manner.

Among the instructions of the CPU 210, the instruction with the longest execution time is 4pLSeC.

Therefore, when the CPU 210 fetches the instructions carrying -, , -, the external bus 204 is exclusively occupied by the CPU 210 for 4 μSeC. Therefore,
Even if the parallel processor controller 412 requests an instruction fetch during this period, the execution will be delayed for 4 pLsec. Figure 7 shows this situation.

11) Parallel processor controller 412 on Mt811
When attempting to fetch instructions,
Assuming that the CPU 210 starts executing an instruction that requires 4 gsec, the period α801. α802
．． α803. In the α804, the CPU 210 exclusively uses the external bus interface 413. And between 1t/I α
At 812, a request for parallel processor controller 412 is accepted to seize external bus interface 413 and fetch two bytes of instructions for one of the parallel processors. During the next period α805, the CPU 210 exclusively uses the external bus interface 413. Assuming that it takes a maximum of 3g5ec to execute an instruction by the parallel processor controller 412, in the worst case, the parallel processor controller issues an instruction fetch request at time t811, and then the execution period α813
゜α814. It takes 8p, sec to finish α815. Therefore, by configuring the parallel processor controller 412 to always issue an instruction fetch request every 8) bsec, the external bus 204 is used for the parallel processor only once every 8 μSec, and the remaining 7
The CPU 210 starts using g5ec.

FIG. 8 shows a flowchart of this operation of the parallel processor controller 412. At the start of execution, step S
At step 801, the processor number n is set to O in order to perform time-sharing parallel processing on processors O to 7 of the parallel processors 412. In step 5802, in order to calculate the time frame for fetching instructions, bus unused 1t/
Initialize the number m remaining for one period to 4. In step 5803, a request is made to the external bus interface 413 to use the bus, and in step 5804 there is a 1 psec wait. In step S805, the remaining number of bus non-use periods m is set to 1.
Decrement by one. In step 3806, it is determined whether the bus use period has come, and if the CPU 210 is using the bus, the process returns to step 5803 and repeats.When the bus is allocated to the parallel processor controller 412,
Proceed to step 3807. In step 5807, the high-order byte of the instruction is fetched from the external memory using the value obtained by setting the least significant bit of the value of the program counter of processor n to 0 as an address. For example, when n is O, two bytes at addresses 86H and 87H of the dual port RAM 411 are used as the value of the program counter. When n is l, addresses 8EH and 8FH are used. That is, for the nth processor PROCn, (80
The address H+8Xn+6) is used as the high-order byte of the program counter, and the address (8'OH+8Xn, +7) is used as the low-order byte of the program counter.

Then, in order to fetch the first byte of the instruction, the lowest bit I is set to O and a 1-byte fetch is performed. Step 5808 fetches the 2 # I'l bytes of the instruction with the least significant bit (.) set to 1. Thus, steps 5807, 880
At step 8, during Igsec, the external bus 204 is used to fetch two bytes of instruction data for processor n. In step 5809, check the remaining number of pass non-use periods m and step 581 until 1m becomes O.
Repeat 0,5811. Step 810 is 1 g, s
Then, in step 5811, m is decremented by 1. By doing this, step 581
It takes exactly 5 μsec for iE to reach 2, and moreover, during this 5JLSeC, the CPU 210 can monopolize the path by Igsec to take advantage of the gap in the bus usage, and can perform instruction fetch for parallel processor processing. In step 5812, according to the fetched instruction data, the dual port RAM 411
Performs calculations between memories and input/output ports.

Note that if the least significant bit of the program counter of processor n is 1, the fetched instruction is ignored and no execution is performed; if it is 0, the value of the program counter is set before execution. Increment by two to prepare for the next instruction fetch. In step 5813, step 5812
Wait for an amount of time depending on the time required, Step 5
812,5813,5814゜S815, S816
Adjust so that it costs 37 isec. Step 5814
Next time, in order to advance the processing target processor by one, the processor number n is incremented by one. In step 5815, it is determined whether the processor number n has exceeded the maximum processor number. If it has exceeded the maximum processor number, the processor number n is returned to O, and the process returns to step 5802 to repeat the above processing.

By the operation described in 1-1 above, the parallel processor controller 412 causes the processor O to execute time-sharing with the eight processors of the processor 7, with an apparent speed of 1.64 μSec.
It becomes possible to control eight processors that execute l instructions.

Here, in step 5812, each processor 0 to
Instruction 7 will be explained. The length of the instruction is a fixed length of 16 bits. Instructions can be classified into the following four types. Byte operations that perform operations between the 8' registers allocated for each processor and 7-bit memory space; Immediate 1-byte operations that perform operations between registers and 7-bit data; There are four operations: a bit operation that performs an operation with an arbitrary bit in a 7-bit memory space, and a jump operation that sets a 10-bit relative address branch depending on conditions.

Next, dual port RAM411 and I10 baud)2
The address space of 12,213 will be explained.

The dual port RAM 411 can be accessed by both the CPU 210 and the parallel processor controller 412. Here, the address seen from each processor is called a local address, and the address seen from the parallel processor controller 412 is called a global address.

The local address OOH08 address 07H is the dual port RAM 411 assigned to each processor.
It corresponds to the memory space for registers. The local addresses 08H to 47H correspond to the remaining area of the dual port RAM 411, that is, the global addresses COH to FFH.

And address 7F from address 48 of local address is I1
0 port is supported.

In this way, register space, memory space, memory space, I
10 port spaces can be mapped into the same address space.

An example of controlling electrical equipment using a processor with the following architecture will be described below.

FIG. 9 shows a timing chart regarding the paper feed system of the copying machine shown in FIG. This example shows the control timing for making two copies. Lower cassette 122
When feeding paper from 1 to 2, at time tllol, port B5 is set to "I II" and clutch CL2 is turned on to rotate paper feed roller 124 and pick up the copying machine. Then, at time tl102, paper sensor 126 detects the paper After the detection and time α1101, the port B5 is set to "O" and the paper feed roller 124 is stopped. This time αl 101
During this time, the copy paper reaches the registration roller 125 and waits for the registration roller 125 to start rotating. On the other hand, document scanning is started by detecting paper at time tl102. That is, the optical system moves forward. Then, the image tip sensor 11
0, at time tl103, the leading edge of the document is placed on the photosensitive drum 1.
08, and from the time from tl103 until the image formation position reaches the transfer position, the registration roller 1
After the time α1102, which is calculated by subtracting the time required for the copy paper to reach the transfer position after rotating the port B6, the port B6 is
', the clutch CL3 is turned on, and the registration rollers 125 start rotating.

When copying multiple sheets as in this example, moving the document scanning optical system forward by the length of the document, then retracting it and returning to the home position before starting paper feeding will lengthen the time it takes to make the next copy. Put it away. To prevent this, time t
At 1104, feeding of the next sheet is started. This timing is the time tl105 when the registration roller 125 is turned on.
This time α1103 is equal to the time α1103 from the copying time α1104 per sheet.
102, the time α1106 from the start of driving the paper feed roller until the paper sensor is turned on again, and the time required from the home position to the image tip sensor α1105. The time α1104 is determined by the copy paper size.

This minimum value becomes the round trip time for document scanning. Also time α
1105 is determined according to the magnification ratio.

- For document scanning, signals FS, ports BO, and Bl are sent from port CO at a frequency corresponding to the scanning speed.

The scan motor controller 230 is controlled by sending a forward signal FW, a reverse signal R2, and a brake signal BRK from B2 to the scanning motor controller 230, respectively. A timing chart for this control is shown in FIG.

When advancing, the advancing speed is determined by the copying magnification at that time, so the programmable oscillator 214 is set to oscillate at a frequency corresponding to this, and then
The reverse signal RV and brake signal BRK are set to 0°, the forward signal FW is set to 1°, and forward movement is started. This is time t 1201. Then, at time t 1202 after a time α 1201 for advancing by the length of the original, the advance signal is sent to “
O'' to set the backward speed using the programmable oscillator 21.
4 and set the backward signal to 1''. Then, when the image tip sensor 110 senses the image edge signal, that is, at time t1203, the backward signal is set to ``O''' and the backward signal is set to ``1'' for 1 hour.
The brake signal BRK is set to l°'' only during 202.

Thereafter, the original scan is reversed due to inertia, and the home position sensor 111 outputs a brake signal BRK of 1 at time t1204 when the home position is returned.
Make it. Then, in order to make a second copy, the brake signal BRK is set to O', the forward speed is set, and the forward signal FW is set to I and the following control is repeated. The second half of FIG. 10 shows an example in which the scanning system stops and does not reach the home position after setting the brake signal BRK after sensing the position of the backward image tip sensor 110. In other words, if the home position is not reached within time α1203 after returning the brake signal BRK to "0"', set a slow speed, set the reverse signal RV to 1°, and slowly reverse until the home position is detected. When the home position is detected, the reverse signal R is activated.
V to "0" and brake signal BRK to "1".

Then, after the maximum time α1204, the brake signal BRK
Set to 0゛'.

As described above, even just extracting the control of the document scanning optical system and paper feeding system is quite complicated.

In the present invention, the following control is performed using the paper feed roller,
One processor PROCO in the parallel processor controller 412 is assigned to control the paper feed system such as registration rollers, and another processor PROC1 in the controller 412 is assigned to control the document scanning optical system such as the forward signal FW. The copying machine is controlled by setting data to the processor and monitoring the operation of the processor.

FIG. 11 shows a flowchart of an example of a paper feeding system control program executed by processor PROCO. When execution starts, it is checked in step 51301 whether there is a remaining copy number N, and the process continues in step 3 until the remaining copy number N becomes 1 or more.
Repeat 1301.

FIG. 12 shows an example of a memory map of the memory area of the dual port RAM 411.

Here, for the remaining number of copies N, the CPU 210 sets the value N at address C18 of the global address. This means that when the operator specifies the start of copying using the copy start button or the like, the CPU 210 writes the number of copies defined at that time to address C18. In step 51302, the remaining number of copies is decremented by one. In step 51303, the flag Uf, that is, the θth bit of the Co address of the global address, is checked and it is determined that it is 1.
When , it is determined that the upper cassette is selected, and when it is O, it is determined that the lower cassette is selected, and the rotation of the paper feed roller 123 or the paper feed roller 124 is started correspondingly. For example, when the flag Uf is 1, the upper paper feed roller 123 is rotated by setting the flag Uf to 1. This can be accomplished by setting the fourth bit at address 49H in the I10 port area shown in FIG. This can be done using instructions for bit operations.

In step 51304, the paper sensor check is continued until the paper sensor 126 is turned off, and when the paper sensor 126 is turned off, it is repeated in step 51305 until the paper sensor 126 is turned on. This is done in consideration of the case where the trailing edge of the paper being copied before the paper currently being fed is on the paper sensor 126.

In step 31306, a scanning flag Sf is set to instruct the document scanning optical system to start moving forward. Flag S
f is assigned to the first bit of the COH address of the global address.

In 31307, the wait is performed by a constant interval βl. This is because, as mentioned above, the instruction execution time is constant even in parallel processors, so the register is used as a count and it is counted up or down.
Program it to proceed to the next step when it reaches a certain value,
The wait time can be adjusted by the initial value of the register used as the counter. This time βl corresponds to α1101 in FIG. 9. Then, in step 5130B, the paper feed roller is turned off. In this case, you can check the flag Uf and set the corresponding boat B4 or port B5 to O°, or set the corresponding port B4. Both sides of B5 °
It may be set to ``0°''.

In step 31309, wait until the image tip sensor 110 is turned on, then in step 51310, wait for a time β2 minutes, and in step 51311, wait until the image tip sensor 110 turns on.
start rotating. Time β2 is time α in FIG.
Corresponds to 1102. Then, in step 51312, the process waits for a time β3 and then checks whether to perform the next sheet feeding. Time β3 corresponds to time α1103 in FIG. In step 51313, the remaining number of copies N is checked, and if it is still necessary to make copies, the process proceeds to step 51314, and if the necessary paper feeding has been completed,
That is, when the remaining number of copies is 0, the process advances to step 51318. In step 1314, the remaining number of copies N is decremented by one to prepare for the next paper feed, and in step 1315, the same process as step 1303 is performed to start paper feeding. In step 1316, the process waits for a time β4, and in step 1317, the rotation of the registration roller 125 is stopped.

This time β4 is the time obtained by subtracting β3 from the time obtained by dividing the size of the fed paper in the traveling direction by the circumferential speed of the photosensitive drum 10g, plus some extra time.

Then, proceed to steps 51314 to 51317, and if continuous copy processing is to be performed, return to step 51304.
- Repeat the process. When the feeding of the last paper is completed, the process branches from step 51313 to step 51318, passes through step 1319, and returns to the beginning to step 5130.
Repeat the process from 1 to -]-. Note that step S1
318.51319 are respectively steps 51316.3
This is the same process as 1317. The times βl, β2. β3. Of β4, time βl and β2 have a fixed length, and time β3. β4. varies depending on the magnification ratio and copy paper size. Therefore, the time β3. Regarding β4, before the CPU 210 sets the remaining number of copies to global address C5H, β3. Set β4.

Next, the processing of the document scanning optical system will be explained.

FIG. 14 shows a flowchart of an example of a control program for the document scanning optical system executed by the processor PROC1.

When execution starts, in step 51501, the scan flag S
Wait until f turns on, and when it turns on, step S1
Proceed to step 502. This is set when the copy paper is moved to the position of the paper sensor 126 in front of the registration roller 125 by the paper feed system control program. That is, the optical scanning system is activated when preparations for starting copying are completed. In step S 1 502, the scanning flag Sf is cleared to indicate that the document scanning request has been accepted. In step 51503, all scanning system signals are cleared.

That is, in order to clear all of the forward signal FW, reverse signal RV, and brake signal BRK, the boats BO, Bl, and B
Set 2 to 0°.

In step 51504, in order to scan the document at a speed corresponding to the magnification ratio, the programmable oscillator 21 is activated so that a signal with a frequency corresponding to this speed is output from the boat CO.
Perform the settings in step 4. Specifically, the frequency setting boat CO of the programmable oscillator is 4AH in the I10 boat area.
The value f1 is assigned to address C18 of the global address by the CPU 21O.
This is done by writing . Step 5150
5, by setting the boat BO to ``1'', a command to start forward movement is issued to the scanning motor controller 230. Then, in step 51506, wait until the image tip sensor 110 is turned on, and then in step 51507, wait the scanning time τl for the length of the document, and step 3150
Turn off the forward signal at 8. This time τl is the CPU 210
has been written in advance to the global address C6H. In step 1509, a value is set at address 4AH in the I10 port area so that the frequency f2 corresponds to the speed when moving backward, and in step 51510, the reverse signal RV is turned on to start backward. Then, in step 51511, monitor the image tip sensor 110 to turn on,
When turned on, brake control is started to prevent the scanning optical system from overrunning and colliding. Step 51512
At step 51513, the reverse signal RV is turned off, and at step 51513, the brake signal BRK is turned on to apply the brakes. Then, in step 51514, wait for time τ2, and in step 51
At 515, the brake signal BRK is turned off, and the scanning system is then moved backward by inertia. Here, the predetermined number of times νl is assigned to the register ν in step 51516, and steps 5L, 517, 3151B, and 51519 are repeated this number of times. This register ν is
Either the dedicated memory area of C1 or local addresses OIH to 05H may be used. In this way, in step 51518, the register ν is decremented one by one, and in step 51519, it is determined that the value of the register ν becomes 0, and the process returns from step 51519 to step 51517 until then. In step 51517, the home position sensor 111 is monitored, and if it is turned on,
Even if register ν is not 0, step S153
Go to 0. Then, in step S1530, the brake is applied, and after a time τ3, the brake signal is turned off in step 1532, and the process returns to step S51501. If the register ν does not return to the home position even if it becomes 0, the process advances to step 51520.

In step 31520, the programmable oscillator 214 is set so that the frequency f3 is output in order to retreat at a low speed.
is set, and the reverse signal RV is turned on in step 51521. In step 51522, the scanning system waits until it reaches the home position, and in step S1523, the backward signal RV
Turn off. Then, in step 51524, the brake signal BRK is turned on, and in step 51525, the register ν
is initialized with a fixed number of times ν2, and steps 31527, 51
At 527, register ν is decremented and step 51526 is repeated until register ν becomes 0. Step 31526 checks whether the scan flag Sf is turned on, and if it is turned on, the process exits from this loop and proceeds to step 51529. Step 5
At step 1529, the brake signal BRK is turned off and the process proceeds to step 51.
Return to step 501 and repeat the second control. Step 51
The processing from step 524 to step 51529 has a maximum of ν2
This is an example of an algorithm that applies the brakes for a time determined by , and if a command to start scanning is received again within that time, it immediately starts scanning.

As shown in Figure 2, the paper feeding system and original scanning system programs are created independently, and the CPU 210 program runs the time β3.
β4. τl, the frequency set value f1, and the paper feed light, that is, a flag Uf indicating the selection of the 1-lower stage of the cassette is set, and the number of copies per copy is set to the remaining number of copies N. Note that if the starting addresses of the programs for the paper feeding system and the document scanning optical system are set in the respective program counters of one of the parallel processors, these programs are processed in parallel. Therefore, controls that require responsiveness, such as the timing to start rotating the registration rollers after the image tip sensor is turned on, can be performed without delay, and the burden on the CPU 210 is significantly reduced.

Other Embodiments FIG. 15 shows a flowchart of another embodiment of the present invention. In this chart, chart step 5804 in FIG.
, 5810 instead of varnish 7'/bu 52001.520
I'm using 02. Steps 52001, 52002 (
7) Execution of process m means that the RO
This is a fixed-format process that can be executed without accessing the M203 or RAM 202. Then step 52001.
5805 and Step'/P52002.

5811, processing 4. Execute process 3, process 2, and process 1. That is, when fetching instructions for processor n in this way, the external bus interface 413
Adjust the timing of using the external bus 20 and wait for the actual instruction fetch.
It becomes possible to execute processing that does not use 4 and increase processing capacity.

For example, as shown in FIG. 16, the counter control flag CRn is assigned to the second bit of the local address OOH, and the local address 03HII#! ! Assign as a counter.

Then, one of the processes m is executed by the parallel processor controller as a process according to the flowchart shown in FIG.

In step 52201, the second bit of the OOH address of the local address of processor n is checked. That is, look at the second bit of address (80H x 8 This is a process to ensure that it takes time, for example, so that it always takes 1 μsec from start to finish.The same applies to steps 32206 and 52207.
For example, 17tsee in total no matter which branch is performed.
This is to ensure that it always takes effect. tip 52
202 decrements the counter by one. For processor n, this counter is the global address (8
The RAM is located at address 0H+8Xn+3). In step 52204, when the decremented result becomes 0, the process proceeds to step 52205; otherwise, the process proceeds to step 52207. and step 5220
5, when the counter is decremented to -0 in order to clear the above-mentioned CRn, the decrement operation ends and the countdown stops.

When the above control is performed, program a of each processor assigns the timer initial value to the local address 03H, and then sets bit CRn to "1°". A timer function can be realized by simply monitoring the value becoming “0”.

If there are 8 processors and each instruction is executed for a fixed time of 8 psec, then 64g5
A timer function element is implemented for each EC.

For example, the document scanning program described above can be changed as shown in FIG.

That is, instead of steps 51516 and 51525 in FIG. 14, steps 52301, 52302 and 52303 are executed, respectively.

52304 is used. In step 52301, the number of times v1
is set as the initial value of the counter, and step 52302
Set bit CR for counter run command at 64.
A countdown starts every μsec. Similarly, in step 32302, the number v2 is set as the initial value of the counter, and in step 52304, bit CR is set. Then, in steps 52305 and 52306, it is determined whether or not CR is O (beep), and if it is not O, the process returns to the next step in which bit CR was set, and bit CR is set to 0.
Repeat the process until.

By doing so, the counter decrement in steps 51518 and 51528 of the conventional program is no longer necessary. Moreover, step 52302 and step 5
Even if a step is added during 2305, there is no need to change the value of the number of times V1. In the previous example, 1 Step 51
The maximum time is the time required to repeat 517, 51518, and 51519 multiplied by the number of repetitions v1, so in order to add a step during this time and make the maximum time the same, it is necessary to change the value of the number of times v1. Met. In contrast, in this embodiment, the counter is decremented at regular intervals regardless of the step.

Such consideration becomes unnecessary, and program modification becomes easy.

Still other embodiments will be described. FIG. 19 shows an example of an external clock input circuit 2401 which is additionally built into the microcomputer 401.

Three falling edge detection circuits 2402 connect terminals CLK 1 and CLK to be added to the microcomputer 401.
2. Input external clocks from CLK3.

The falling edge detection circuit 2402 detects the initialization signal CL.
After KCLR becomes 1 and is cleared, when a falling edge of the external clock is detected, it outputs III, and remains at "°O" while there is no falling edge.

This output is then connected to the input of flip-flop 2403. The flip-flop 24o3 receives the initialization signal CL.
When KCLR becomes 1, the output value of the falling edge detection circuit 2402 at that point is input, and the next initialization signal CLK is input.
Hold until CLR becomes 1. Data selector 240
4 is A depending on the values of selection signals cso and csi.

Select one of the inputs B, C, and D, and output the signal CC0ND.
Output as . For example, when the signals cst and cso are 00, A is selected, the signal CC0ND becomes l, and the signal C
When 5I and C3O are Ol, when B is selected and the external clock signal CLKI falls, the signal CC0N
D becomes l, and if there is none, it becomes 0.

The falling edge detection circuit 2402 and flip-flop 2403 can be realized by a circuit as shown in FIG. 20, for example. This method is an example of a synchronous method, in which data is sampled using the basic clock of a microcomputer, and falling edges of the sampled data are detected in time series. The external clock signal is input to the serial input terminal SI of the 4-bit parallel output shift register 2501. Shift register 2501 is system clock 5
Data is sequentially shifted by YSCLK. 4-person power A
ND gate 2502 directly inputs the shifted older two bits of shift register 2501, and the other two inputs are connected to the shifted newer two bits via inverter 2503.

Therefore, consecutive 4 of the system clock 5YSCLK
When the external clock becomes 1°1.0.0 at a timing of 1, the 4-man power AND gate 2502 becomes 1. In this way, under the condition that two same levels occur in succession, falling edges can be stably detected while chattering is prevented. And JK flip flop 250
Since the output of the 4-man AND gate 2502 is connected to the J terminal of 4, and the clock is connected to the system clock 5YSCLK, the edge detection signal is latched at the next timing, and the output of the JK flip-flop 2504 becomes 1. This signal becomes an input to a flip-flop 2403, which is an AND gate (AND gate) 250 with gate G as one input.
5 and is connected to an inverter 2506.

Another AND gate 2507 is an inverter 2506
The output of the JK flip-flop 2508 and the gate G are input, and the output is connected to the terminal of the JK flip-flop 2508. Also, AND
The output of gate 2505 is connected to the J terminal of JK flip 2508. Furthermore, JK flip-flop 2508
The clock terminal of is connected to the system clock 5YSCLK. A clear terminal CL of the falling edge detection circuit 2402 is connected to a terminal of the JK flip-flop 2504. Here, the clear terminal CL and the gate G are connected externally, and an initialization signal CLKCLR is applied thereto. The application timing of the initialization signal CLKCLR is synchronized with one cycle of the system clock each time. By setting the initialization signal CLKCLR to 1, when the output of the 4-person AND circuit 25o2 is 0, the JK flip-flop 2504 is cleared, and when it is 1, the output of the JK flip-flop 2504 immediately before that point is 1. It is cleared when , and set to l when it is 0. Therefore, it is possible to prevent edge detection from being omitted due to the application timing of the initialization signal CLKCLR. Also, AND gates 2505 and 2507 L with gate G as input: Therefore, the JK flip-flop 2508 is synchronized with the initialization signal CLKCLR to hold the edge detection state immediately before, and then the initialization signal CLKCLR is set to 1. Data can be retained until

In a microcomputer equipped with a falling edge detection means as described above, the selection signals cso, cs
The parallel processor controller 412 controls t and checks the detection signal CC0ND. A flowchart in this case is shown in FIG. That is,
Step 52601 is added after step 5816, and each time the processor number n goes around, the initialization signal CL
The KCLR is synchronized with the system clock and set to ■ to clear the edge detection O and latch the immediately previous edge detection result. By doing this, during each process from processor O to processor 7 until the next step 52601 is executed, the falling edge of the external clock is detected during the period in which the immediately preceding process from processor O to processor 7 is being performed. Select result signal cso, cs
By controlling t, inputting the signal CC0ND,
Can be inspected.

Then, as shown in Fig. 22, external clock selection flags C8On and C51n are assigned to the 3rd and 4th bits of the OOH address in the local area for each processor n, respectively, and the counter decrement process is performed as shown in Fig. 23. change. That is, in step 52201, when CR is 1, the process proceeds to step 52801, and the external clock selection flag C
The values of S 1 n and C3On are respectively selected by the selection signal CSI.
, as CSO, the edge detection signal CC0ND is sent to the data selector 2404 and read in step 52802. If this value is 1, the process proceeds to step 52202 to perform countdown processing; otherwise, time is adjusted in step 32803.

Then, in each processor program, the counter can be used not only as a count timing timer but also as an external clock counter.

For example, in the above-mentioned embodiment, the original scanning system and the paper feeding conveyance system are each operated by the motor M2. Although it is driven by motor Ml,
On the program, the length of document scanning and the moving distance of copy paper are controlled by motor M2. Assuming that the rotational speed of the motor M1 is kept constant, processing is performed that is delayed in terms of operation time. In contrast, in this embodiment, as shown in FIG. 24, clock disks 2901 and 2902 are connected to the shafts driven by the motors Ml and M2, respectively, and a photointerrupter 2903 is connected.

2904 is installed so that the rotation of the slits in the clock disks 2901 and 2902 outputs a rectangular wave according to the rotation speed, and the output is sent to the microprocessor incorporating the external clock input circuit 2401 of this embodiment. Connect to the external clock terminals CLKI and CLK2 of the 2900. After doing this, for example, in a document scanning system control program, time adjustment regarding the scanning length and counter countdown are performed using the external clock CLK2, and in a paper feeding system control program, time adjustment regarding the moving length of copy paper is performed. can be performed using a counter that counts down in response to the external clock CLKI, and program control that is not affected by rotational fluctuations of the motors M1 and M2 is possible.As explained above, according to this embodiment, the CPU and dual By connecting parallel processor controllers via RAM and providing each parallel processor with an independent timer mechanism,
It is now possible to easily cause individual processors of parallel processors to execute general processing even while waiting for time.

Furthermore, by providing a signal selection means for the count timing of the timer mechanism provided in each of the parallel processors, a pulse signal of a frequency corresponding to the equipment operation such as the number of rotations of the motor can be selected by the signal selection means for the count timing. By switching and operating the timer, a program corresponding to this timing can be prepared and executed as a program for each individual processor in the parallel processor. As a result, the program can be modified even when the speed of equipment operation changes. It will be possible to make it unnecessary.

This eliminates the need for technical programming for high-speed response, making program development easier and significantly reducing development costs.

In this embodiment, an electrophotographic copying machine is used as an example of the image forming apparatus, but the present invention can of course also be applied to facsimile machines, printers, etc.

(Effects) According to the present invention, by providing a timer function to a plurality of arithmetic control units (parallel processor controllers) operating in parallel, other processing can be executed while the timer is operating, and the timer The measured time can be kept constant.

[Brief explanation of drawings]

Fig. 1 is a control circuit diagram of a copying machine according to the present embodiment, Fig. 2 is a sectional view of a copying machine to which the present invention can be applied, Fig. 3 is a control circuit diagram of a conventional copying machine, and Fig. 4 is a control circuit diagram of a conventional copying machine. FIG. 5 is a diagram showing an example of a control program for the copying machine. FIG. 6 is a diagram showing the execution timing of the program in FIG. 5. FIG. 7 is a diagram showing an example of the control program for the copying machine. 8 is a flowchart of the basic operation of the parallel processor controller 412, FIG. 9 is a diagram showing the timing related to paper feeding, etc. of the copying machine of FIG. 2, and FIG. Figure 11 is a diagram showing the timing related to the original scanning system, Figure 11 is a diagram showing a flowchart of paper feeding, etc., Figure 12 is a diagram showing the timing of the document scanning system, and Figure 12 is a diagram showing the timing of the document scanning system.
13 is a diagram showing the area of the I10 boat, FIG. 14 is a diagram showing a flowchart of the document scanning system, FIG. 15 is a diagram showing a flowchart of another embodiment of the present invention, and FIG. Figure 16 is a diagram showing memory addresses,
FIG. 17 is a diagram showing a detailed processing program of process m in FIG. 15, FIG. 18 is a diagram showing a flowchart of another example of the document scanning system, and FIG. 19 is a circuit diagram of an external clock input circuit.
FIG. 20 is a falling edge detection circuit diagram, FIG. 21 is a diagram showing a flowchart of another embodiment of the present invention, FIG. 22 is a diagram showing memory addresses of the embodiment of FIG. 21, and FIG. A diagram showing a detailed processing program for process m in FIG. 21, and FIG. 24 is a control block diagram of the copying apparatus. No.? Figure 3

Claims (1)

[Scope of Claims] A control device for controlling the execution timing of a sequence of a plurality of process means for performing image formation, comprising: a central processing section; and a control device that is controllable from the central processing section and controls the plurality of processing means. 1. A control device for an image forming apparatus, comprising: a plurality of arithmetic and control units that operate in parallel; and a timer function that measures time for determining control timing in the arithmetic and control units.