JPS6236366Y2 - - Google Patents

Description

[Detailed description of the invention] This invention relates to a receiver mute circuit configured to operate in the order of predetermined reception priorities when receiving multiple radio waves using multiple radio receivers or transceivers. It is something.

Many of the current receivers (the same applies to the receiving section of the transmitter/receiver, but the description is omitted below) have sufficiently good display accuracy and stability of the received frequency, and the radio waves emitted irregularly. A standby receiver can be easily installed. However, when two or more receivers are operated by one person or by fewer people than the number of receivers, confusion may occur due to simultaneous operation of the plurality of receivers.

This device is configured so that only one receiver operates at the same time in order of reception priority by incorporating a simple control circuit into the receiver. Figure 1 shows the receiver installation. Each receiver is equipped with a terminal A that inputs a control level from a receiver with a higher reception priority, and a terminal B that outputs a control level to a receiver with a lower reception priority. Connect output terminal B 1 of the receiver with reception priority ₁ and input terminal A ₂ of the receiver with reception priority 2, and connect output terminal B 2 of the receiver with reception priority ₂ and reception priority n in the same way.
Connect it to the input terminal An of the receiver.
The receivers with higher reception priority are connected to the receivers with lower priority in order, and during standby reception, the input terminal is at H level and the output terminal is at L level, and all receivers with lower reception priority are muted. Operate.

FIG. 2 is an example of an implementation circuit of the present invention, and 1 is
AF amplifier, 2 is a speaker, 3 and 4 are coupling capacitors, 6 is the output of the detection or pre-stage amplifier, and 5 is a resistance including the internal resistance of the pre-stage. 7 is the first control transistor (PNP type), the emitter is connected to Vcc, the collector is connected to the AF circuit through resistor 8, resistors 9 and 10 are connected in series between the emitter and input terminal A, and the resistor is connected to the junction of the resistors. Connect the points to the base. If the circuit of terminal A is open (even if it is connected to another receiver), no current will flow through resistors 9 and 10, so the emitter and base of transistor 7 are at the same potential, and the collector and Since there is a cut-off between the emitters, it does not affect the AF circuit. Also, when the circuit at terminal A goes to L level, a voltage drop occurs across the resistor 10, which is applied to the base of the transistor as a forward bias, so conduction occurs between the collector and emitter, and the Vcc circuit is connected to the bypass capacitor 11 in an AF manner. Since is at ground potential, the AF signal applied to the AF amplifier 1 is divided between the resistor 5 and the conductive internal resistance of the transistor, and if this ratio is large enough, the audio output is completely muted, and the resistor 8 in series with the collector It is also possible to reduce the volume to an appropriate low level by adjusting the volume.

The second control transistor (NPN type) 12 has its collector connected to the output terminal B circuit, its emitter connected to the ground, and its base passed through a resistor 13 and a time constant holding circuit consisting of a capacitor 14 and a diode 15.
A threshold adjuster 16 sets the operating level. The threshold voltage 17 can be introduced from an output meter circuit, squelch circuit, AGC circuit, etc. that are related to the intensity of the received wave. transistor 12
When a forward bias is applied to the base of , and conduction occurs between the collector and emitter, terminal B goes to L level, and the input terminal circuit of the receiver with lower priority than itself goes to L level, thereby muting the operation. The time constant holding circuit in the base circuit is used to stabilize this operation, and the diode 15 is used to maintain the charging time constant for a relatively large-capacity capacitor for fast attack and slow release, which are necessary when receiving SSB or telegrams. It has the effect of shortening the

The diode inserted between terminals A and B is 3
When more than one receiver is connected using the above method, it is effective to mute all adjacent receivers and lower priority receivers when used.

As described above, when using the present invention, only the receiver with the highest priority among multiple standby receivers operates, so only one operator is required, and there is no risk of misunderstanding the order of priority reception. However, the practical effects are significant.

[Brief explanation of drawings]

FIG. 1 is an illustration of an example of use according to the present invention, and FIG. 2 shows an example of an implementation circuit of the present invention. 1...AF amplifier, 2...speaker, 3, 4,
11, 14... Capacitor, 5, 8, 9, 10,
13...Resistor, 7,12...Transistor, 1
5, 18...Diode, 16...Threshold adjuster.

Claims (1)

[Claims for Utility Model Registration] In a radio receiver or transceiver, (1) a terminal for inputting a control level from a receiver or transceiver with a higher reception priority, and a terminal for inputting a control level from a receiver or transceiver with a lower reception priority; (2) When the level of the input terminal is L, the AF signal is muted by turning ON conduction between the collector and emitter of the first control transistor provided in parallel with the AF signal circuit. (3) a circuit that turns on conduction between the collector and emitter of the second control transistor in response to the reception input;
(4) A circuit that clamps to L level when it is ON; (4) so inserted between the input terminal and the output terminal;
A prioritized receiver mute circuit comprising: a diode that clamps an output terminal line to L level when the input terminal line is L level;