JPS6236395B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a built-in capacitor, and particularly to a semiconductor device having a semiconductor capacitive element for high frequency.

As shown in Fig. 1, an oscillation circuit for electronic watches generally includes a crystal oscillator 1, a bias resistor RF, and an amplifier 2 connected in parallel, with capacitors C _G and C _D connected to both terminals. When a capacitor is built into a semiconductor device, C _G or C _D is used as shown in Figure 5.
One of these will be built-in, and the other will have a variable capacitance. Conventionally, when forming capacitors in semiconductor integrated circuits, (1) MOS (metal monoxide film) is used.
(2) junction capacitance using the diffusion layer-substrate,
(3) Junction capacitance using a diffusion layer-well region is known. However, due to the structure of these capacitors, a voltage is applied with a reverse bias, so the voltage causes an extension of the inversion layer and space charge layer on the semiconductor surface and the junction of the diffusion layer, so the capacitance value changes due to the so-called applied voltage dependence. have sex. In order to eliminate such voltage dependence, the applicant has developed the
A P-type well region 4 is formed in an n-type silicon substrate 3 as shown in the figure, a polysilicon layer 6 is formed on the surface of this well region with a gate oxide film 5 interposed therebetween, and is tightly opened in a passivation film 7. A semiconductor capacitive element was developed in which electrodes 8 and 9 were provided on the polysilicon layer 6 and the well 4, respectively, and a forward bias voltage was constantly applied to the electrode 8 of the polysilicon layer.

By the way, there are two types of crystals used in the oscillation circuit for watches: 32768KHz and 4194304MHz. When performing 32768 KHz oscillation with the above-mentioned forward bias voltage application type semiconductor capacitor element, the same characteristics are obtained with the external capacitor and the built-in capacitor, and there is no problem as the influence of parasitic resistance as described below is not observed. However, when performing high frequency oscillation such as 4194304 MHz with the forward bias voltage application type semiconductor capacitor element, there is a large difference in characteristics between an external capacitor and a built-in capacitor. That is, it has been found that when a capacitor is formed within a semiconductor integrated circuit, the electrical characteristics are significantly deteriorated. The cause of such deterioration of electrical characteristics is considered to be due to parasitic resistance. Parasitic resistance is the third
As shown in FIG. 4 and its equivalent circuit, the sheet resistances R ₁ , R ₁ , R ₁ in the polysilicon layer 6 are
(75Ω/cm ² ) and well surface diffusion resistance R ₂ , R ₂ , R ₂
(5KΩ/cm ² ) is a distribution constant. In this case, the lower limit voltage for operation (V _DDMIN ) and current consumption (I _DD ) are significantly affected and cannot be ignored. In particular, in the 1.5V system, if V _DDMIN increases by 0.05V, the yield deteriorates by more than 10%, so as shown in FIG. 6, even the addition of a parasitic resistance of about 300Ω causes a deterioration of more than 0.15V, which becomes a fatal defect.

The present invention has been made to eliminate the above-mentioned deficiencies of the prior art, and therefore, an object of the present invention is to eliminate the influence of parasitic resistance in a capacitive element built into a semiconductor integrated circuit used for high frequency oscillation.

In order to achieve the above object, in one embodiment of the present invention, in a forward bias voltage application type semiconductor capacitor element, contacts are provided in a semiconductor well region and a polycrystalline semiconductor layer at positions that partially cut them into a plurality of resistance regions. provided. Then, the contacts in the well region and the contacts in the polycrystalline semiconductor layer are electrically connected. This creates a structure that suppresses parasitic resistance. Although not particularly limited, the contact is provided at a position where the resistances of the well region and the polycrystalline semiconductor layer are equally divided.

The present invention will be explained below with reference to the embodiments shown in FIGS. 7 and 8. In this figure, components common to the conventional example are indicated by the same reference symbols as in FIGS. 2 and 3. As shown ⁱⁿ FIG. 8, the passivation film is opened in the polysilicon layer 6 and contacts 8', 8', . P ⁺ diffusion layers 4', 4'... are provided, and a plurality of contacts 9', 4', etc. are provided on the aluminum wiring to divide the diffused resistance into several parts.
9'... is provided. In this embodiment, contacts 8, 8', 8', . . . to the polysilicon layer and contacts 9, 9', . . . to the well region are provided alternately and spread radially from the center to the periphery. . FIG. 9 shows the equivalent circuit of FIG. 8, and the resistance values attached to the OS _CIN side and the V _DD (+) side are much smaller than those shown in FIG. 4 as a conventional example. This is because by providing contacts 8' and 9' in each part, the overall resistance can be divided and the parasitic resistance can be reduced. In such a structure, in order to suppress parasitic resistance, it is desirable to make the distance between the gate part of the MOS used as a capacitor and the source/drain part as short as possible, and to make them equidistant.

Since the present invention makes contact between the polysilicon layer and the aluminum wiring on the thick oxide film at multiple locations, it is possible to reduce the parasitic resistance and provide a capacitive element that does not destroy the insulating film in the capacitive part. There is an effect.

The present invention is not limited to the above embodiments.

Various patterns can be considered for connecting the sheet resistor and the diffused resistor with contacts, as shown in FIGS. 10 and 11, for example. In the figure, the hatched area 10 and the unhatched white area 11 are the contact area and wiring for the polysilicon layer (sheet resistance);
The other is a well region (contact portion and wiring for the diffused resistor), which are arranged alternately and connected to each other by aluminum wiring or the like.

The present invention is effective in semiconductor-embedded capacitive elements in high frequency bands, and is therefore particularly suitable for being incorporated into a single semiconductor substrate as a complementary IC together with P-channel and N-channel MOSFETs.

[Brief explanation of the drawing]

FIG. 1 is a general circuit diagram of a watch oscillator circuit. Figures 2 to 4 show examples of semiconductor capacitive elements conceived by the applicant, where Figure 2 is a plan layout diagram, Figure 3 is a sectional view taken along line A-A in Figure 2, and Figure 4 is its equivalent. It is a circuit diagram. Fig. 5 is a circuit diagram showing an example in which a part of the capacitance is built into a semiconductor in an oscillation circuit, Fig. 6 is a relationship curve diagram between parasitic resistance and lower operating limit voltage, and Figs. 7 to 9 are semiconductor capacitors according to the present invention. One embodiment of the device is shown, with FIG. 7 being a plan layout diagram, FIG. 8 being a sectional view taken along line BB in FIG. 7, and FIG. 9 being an equivalent circuit diagram thereof. FIGS. 10 and 11 are plan layout diagrams showing other embodiments of the semiconductor capacitive element according to the present invention. DESCRIPTION OF SYMBOLS 1...Crystal oscillator, 2...Amplifier, 3...Silicon substrate, 4...Well region, 4'...P ⁺ diffusion layer, 5...Gate insulating film, 6...Polysilicon layer, 7... Passivation film, 8, 9... Electrode, 8', 9'... Contact part, 10, 11...
Contact part and wiring.

Claims (1)

[Claims] 1. A second conductivity type semiconductor region that is formed on a first conductivity type semiconductor substrate having a thin insulating film and a thick insulating film on its surface and forming one electrode of a capacitor;
A semiconductor device comprising a thin insulating film and a polysilicon layer formed on a semiconductor region via a thick insulating film and forming the other electrode of a capacitive element, the polysilicon layer having a plurality of locations of the thick insulating film. 1. A semiconductor device, wherein contacts between a polysilicon layer and an aluminum wiring are provided on the top, and the contacts at the plurality of locations are electrically coupled to each other.