JPS58159367A - MOS capacitor device - Google Patents
MOS capacitor deviceInfo
- Publication number
- JPS58159367A JPS58159367A JP57043434A JP4343482A JPS58159367A JP S58159367 A JPS58159367 A JP S58159367A JP 57043434 A JP57043434 A JP 57043434A JP 4343482 A JP4343482 A JP 4343482A JP S58159367 A JPS58159367 A JP S58159367A
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- Prior art keywords
- capacitor
- electrode
- complementary
- circuit
- capacitor device
- Prior art date
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
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- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明はMO8容量装置に関し、とくに、相補型MO8
装置と水晶振動子とを組合せた、いわゆる相補型MO5
水晶発振器の安定化に有用なMO5容量装置を提供する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MO8 capacitor device, and more particularly to a complementary MO8 capacitor device.
A so-called complementary MO5 that combines a device and a crystal oscillator.
An MO5 capacitor device useful for stabilizing a crystal oscillator is provided.
一般に1.アナログまたはデジタル電子時計において、
相補型MO8水晶発振器は周波数安定度が非常に良好で
、かつ低電圧、低消費電流特性を有する為、多く利用さ
れるようになった。このような電子時計において電源電
圧の変動に対する周波数安定度は最も重要な要素である
。この電源電圧に依る周波数の変動を支配するのが水晶
発振回路部である。Generally 1. In analog or digital electronic watches,
Complementary MO8 crystal oscillators have very good frequency stability, low voltage, and low current consumption characteristics, so they have become widely used. In such electronic watches, frequency stability against fluctuations in power supply voltage is the most important element. The crystal oscillation circuit unit controls frequency fluctuations depending on the power supply voltage.
先ず、水晶発振器の回路構成について説明する。First, the circuit configuration of the crystal oscillator will be explained.
通常の相補型MO8水晶発振回路の構成例を第1図に示
す。第1図においてムは相補型MO8)ランジスタで構
成される反転増幅器、k増幅器と共振回路との間の緩衝
抵抗、rtalは水晶振動子である。■及びGgは水晶
振動子の共振容量である。An example of the configuration of a typical complementary MO8 crystal oscillation circuit is shown in FIG. In FIG. 1, M is an inverting amplifier composed of complementary MO8) transistors, k is a buffer resistor between the amplifier and the resonant circuit, and rtal is a crystal oscillator. (2) and Gg are the resonance capacitances of the crystal resonator.
次に、前記反転増幅器ムの内部結線図を第2図に示す。Next, FIG. 2 shows an internal wiring diagram of the inverting amplifier.
Rfは直流バイアス用の抵抗性素子で、発振回路の利得
や正相に影響を与えないようにする為に、通常10MΩ
以上の値に選ばれる。T1及びT2は互いに相補型をな
すPチャネル型及びNチャネル型MO5)7ンジスタで
、それぞれのソースは電源VDD、 Vaaに接続され
、実用回路では、通常電源電圧がVDD−Vaa間に1
.6v印加されると水晶振動子の固有振動周波数に応じ
て発振を行なう。Rf is a resistive element for DC bias, and is usually 10MΩ in order not to affect the gain or positive phase of the oscillation circuit.
The value above is selected. T1 and T2 are P-channel type and N-channel type MO5)7 transistors which are complementary to each other, and their respective sources are connected to the power supplies VDD and Vaa.In practical circuits, the power supply voltage is usually 1 between VDD and Vaa.
.. When 6V is applied, oscillation occurs according to the natural vibration frequency of the crystal resonator.
第3図に従来電子時計に使用されている前記第1図示水
晶発振器の反転増幅器ムの入力側に接続されたMO8容
量Cgのマスクレイアウトの平面図で示す。また、第4
図は同装置のムーム′断面概要図である。このようなM
O8容量素子は下記のようにして相補型MO8)ランジ
スタ集積回路と一体形成される。ただし、相補型MO8
)ランジスタの構成部分の詳しい説明は省略する。第3
図。FIG. 3 is a plan view showing a mask layout of an MO8 capacitor Cg connected to the input side of the inverting amplifier of the crystal oscillator shown in the first figure, which is conventionally used in an electronic watch. Also, the fourth
The figure is a schematic cross-sectional view of the device. M like this
The O8 capacitive element is integrally formed with a complementary MO8 transistor integrated circuit in the following manner. However, complementary MO8
) A detailed explanation of the constituent parts of the transistor will be omitted. Third
figure.
第4図に示すようにN型シリコン(比抵抗1〜10Ω・
cIn)基板1上にPウェルマスク合わせをおこないボ
ロンイオンを加速電圧数十keVで注入し、アニール・
ドライブイン酸化をおこない、拡散深さを数μmに制御
したf拡散層2および保護酸化膜3を形成する。その後
、MOSトランジスタチャネル形成用マスクと一体形成
のマスクで前記f拡散層2上の前記保護酸化膜3をエツ
チングし、同所にMO8)う/ジスタ用ゲート酸化膜と
同じ組成物の誘電体層4を形成する。通常、ゲート酸化
膜の厚さは約1200ムであり、前記誘電体層4も同じ
厚みである。次に、MO−8)ランジスタのゲート電極
および第一層配線を形成する為の多結晶シリコンマスク
合わせ工程をおこない、約6000の後P+拡散領域6
形成のだめの窓開は用マスクによって、前記保護酸化膜
3を窓開けし、ボロンを加速電圧数十KeVで注入し、
ついで、全面に酸化膜7を堆積し、さらに、コンタクト
窓開は用マスクでコンタクト電極領域8を作り、このコ
ンタクトLli極領域8および前記?拡散領域6にまた
がる第21−配線を形成するアルミニウム用マスクなら
びに前記第1層配線の多結晶シリコン膜6へのコンタク
ト用マスクでそれぞれの所定窓開けの後、同所にアルミ
ニウム膜9(,9−bを蒸着して電極を形成する。なお
、前記P1拡散領域6および前記コンタクト電極領域8
は相補型MO+3 トランジスタのソースおよびドレイ
ン各領域の形成工程で同時に送り込まれる。また、10
はコンタクト部分を示す。As shown in Figure 4, N-type silicon (specific resistance 1~10Ω・
cIn) After aligning the P-well mask onto the substrate 1, boron ions are implanted at an acceleration voltage of several tens of keV, and annealing is performed.
Drive-in oxidation is performed to form an f diffusion layer 2 and a protective oxide film 3 with a diffusion depth controlled to several μm. Thereafter, the protective oxide film 3 on the f diffusion layer 2 is etched using a mask integrally formed with the MOS transistor channel forming mask, and a dielectric layer of the same composition as the gate oxide film for MO8) is placed in the same place. form 4. Typically, the gate oxide film has a thickness of about 1200 µm, and the dielectric layer 4 has the same thickness. Next, a polycrystalline silicon mask alignment process is performed to form MO-8) transistor gate electrodes and first layer wiring, and after about 6,000 yen, P+ diffusion region 6
The protective oxide film 3 is opened using a mask to form a window, and boron is implanted at an accelerating voltage of several tens of KeV.
Next, an oxide film 7 is deposited on the entire surface, and a contact electrode region 8 is formed using a contact window opening mask, and this contact Lli electrode region 8 and the above-mentioned ? After opening a predetermined window in each of the aluminum mask for forming the 21st interconnection spanning the diffusion region 6 and the contact mask for the polycrystalline silicon film 6 of the first layer interconnection, the aluminum film 9 (, 9 -b is vapor-deposited to form an electrode. Note that the P1 diffusion region 6 and the contact electrode region 8
is fed simultaneously in the process of forming the source and drain regions of the complementary MO+3 transistor. Also, 10
indicates the contact part.
第3図および第4図で示すMO8容量素子の等価回路を
示すと第6図のようになる。第5図において、一方の前
記アルミニウム膜電極9−4は電源の高電位端子であり
、他方の前記!ルミニウム膜電極9−bはMO8容量の
他方の電極端子である。FIG. 6 shows an equivalent circuit of the MO8 capacitive element shown in FIGS. 3 and 4. In FIG. 5, one of the aluminum film electrodes 9-4 is a high potential terminal of a power supply, and the other aluminum film electrode 9-4 is a high potential terminal of a power source. The aluminum membrane electrode 9-b is the other electrode terminal of the MO8 capacitor.
またD+、 02. Os・・・・・・Ci及びP+、
R2,Rs・叩・亀はそれぞれ、前記f拡散層2およ
び前記多結晶シリコン膜6間に分布する容量および内部
抵抗である。Also D+, 02. Os...Ci and P+,
R2, Rs, R, and R are the capacitance and internal resistance distributed between the f diffusion layer 2 and the polycrystalline silicon film 6, respectively.
第5図の等価回路は分布定数として抵抗R4l容槍Ci
のRe分布定数回路とみなされる。さらに第6図を集中
定数モデルに簡単化すると第6図のようになる。第6図
において、RおよびCは第6図のR1,R2・・・・・
・■および01.02.・川・・C1との関係で次式の
ようにあられされる。The equivalent circuit in Fig. 5 shows the resistance R4l capacity Ci as a distributed constant.
It is considered as a Re distributed constant circuit. Furthermore, when FIG. 6 is simplified to a lumped constant model, it becomes as shown in FIG. In Fig. 6, R and C are R1, R2 in Fig. 6...
・■ and 01.02.・River...It appears as shown in the following equation in relation to C1.
1=1
一ト記構成のMO8容量ag、すなわち多結晶シリコン
膜6により形成された電極と拡散層2とにより形成され
たMO8型容量にあって、前記多結晶シリコン膜6直下
の拡散層2と拡散層2の電位取り出し口9−ILとの間
で形成される抵抗Rと前記MO8容量装置の容量Cとの
積で構成される時定数が内部抵抗成分の為に大きくなる
。このため、この時定数が発振回路の周期よりも長くな
ることがあり、水晶振動子の基準発振に追従しなくなる
。1=1 In the MO8 capacitor ag having a one-note configuration, that is, the MO8 type capacitor formed by the electrode formed by the polycrystalline silicon film 6 and the diffusion layer 2, the diffusion layer 2 directly under the polycrystalline silicon film 6 A time constant constituted by the product of the resistance R formed between and the potential extraction port 9-IL of the diffusion layer 2 and the capacitance C of the MO8 capacitor device becomes large due to the internal resistance component. For this reason, this time constant may become longer than the period of the oscillation circuit, and the reference oscillation of the crystal resonator cannot be followed.
従って、発振動作が不安定になり、後段に接続されるカ
ウンタが誤分周を行ない、水晶発振回路として不安定な
特性となる欠点があった。なお、第1図示の回路構成で
、反転増幅器ムの出力側に接続される容量ωをMO8容
量装置で形成する場合にも同様のことが言える。Therefore, the oscillation operation becomes unstable, and the counter connected at the subsequent stage performs erroneous frequency division, resulting in unstable characteristics as a crystal oscillation circuit. The same thing can be said in the case where the capacitor ω connected to the output side of the inverting amplifier is formed by an MO8 capacitor device in the circuit configuration shown in FIG.
本発明は相補型MO8水晶発振回路の入力側ないしは出
力側に接続されたMO8容量cgないしは艶とが、その
構造上必然的にもつ内部抵抗R(すなわち、前記f拡散
層2の抵抗)によって決まる時定数の大きさで水晶発振
器が特定の基準発振をしなくなる為に起こる欠点、すな
わち、後段に接続されたカウンタが誤分周する欠点を除
去しようとするもので、前記MO8O8容量−しは(に
付随する内部抵抗成分を小さクシ、前記容量素子で決ま
る時定数を小さくシ、水晶振動子の基準周波数に確実に
追従させることのできるMO8容量装置を提供するもの
である。In the present invention, the MO8 capacitor cg or capacitance connected to the input side or the output side of the complementary MO8 crystal oscillation circuit is determined by the internal resistance R (that is, the resistance of the f diffusion layer 2) that is necessarily present in its structure. This is intended to eliminate the drawback that occurs when the crystal oscillator does not perform a specific reference oscillation due to the size of the time constant, that is, the counter connected to the subsequent stage incorrectly divides the frequency. The purpose of the present invention is to provide an MO8 capacitor device that can reduce the internal resistance component associated with the capacitive element, reduce the time constant determined by the capacitive element, and reliably follow the reference frequency of the crystal resonator.
以下、本発明の構成について説明する。本発明のMO8
容量装置は第7図の構成で示される。第8図は第7図に
おけるB −B’の断面概要図である。1第7図、第8
図において、第3図、第4図と同一番号は同一部分を示
し、MO8容量の電極g−a1゜9−b′は櫛形に形成
されている。従って、f拡散層2のコンタクとf拡散領
域6′はP−拡散層2中に多数形成される構造となる。The configuration of the present invention will be explained below. MO8 of the present invention
The capacitive device is shown in the configuration of FIG. FIG. 8 is a schematic cross-sectional view taken along line B-B' in FIG. 7. 1 Figures 7 and 8
In the figure, the same numbers as in FIGS. 3 and 4 indicate the same parts, and the MO8 capacitor electrode g-a19-b' is formed in a comb shape. Therefore, a large number of contacts of the f-diffusion layer 2 and f-diffusion regions 6' are formed in the p-diffusion layer 2.
第9図は第8図の構造のMO8容量装置を抵抗司と容址
句のRC分布定数回路として表わしたものであり、従来
例との大きな差異は第9図にみられる等簡約配線要素1
1によって、内部抵抗要素R+、 R2・・・・・・阻
が外部端子側からみて並列化されるようになしだ点にあ
る。Figure 9 shows the MO8 capacitor device with the structure shown in Figure 8 as an RC distributed constant circuit with resistors and capacitors.The major difference from the conventional example is the simplified wiring element 1 shown in Figure 9.
1, the internal resistance elements R+, R2, etc. are arranged in parallel when viewed from the external terminal side.
さらに第9図を集中定数モデルに簡単化すると第10図
のようになる。ただし、本発明のMO8容量装置の製造
方法は前記従来例MO8容量の製造工程を何ら変更する
必要のないものである。Furthermore, when FIG. 9 is simplified to a lumped constant model, it becomes as shown in FIG. 10. However, the method for manufacturing an MO8 capacitor according to the present invention does not require any change in the manufacturing process for the conventional MO8 capacitor.
第7図および第8図に示すMO8容量装置の構造ではf
拡散層2内に設ける?拡散領域6′を細長い平面形状で
分布させ、これらを第2層配線のアルミニウム膜9−a
′で電極結合している。このように、MO8容量装置の
一方の接触電極体を櫛形にしている為、電源の高電位端
子9−a′につながる前記P−拡散層2の実効的距離が
減少している。その為、F配列部端子9−&’と前記P
−拡散層2間の内部抵抗が小さくなる。すなわち、内蔵
MO8容量を第8図のような構成にすることによって、
前記電源の高電位端子リーaとf拡散層2との間の内部
抵抗が同P−拡散層2内で等電位結合され、あたかも、
第9図示の配線要素11で結合されたようになって、実
効的に各分布抵抗を並列化することによってその等筒内
部抵抗が減少する。しだがって、時定数は従来の構成に
よるMO8容量より小さくなり、高周波用水晶振動子の
相補型MO3の発振回路の動作に十分追従する。なお、
多結晶シリコン膜6およびその直下の誘電体層4′も、
前記高電位端子cd −& と並行してその櫛型電極
体間にス互に絡ませて配置して、その外部端子d−bは
櫛型対称に形成される。In the structure of the MO8 capacitor shown in FIGS. 7 and 8, f
Provided within the diffusion layer 2? The diffusion regions 6' are distributed in an elongated planar shape, and these are distributed over the aluminum film 9-a of the second layer wiring.
′ is connected to the electrode. In this way, since one contact electrode body of the MO8 capacitive device is comb-shaped, the effective distance of the P- diffusion layer 2 connected to the high potential terminal 9-a' of the power source is reduced. Therefore, the F array part terminal 9-&' and the P
-The internal resistance between the diffusion layers 2 is reduced. That is, by configuring the built-in MO8 capacitor as shown in Fig. 8,
The internal resistance between the high potential terminal lead a of the power supply and the f diffusion layer 2 is coupled to the same potential within the same p diffusion layer 2, as if
By effectively parallelizing each distributed resistance by connecting them by the wiring element 11 shown in FIG. 9, the internal resistance of the equal cylinders is reduced. Therefore, the time constant is smaller than the MO8 capacitor with the conventional configuration, and it sufficiently follows the operation of the complementary MO3 oscillation circuit of the high frequency crystal resonator. In addition,
The polycrystalline silicon film 6 and the dielectric layer 4' immediately below it are also
The external terminals d-b are arranged parallel to the high-potential terminals cd-& and intertwined with each other between the comb-shaped electrode bodies, and the external terminals d-b are formed in a comb-shaped symmetry.
従って、かかる構成のMO8容量装置を用いた相補型M
O8水晶発振回路では、その後段に接続されたカウンタ
が誤分周するという不都合はなく、時計用ICに応用し
て、その時刻の正確さを期することができる。Therefore, complementary M
The O8 crystal oscillator circuit does not have the problem of incorrect frequency division of the counter connected to the subsequent stage, and can be applied to a clock IC to ensure the accuracy of the time.
なお、本発明のMO8容量装置は前述の実施例のプロセ
スはPウェル型CMO5で説明しているが、Nウェル型
0MO8でも全く同じである。そしてモノリシックIC
に内蔵することによって時計組立の作業工数が減り、ト
リミング用の容量のみ外付けすればよいだけである。In the MO8 capacitor device of the present invention, although the process of the above-mentioned embodiment is explained for P-well type CMO5, it is exactly the same for N-well type 0MO8. and monolithic IC
By incorporating the device into the device, the number of man-hours required for assembling the watch is reduced, and only the trimming capacity needs to be externally attached.
以上の如く、本発明は簡単な構成によりMO8容量の内
部抵抗を減少させることが可能なMO8容量装置を提供
出来るので、その工業的価値は大である。As described above, the present invention can provide an MO8 capacitor device that can reduce the internal resistance of the MO8 capacitor with a simple configuration, and therefore has great industrial value.
第1図は通常の相補型MO8水晶発振器の回路構成図、
第2図は第1図発振回路中の相補型MO8反転反転器の
回路図、第3Nおよび第4図は従来の相補型MO+3容
量の概要平面図およびそのムームl断面図、第6図は等
価的分布定数回路図、第6図は等価的集中定数回路図、
第7図及び第8図は本発明のMO8容量の概要平面図お
よびそのB−Br断面図、第9図は同装置の等価的分布
定数回路図、第10図は同装置の等価的集中定数回路図
をそれぞれ示す。
1・・・・・・1型シリコン基板、2・・・・・・P−
拡散層、3・・・・・保護酸化膜、4・・・・・・誘電
体層、5・・・・・・多結晶ンリコン膜、d・・・・・
・?拡散領域、7・・・・・・酸化シリコン膜、8・・
・・・・コンタクト電極領域、9−a’ 、 e−b’
・・・・・・アルミニウム膜電極。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図
第2図
4m
27
第5図
第6図
第7図
第8図Figure 1 is a circuit diagram of a typical complementary MO8 crystal oscillator.
Figure 2 is a circuit diagram of the complementary MO8 inverter in the oscillation circuit of Figure 1, Figures 3N and 4 are a schematic plan view and a cross-sectional view of the conventional complementary MO+3 capacitor, and Figure 6 is the equivalent. Figure 6 is an equivalent lumped constant circuit diagram.
Figures 7 and 8 are a schematic plan view and a B-Br sectional view of the MO8 capacitor of the present invention, Figure 9 is an equivalent distributed constant circuit diagram of the same device, and Figure 10 is an equivalent lumped constant diagram of the same device. A circuit diagram is shown for each. 1...1 type silicon substrate, 2...P-
Diffusion layer, 3... Protective oxide film, 4... Dielectric layer, 5... Polycrystalline silicon film, d...
・? Diffusion region, 7...Silicon oxide film, 8...
...Contact electrode area, 9-a', eb'
...Aluminum film electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 4m 27 Figure 5 Figure 6 Figure 7 Figure 8
Claims (1)
領域上に誘電体層を介して多結晶シリコン膜を設けて他
方の電極となす容鎗装置で、前記拡散領域への接触電極
体および前記多結晶シリコン膜電極とを交互に配してそ
れぞれ櫛形に形成したことを特徴とするMO8容量装置
。A forceps device in which a predetermined diffusion region of a semiconductor substrate is used as one electrode, and a polycrystalline silicon film is provided on the diffusion region via a dielectric layer to serve as the other electrode. An MO8 capacitor device characterized in that polycrystalline silicon film electrodes are alternately arranged and each formed in a comb shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57043434A JPS58159367A (en) | 1982-03-17 | 1982-03-17 | MOS capacitor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57043434A JPS58159367A (en) | 1982-03-17 | 1982-03-17 | MOS capacitor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58159367A true JPS58159367A (en) | 1983-09-21 |
Family
ID=12663585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57043434A Pending JPS58159367A (en) | 1982-03-17 | 1982-03-17 | MOS capacitor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58159367A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01133354A (en) * | 1987-11-19 | 1989-05-25 | Sanyo Electric Co Ltd | Semiconductor integrated circuit and manufacture thereof |
| JPH02228063A (en) * | 1989-01-06 | 1990-09-11 | Ncr Corp | High frequency integrated circuit channel capacitor |
| JPH04177762A (en) * | 1990-11-09 | 1992-06-24 | Nec Ic Microcomput Syst Ltd | Semiconductor device |
| EP0822601A1 (en) * | 1996-07-30 | 1998-02-04 | STMicroelectronics S.r.l. | MOS capacitor with wide voltage and frequency operating ranges |
| US6340832B2 (en) | 2000-03-28 | 2002-01-22 | Nec Corporation | MIM capacitor having reduced capacitance error and phase rotation |
| US6974744B1 (en) | 2000-09-05 | 2005-12-13 | Marvell International Ltd. | Fringing capacitor structure |
| US6980414B1 (en) | 2004-06-16 | 2005-12-27 | Marvell International, Ltd. | Capacitor structure in a semiconductor device |
| US7215003B2 (en) | 2000-11-17 | 2007-05-08 | Rohm Co., Ltd. | Driver for driving a load using a charge pump circuit |
| JP2007250705A (en) * | 2006-03-15 | 2007-09-27 | Nec Electronics Corp | Semiconductor integrated circuit device and dummy pattern arrangement method |
| CN112331653A (en) * | 2020-10-29 | 2021-02-05 | 长江存储科技有限责任公司 | Semiconductor device, three-dimensional memory and semiconductor device manufacturing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5558561A (en) * | 1978-10-25 | 1980-05-01 | Hitachi Ltd | Semiconductor capacitance element |
-
1982
- 1982-03-17 JP JP57043434A patent/JPS58159367A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5558561A (en) * | 1978-10-25 | 1980-05-01 | Hitachi Ltd | Semiconductor capacitance element |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01133354A (en) * | 1987-11-19 | 1989-05-25 | Sanyo Electric Co Ltd | Semiconductor integrated circuit and manufacture thereof |
| JPH02228063A (en) * | 1989-01-06 | 1990-09-11 | Ncr Corp | High frequency integrated circuit channel capacitor |
| JPH04177762A (en) * | 1990-11-09 | 1992-06-24 | Nec Ic Microcomput Syst Ltd | Semiconductor device |
| EP0822601A1 (en) * | 1996-07-30 | 1998-02-04 | STMicroelectronics S.r.l. | MOS capacitor with wide voltage and frequency operating ranges |
| US6590247B2 (en) | 1996-07-30 | 2003-07-08 | Sgs-Thomson Microelectronics S.R.L. | MOS capacitor with wide voltage and frequency operating ranges |
| US6340832B2 (en) | 2000-03-28 | 2002-01-22 | Nec Corporation | MIM capacitor having reduced capacitance error and phase rotation |
| US6974744B1 (en) | 2000-09-05 | 2005-12-13 | Marvell International Ltd. | Fringing capacitor structure |
| US7436015B2 (en) | 2000-11-17 | 2008-10-14 | Rohm Co., Ltd | Driver for driving a load using a charge pump circuit |
| US7215003B2 (en) | 2000-11-17 | 2007-05-08 | Rohm Co., Ltd. | Driver for driving a load using a charge pump circuit |
| US8441054B2 (en) | 2000-11-17 | 2013-05-14 | Rohm Co., Ltd. | Driver for driving a load using a charge pump circuit |
| US9017427B1 (en) | 2001-01-18 | 2015-04-28 | Marvell International Ltd. | Method of creating capacitor structure in a semiconductor device |
| US7116544B1 (en) | 2004-06-16 | 2006-10-03 | Marvell International, Ltd. | Capacitor structure in a semiconductor device |
| US7578858B1 (en) | 2004-06-16 | 2009-08-25 | Marvell International Ltd. | Making capacitor structure in a semiconductor device |
| US7988744B1 (en) | 2004-06-16 | 2011-08-02 | Marvell International Ltd. | Method of producing capacitor structure in a semiconductor device |
| US8537524B1 (en) | 2004-06-16 | 2013-09-17 | Marvell International Ltd. | Capacitor structure in a semiconductor device |
| US6980414B1 (en) | 2004-06-16 | 2005-12-27 | Marvell International, Ltd. | Capacitor structure in a semiconductor device |
| JP2007250705A (en) * | 2006-03-15 | 2007-09-27 | Nec Electronics Corp | Semiconductor integrated circuit device and dummy pattern arrangement method |
| CN112331653A (en) * | 2020-10-29 | 2021-02-05 | 长江存储科技有限责任公司 | Semiconductor device, three-dimensional memory and semiconductor device manufacturing method |
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