JPS6236852A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable the increase in the density and the integration of a semiconductor device by laminating a high melting point metal film or a high melting point metal silicide film on a polysilicon film of a connecting wiring portion to reduce a high resistance load. CONSTITUTION:In a semiconductor device having a polysilicon film which contains a high resistance load and a connecting wiring portion, a high melting point metal film or a high melting point metal silicide film is laminated on the wiring portion. Thus, since the impurity implanting amount to the low resistance can be reduced, lateral diffusion of an impurity to the high resistance can be reduced. The low resistance wiring portion is formed in 2-layer structure of high melting point metal or its silicide on the polysilicon to be lower resistance than a sole polysilicon wiring layer to reduce a wiring delay.

Description

Detailed Description of the Invention <Industrial Application Field> The present invention provides a semiconductor device having a polysilicon film including a high resistance load section and a connection wiring section (for example, two high resistance loads and four transistors). This invention relates to a static semiconductor memory device (such as a static type semiconductor memory device configured with a 1-bit memory cell).

<Prior art> A static semiconductor memory device (hereinafter referred to as rs) in which information is held in a flip-70 block type circuit (hereinafter referred to as rs) -RAM IC
In order to achieve high integration, high resistance load type memory cells, which can be formed into small memory cells, are often used. A high resistance load is usually formed from a second layer of polysilicon film, and this polysilicon film is also used for interconnections between elements.

One method of manufacturing the memory cell portion of a conventional S-RAM IC will be explained using FIGS.

An element isolation region 1, a gate oxide film 2, and three gate electrodes are formed without cutting. Next, ion implantation is performed in a self-aligned manner to completely form the source/drain region (n+ layer) 1 (
Figure 2(a)).

Next, a contact hole 5 is opened, a polysilicon film 6 is deposited, and an oxide film (SIO2 film) 7 is formed on the surface (FIG. 2(b)).

Next, the entire part that becomes a high resistance load is masked, i.e.,
After forming the resist film 8 on the part that will be a high resistance load and etching the oxide film, phosphorus or arsenic is applied, for example, at an acceleration energy of 80 KeV and a dose]
A low resistance part is formed by ion implantation at cm-2 (FIG. 2(C)).

Next, all wiring patterning, oxidation, deposition of a glass layer 9, and flow process of glass are carried out (see Figure 2).
d)).

Subsequently, contact holes are opened, metal wiring is completely formed, and a passivation film is deposited.

<Problems to be Solved by the Invention> It is desirable that the wiring resistance between elements be as low as possible, but when forming a high resistance part and a low resistance part in the same wiring as described above,
During high-temperature heat treatment such as phosphorus glass flow, impurities in the low-resistance portion diffuse into the high-resistance portion, so it was necessary to make the high-resistance portion considerably larger than the effective mass dandruff length, which hindered miniaturization. I was trying to suppress the seeping impurities,
When annealing is performed at a low temperature or for a short time, or when the amount of impurities is reduced, the resistance of the wiring portion increases.

The present invention has been made in view of the above points, and an object thereof is to make it possible to reduce the size of a high-resistance load section and to provide a low-resistance wiring section.

Means for solving the above problems〉 Forming a layer on a high melting point metal film or a high melting point metal silicide film on the polysilicon film of the connection wiring portion 〇<Example> The following is an example? The present invention will be explained in detail using the following description.

FIG. 3 is an equivalent circuit diagram of a memory cell of a fls-RAM IC to which the present invention is applied. R,, R2 are high resistance loads,
T, , T2 are L transistors forming a flip-flop association, T3. T4 is a transistor used for writing and reading information.

A cross-sectional view of the R, T portions is shown in FIG.

In FIG. 1, the portion under the CVD S io 2 film +7' is a high resistance portion, and the portion consisting of two layers of polysilicon film 16 and tungsten film 20 is a low resistance portion.

FIGS. 4(a) to 4(a) are flowcharts of the process. First, an element isolation region 11, a gate oxide film 12, and a gate electrode 13 are formed. Next, ion implantation is performed in a self-aligned manner to form source/drain regions (n+ layer) 14 (FIG. 4(a)).

Next, 15 contact holes were opened, 16 second-layer polysilicon films were deposited, and CVD Sio2
17 films are deposited (FIG. 4 et al.)).

Next, a S r 02 film 17' that will serve as a mask for the high resistance part is formed by patterning, and selectively tungsten KC
A tungsten film 20 is formed on the polysilicon film 16 by depositing by VD method (FIG. 4(C)).

Next, phosphorus or arsenic ions are implanted, all activation annealing is performed, and wiring patterning 2 is performed. At this time, the ion implantation amount is less than one-tenth of that of the conventional method, for example, the acceleration energy is 80Ke, the dose is Amount I X I O” cm
-2. Next, 19 CV D S r 02 + phosphor glass layers are deposited and phosphorus glass flow 7 is performed (FIG. 4(d)).

Next, all contact holes are opened, all metal wiring is formed, and the passivation → John film is formed. Other Embodiments of Deposition In the above embodiments, tungsten was selectively deposited by CVD in forming the low-resistance wiring, but the same effect can be obtained with other high-melting point metals or high-melting point metal silicides. Further, the same applies not only to CVD but also to sputtering and the like.

Furthermore, the same effect can be obtained by depositing a high melting point metal layer by a battering method or the like, selectively siliciding the entire surface of the polysilicon, and removing the high melting point metal layer in the non-reacted areas. In order to facilitate silicidation, even if Ar, Si, etc. are implanted (ITM: Ion Implantation T
through Meta] or IBI: Ion B
eam induced 5 ilicides).

<Effects of the Invention> As described in detail above, the present invention provides a semiconductor device having a high resistance load portion, a connection wiring portion, and a polysilicon film including a high resistance load portion, a high melting point metal film or a high It is characterized by having a structure in which melting point metal silicide films are laminated, and provides the following effects.

゛(1) Since the amount of impurities introduced into the low-resistance portion can be reduced, is it possible to diffuse the impurity laterally into the high-resistance portion? The high resistance load section can be reduced in size. Therefore, a 5-RAM cell or the like can be made smaller, and it is possible to increase the density and integration of semiconductor devices.

(2) The low resistance wiring part has a two-layer structure with high melting point metal or its silicate on polysilicon,
Compared to single-layer polysilicon wiring, it has lower resistance and reduces wiring delays.

(3) Since the high-resistance portion and the low-resistance portion can be formed by self-alignment, the time can be reduced by about 2 seconds.

[Brief explanation of the drawing]

Figure 1 shows a cross section of a 5-RAM IC, which is an embodiment of the present invention, including a high resistance load section in a memory cell and transistors constituting a flip-flop. 3 is an equivalent circuit diagram of a 5-RAM IC memory cell, and FIG. 4 is a diagram showing a schematic manufacturing process of the embodiment shown in FIG. 1. Explanation of symbols 11° element isolation region, 12 gate oxide film, 13: gate electrode, 14: source/drain region (layer by layer LI5:
Contact hole, 16: Polysilico 7 film,] 7,
I 7”, CVD S IO2 film, 19°CVD5
r02+phosphorus glass layer, 20: tungsten film. Agent Patent attorney Aihiko Fukushi (and 2 others) 17--
----CVDSiO February 19-------CVDSi 02 film seri) Geras layer 2
0------・Kun 7゛Sten Moon Trap 5-RAMIC Mechani-ri and Lu-I surface circuit flash rate 3 Seki 18 Open 0362 36852 (4) ff11in+
41 signs of ``1 sword and 1 sword''
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Claims (1)

[Claims] 1. A semiconductor device having a polysilicon film including a high resistance load part and a connection wiring part, characterized in that a high melting point metal film or a high melting point metal silicide film is laminated on the connection wiring part. semiconductor devices.