JPS6237072A - Protective circuit for inverter - Google Patents

Protective circuit for inverter

Info

Publication number
JPS6237072A
JPS6237072A JP60176086A JP17608685A JPS6237072A JP S6237072 A JPS6237072 A JP S6237072A JP 60176086 A JP60176086 A JP 60176086A JP 17608685 A JP17608685 A JP 17608685A JP S6237072 A JPS6237072 A JP S6237072A
Authority
JP
Japan
Prior art keywords
conductive
signal
transistor
transistors
transformer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60176086A
Other languages
Japanese (ja)
Inventor
Osamu Kinoshita
治 木下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Telecom Networks Ltd
Original Assignee
Fujitsu Telecom Networks Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Telecom Networks Ltd filed Critical Fujitsu Telecom Networks Ltd
Priority to JP60176086A priority Critical patent/JPS6237072A/en
Publication of JPS6237072A publication Critical patent/JPS6237072A/en
Pending legal-status Critical Current

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  • Inverter Devices (AREA)

Abstract

PURPOSE:To prevent the states of the simultaneous conduction of switching elements, and to improve reliability by nullifying a signal from the other swtiching element when one signal of signals alternately bringing the switching elements to a conductive state is inputted in the signals. CONSTITUTION:A half-bridge type inverter circuit is constituted of a transformer 1, transistors 4, 6 for a switching element, a DC power supply 5 and capacitors 8, 9, the transistors 4, 6 are each switched and controlled by conductive signals d1, d2 through transformers 12, 15, etc., and AC voltage Va is outputted from a secondary winding 16 for the transformer 1. Diodes 17, 18 are fitted as control means at that time. Accordingly, when the conductive signal d1(d2) is inputted and one transistor 4(6) is set under a conductive state, possibility in which the other transistor 6(4) is brought to the conductive state can be prevented because the transistors are clamped by diodes 17, 18 even when disturbance signals are overlapped from the outside.

Description

【発明の詳細な説明】 〔概要〕 プリフジ形インバータにおいて、一方の開閉素子を導通
状態とする導通信号が入力された場合に、他方の開閉素
子に導通信号が入力されることを阻止する手段を設ける
ことにより、両開閉素子が同時に導通状態となり、事故
を発生することを防止する。
[Detailed Description of the Invention] [Summary] In a pre-Fuji type inverter, when a conduction signal that brings one switching element into a conductive state is input, a means for preventing a conduction signal from being input to the other switching element is provided. By providing this, it is possible to prevent both switching elements from becoming conductive at the same time and causing an accident.

〔産業上の利用分野〕[Industrial application field]

本発明は、インバータ回路に擾乱信号が入力された場合
にも、事故発生を防止可能とするインバータの保護回路
に関する。
The present invention relates to an inverter protection circuit that can prevent accidents even when a disturbance signal is input to the inverter circuit.

゛ 現在、直流電源から交流電圧を発生するインバータ
としては、変成器の1次捲線に接続する直流電源の極性
を所定周期で反転し、2次捲線に交流電圧を出力するハ
ーフブリッジ方式或いはフルブリフジ方式が広く採用さ
れている。
゛Currently, inverters that generate AC voltage from a DC power supply are half-bridge or full-bridge systems, which reverse the polarity of the DC power supply connected to the primary winding of the transformer at predetermined intervals and output AC voltage to the secondary winding. has been widely adopted.

かかるインバータ回路において、変成器の1次#@線に
直流電源の両極性端子を接続する開閉素子が誤動作する
と、直流電源を短絡することとなり、開閉素子の破損等
の大きな事故を惹起する。
In such an inverter circuit, if the switching element that connects the bipolar terminals of the DC power source to the primary #@ line of the transformer malfunctions, the DC power source will be short-circuited, causing a major accident such as damage to the switching element.

従ってかかる開閉素子の誤動作を極力防止する手段の実
現が強く要望されている。
Therefore, there is a strong demand for a means to prevent malfunctions of such switching elements as much as possible.

〔従来の技術〕[Conventional technology]

第3図は従来あるハーフブリッジ形インバータ回路の一
例を示す図であり、第4図は第3図における各種信号波
形を例示する図である。
FIG. 3 is a diagram showing an example of a conventional half-bridge type inverter circuit, and FIG. 4 is a diagram illustrating various signal waveforms in FIG. 3.

第3図において、変成器1の1次捲線2の端子3は、ト
ランジスタ4を介して直流電源5の正極性端子(+)に
、またトランジスタ6を介して直流電源5の負極性端子
(−)に接続されており、また端子7は、コンデンサ8
を介して正極性端子(+)に、コンデンサ9を介して負
極性端子(−)に接続されている。その結果直流電源5
の端子電圧■4は、コンデンサ8および9により直流電
圧Vdlおよび■4□に分圧される。
In FIG. 3, the terminal 3 of the primary winding 2 of the transformer 1 is connected to the positive terminal (+) of the DC power source 5 via the transistor 4, and to the negative terminal (-) of the DC power source 5 via the transistor 6. ), and terminal 7 is connected to capacitor 8
It is connected to the positive polarity terminal (+) through the capacitor 9, and to the negative polarity terminal (-) through the capacitor 9. As a result, DC power supply 5
Terminal voltage ■4 is divided by capacitors 8 and 9 into DC voltages Vdl and ■4□.

今入力端子10に、所定周期で論理“1”となる導通信
号dl  (第4図参照)を入力すると、トランジスタ
11が導通信号d、に同期して導通状態となり、変成器
12を介してトランジスタ4を、導通信号d、に同期し
て付勢する。
When the conduction signal dl (see FIG. 4), which becomes logic "1" at a predetermined period, is input to the input terminal 10, the transistor 11 becomes conductive in synchronization with the conduction signal d, and the transistor 4 is energized in synchronization with the conductive signal d.

付勢されたトランジスタ4は導通状態となり、変成器1
の1次捲線2には直流電圧V 41が印加され、端子3
から端子7に向けて、断続電流■、が流れる。
The energized transistor 4 becomes conductive and the transformer 1
A DC voltage V 41 is applied to the primary winding 2 of the terminal 3.
An intermittent current ■ flows from the terminal 7 toward the terminal 7.

同様に、導通信号d1と交互に論理“1”となる導通信
号d2 (第4図参照)を入力端子13に入力すると、
前述と同様の過程で、トランジスタ14および6が導通
信号d2に同期して導通状態となり、変成器1の1次捲
線2には直流電圧Vd2が印加され、端子7から端子3
に向けて、断続電流rT□が流れる。
Similarly, when the conductive signal d2 (see FIG. 4) which becomes logic "1" alternately with the conductive signal d1 is input to the input terminal 13,
In the same process as described above, transistors 14 and 6 become conductive in synchronization with conduction signal d2, DC voltage Vd2 is applied to primary winding 2 of transformer 1, and voltage from terminal 7 to terminal 3 is applied to primary winding 2 of transformer 1.
An intermittent current rT□ flows toward.

その結果変成器lの2次捲線16には、導通信号d、お
よびd2と同一周期の交流電圧■1が発生する。
As a result, in the secondary winding 16 of the transformer l, an alternating current voltage (1) having the same period as the conductive signals d and d2 is generated.

なお導通信号d、およびd2は第4図に示す如く、必ず
一方のみが論理“1”となる様配慮されているが、若し
導通信号d、またはd2に、第4図に示す如き擾乱信号
dXが、電源雑音、誘導障害その他に起因して重畳され
ると、トランジスタ11および14、従ってトランジス
タ4および6が同時に導通状態となり、直流電源5の端
子電圧V、を短絡することとなる。
Note that as shown in FIG. 4, the conductive signals d and d2 are designed to ensure that only one of them is logic "1"; however, if the conductive signal d or d2 receives a disturbance signal as shown in FIG. When dX is superimposed due to power supply noise, inductive interference, etc., transistors 11 and 14, and therefore transistors 4 and 6, become conductive at the same time, shorting the terminal voltage V of DC power supply 5.

その結果トランジスタ4および6が破損し、直流電源5
に設けられているヒユーズの溶断、或いはブレーカの遮
断等、大きな事故を発生する。
As a result, transistors 4 and 6 are damaged, and the DC power supply 5
A major accident may occur, such as the fuse installed in the machine blowing out or the breaker shutting off.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

以上の説明から明らかな如く、従来あるインバータ回路
においては、導通信号d、またはd2に擾乱信号dxが
重畳すると、トランジスタ4および6が同時に導通状態
となり、インバータに大きな事故を発生させる恐れがあ
った。
As is clear from the above explanation, in conventional inverter circuits, when the disturbance signal dx is superimposed on the conduction signal d or d2, the transistors 4 and 6 become conductive at the same time, which may cause a major accident in the inverter. .

〔問題点を解決するための手段〕[Means for solving problems]

第1図は本発明の原理を示す図である。 FIG. 1 is a diagram showing the principle of the present invention.

第1図においては、変成器100の1次捲線101に極
性の異なる直流電圧v4い■4□を、交互に導通状態と
なる開閉素子201.202を介して印加し、2次t4
[102に交流電圧を出力するインバータ回路において
、一方の開閉素子201(202)を導通状態とする信
号d+  (dz)が入力された場合に、他方の開閉素
子202(201)を導通状態とする信号dz(d+)
を無効とする制御手段300を設ける。
In FIG. 1, DC voltages v4 and 4 with different polarities are applied to the primary winding 101 of the transformer 100 through switching elements 201 and 202 which are alternately turned on, and the secondary winding t4
[In an inverter circuit that outputs an AC voltage to 102, when a signal d+ (dz) that makes one switching element 201 (202) conductive is input, the other switching element 202 (201) is made conductive. signal dz(d+)
A control means 300 is provided for disabling the.

〔作用〕[Effect]

即ち本発明によれば、信号d、およびd2が同時に有効
となることは防止され、開閉素子201および202が
同時に導通状態となることは防止され、インバータ回路
に事故の発生することを防止する。
That is, according to the present invention, signals d and d2 are prevented from becoming valid at the same time, and switching elements 201 and 202 are prevented from becoming conductive at the same time, thereby preventing an accident from occurring in the inverter circuit.

〔実施例〕〔Example〕

以下、本発明の一実施例を図面により説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第2図は本発明の一実施例によるハーフブリッジ形イン
バータ回路を示す図である。なお、全図を通じて同一符
号は同一対象物を示す。また各種信号波形は、第4図に
示す通りとする。
FIG. 2 is a diagram showing a half-bridge inverter circuit according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. Further, various signal waveforms are as shown in FIG.

第2図においては、ダイオード17および18が、制御
手段300として設けられている。
In FIG. 2, diodes 17 and 18 are provided as control means 300.

第2図において、入力端子10に第4図に示す如き導通
信号d、(第4図参照)を入力すると、トランジスタ1
1および4が導通信号d1に同期して導通状態となり、
前述と同様に変成器1の1次捲線2に断続電流エア、が
流れる。
In FIG. 2, when a conductive signal d, as shown in FIG. 4 (see FIG. 4) is input to the input terminal 10, the transistor 1
1 and 4 become conductive in synchronization with the conduction signal d1,
Similarly to the above, intermittent current air flows through the primary winding 2 of the transformer 1.

なおトランジスタ11が導通状態となると、トランジス
タ14のベース・エミッタ間電圧は、ダイオード18に
よりトランジスタ11のコレクタ・エミッタ間電圧にク
ランプされる。かかる状態で、擾乱信号dXが入力端子
13から入力されても、トランジスタ14は導通状態に
設定されることは阻止される。従ってトランジスタ4が
導通状態に設定された状態で、更にトランジスタ6が導
通状態となることは無い。
Note that when the transistor 11 becomes conductive, the base-emitter voltage of the transistor 14 is clamped to the collector-emitter voltage of the transistor 11 by the diode 18. In this state, even if the disturbance signal dX is input from the input terminal 13, the transistor 14 is prevented from being set to a conductive state. Therefore, in a state where transistor 4 is set to be conductive, transistor 6 will not be further rendered conductive.

同様に、導通信号d2が入力端子13に入力され、トラ
ンジスタ14が導通状態となった場合にも、前述と同様
にトランジスタ11のベース・エミッタ間電圧が、ダイ
オード17によりトランジスタ14のコレクタ・エミッ
タ間電圧にクランプされ、擾乱信号dXが入力端子10
から入力されても、トランジスタ11は導通状態に設定
されることは阻止され、トランジスタ6が導通状態に設
定された状態で、更にトランジスタ4が導通状態となる
ことは無い。
Similarly, when the conduction signal d2 is input to the input terminal 13 and the transistor 14 becomes conductive, the voltage between the base and emitter of the transistor 11 is changed by the diode 17 between the collector and emitter of the transistor 14, as described above. The disturbance signal dX is clamped to the voltage at the input terminal 10.
Even if an input signal is input from , transistor 11 is prevented from being set to a conductive state, and in a state where transistor 6 is set to a conductive state, transistor 4 is not further set to a conductive state.

以上の説明から明らかな如く、本実施例によれば、導通
信号d、またはd2が入力され、トランジスタ4または
6が導通状態に設定されている状態で擾乱信号dXが重
畳された場合にも、トランジスタ6または4が導通状態
となることは防止され、トランジスタ4および6の破損
等の事故が発生することが防止される。
As is clear from the above description, according to this embodiment, even when the conductive signal d or d2 is input and the disturbance signal dX is superimposed with the transistor 4 or 6 set to the conductive state, Transistors 6 or 4 are prevented from becoming conductive, and accidents such as damage to transistors 4 and 6 are prevented from occurring.

なお、第2図はあく迄本発明の一実施例に過ぎず、例え
ば本発明の対象となるインバータ回路はハーフブリッジ
形に限定されることは無く、フルブリッジ形の場合にも
本発明の効果は変わらない。
Note that FIG. 2 is only one embodiment of the present invention, and for example, the inverter circuit to which the present invention is applied is not limited to a half-bridge type, and the effects of the present invention can be obtained even in the case of a full-bridge type. remains unchanged.

〔発明の効果〕〔Effect of the invention〕

以上、本発明によれば、前記インバータ回路において、
開閉素子が同時に導通状態となることが防止され、開閉
素子の破損し、直流電源に設けられているヒユーズの溶
断、或いはブレーカの遮断等の事故が防止され、当該イ
ンバータ回路の信頼性が向上する。
As described above, according to the present invention, in the inverter circuit,
Switching and closing elements are prevented from becoming conductive at the same time, and accidents such as damage to switching elements, blowing of fuses provided in the DC power supply, or tripping of breakers are prevented, and the reliability of the inverter circuit is improved. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理を示す図、第2図は本発明の一実
施例によるハーフブリッジ形インバータ回路を示す図、
第3図は従来あるハーフブリッジ形インバータ回路の一
例を示す図であり、第4図は第3図における各種信号波
形を例示する図である。
FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a half-bridge type inverter circuit according to an embodiment of the present invention,
FIG. 3 is a diagram showing an example of a conventional half-bridge type inverter circuit, and FIG. 4 is a diagram illustrating various signal waveforms in FIG. 3.

Claims (1)

【特許請求の範囲】 変成器(100)の1次捲線(101)に極性の異なる
直流電圧(V_d_1、V_d_2)を、交互に導通状
態となる開閉素子(201、202)を介して印加し、
2次捲線(102)に交流電圧を出力するインバータ回
路において、 一方の前記開閉素子(201/202)を導通状態とす
る信号(d_1/d_2)が入力された場合に、他方の
前記開閉素子(202/201)を導通状態とする信号
(d_2/d_1)を無効とする制御手段(300)を
設けることを特徴とするインバータの保護回路。
[Claims] Direct current voltages (V_d_1, V_d_2) with different polarities are applied to the primary winding (101) of the transformer (100) via switching elements (201, 202) that are alternately turned on and off,
In an inverter circuit that outputs an alternating current voltage to a secondary winding (102), when a signal (d_1/d_2) that makes one of the switching elements (201/202) conductive is input, the other switching element (201/202) becomes conductive. 202/201) is provided with a control means (300) for disabling a signal (d_2/d_1) that turns on a signal (d_2/d_1).
JP60176086A 1985-08-09 1985-08-09 Protective circuit for inverter Pending JPS6237072A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60176086A JPS6237072A (en) 1985-08-09 1985-08-09 Protective circuit for inverter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60176086A JPS6237072A (en) 1985-08-09 1985-08-09 Protective circuit for inverter

Publications (1)

Publication Number Publication Date
JPS6237072A true JPS6237072A (en) 1987-02-18

Family

ID=16007470

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60176086A Pending JPS6237072A (en) 1985-08-09 1985-08-09 Protective circuit for inverter

Country Status (1)

Country Link
JP (1) JPS6237072A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2358295A (en) * 1997-04-30 2001-07-18 Intel Corp DC-to-DC converter
US6417653B1 (en) 1997-04-30 2002-07-09 Intel Corporation DC-to-DC converter

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5561282A (en) * 1978-10-27 1980-05-08 Nippon Soken Inc Separate excitation type inverter circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5561282A (en) * 1978-10-27 1980-05-08 Nippon Soken Inc Separate excitation type inverter circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2358295A (en) * 1997-04-30 2001-07-18 Intel Corp DC-to-DC converter
GB2358295B (en) * 1997-04-30 2001-10-10 Intel Corp DC-to-DC converter
US6417653B1 (en) 1997-04-30 2002-07-09 Intel Corporation DC-to-DC converter

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