JPS6237410B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a data transfer method, and particularly relates to a data transfer method that can be used as needed to operate a central processing unit (CPU).
Removable man-machine interface console device and CPU connected to the CPU main body
Regarding the data transfer method between

(2) Conventional technology and problems Conventional console device and CPU as described above
The data transfer method between the two is shown in FIG. The console device 1 in FIG. 1 includes an operation key group 11,
It has a key operation detection and transfer request sending circuit 12, an automatic display transfer request sending circuit 13, a data transfer circuit 14, and a display circuit 15. Also,
A transfer request reception and contention control circuit 21 and a data transfer circuit 22 are provided on the CPU 2 side. Between the console device 1 and the CPU 2, a periodic transfer request signal line S11, a transfer request signal line S12 based on key operation detection, a transfer response signal line S13, a transfer data line S14, and various system signal lines S15 including a clear signal are connected. be done.

Transfer of key information from the console device to the CPU in FIG. detects the transfer request S12 from the console device 1 to the transfer request reception and contention control circuit 21 of the CPU 2,
After receiving the transfer response S13 from the CPU 2, the transfer operation is started, and when the transfer is completed, the process returns to the idle state. In addition, in the console device of FIG. 1, in order to realize the automatic display function, the automatic display of the console device 1 is configured to start a transfer operation for performing a periodic display operation separately from the above-mentioned transfer operation. The transfer request sending circuit 13 sends a transfer request S1 at a fixed period.
1 is sent to the CPU.

Therefore, when the two transfer requests mentioned above collide, it is necessary to perform conflict control to give priority to one of them. For example, automatic display transfer, which has little effect on CPU operation itself, is interrupted and transfer based on key operation detection is required. There is a problem in that the device becomes larger and the control becomes complicated because means for prioritizing control is provided in the control circuit 21. In addition, since the transfer operation in the conventional method described above is asynchronous based on key operations, the key information sent from the console device is a notification of a change state from on to off or from off to on. be. Therefore, for signals that require constant knowledge of the state of the key (on or off), a single transmission error may have very serious consequences. There is a problem that this increases the number of interface lines between the console device and the CPU.

(3) Purpose of the Invention In view of the problems of the conventional method described above, the main purpose of the present invention is to edit key information in a removable console device into a transfer command and periodically transfer it to and from the CPU. Based on the idea of doing
The object of the present invention is to provide a data transfer method that can simplify transfer control between a CPU and a console device, simplify the circuit configuration accordingly, and minimize the number of interface lines.

(4) Structure of the Invention The present invention provides a removable man-machine device connected to a central processing unit (CPU) to display the internal state of the CPU and provide operational information to the CPU. During data transfer between the interface console device and the CPU, display target register selection information in the CPU is checked at regular intervals in order to automatically perform display operations.
A transfer control circuit for executing an automatic display function capable of transmitting display data to and from the CPU at the same time is shared for transmitting key operation information on the console device.
A transfer command is generated by converting the key operation information on the console device into a binary number, including the selection information of the display target register in the CPU, and the transfer command is serially transferred to the CPU at regular intervals. There is provided a data transfer method characterized in that return data in response to the transfer command transferred to the CPU in a period can be serially transferred from the CPU.

(5) Embodiment of the invention A console device as an embodiment of the invention
Figure 2 shows the data transfer method with the CPU.
As shown in FIGS. 3 and 4. In the device shown in FIG. 2, the console device 3 consists of an operation panel equipped with a group of operation keys 31 and a display circuit 34, a periodic transfer request sending circuit 32, and a data transfer circuit 33, and includes an interface section 4 of the CPU. consists of a transfer request receiving circuit 41 and a data transfer circuit 42. Between the console device 3 and the CPU 4, a periodic transfer request S21 and a transfer response S2 are sent.
2. Transfer data line S23 and control/clear line S24 are connected.

FIG. 3 shows a transfer circuit 33 on the console device side.
An example of the configuration is shown. The transfer circuit 33 in FIG.
Command mode creation circuit 331, selection circuit 33
2, a shift register 333, a command/mode analysis circuit 334, and a timing circuit 335. Also, Figure 4 shows the transfer circuit 4 on the CPU side.
Two configuration examples are shown. Transfer circuit 42 in FIG.
are a command mode creation circuit 421, a shift register 422, and a command mode analysis circuit 42.
3. Data and system control signal distribution circuit 42
4 and a timing circuit 425.
In FIG. 4, 43 represents a circuit inside the CPU.

The operation of the transfer circuit 33 shown in FIG. 3 will be explained. Each circuit configuring the transfer circuit 33 is a timing circuit 33.
It is controlled to operate at a constant cycle by a timing signal from 5. First, the operation key state information S25 is transmitted to the command mode creation circuit 331.
Identified by That is, the display key is pressed, the store key is pressed, and no operation is performed, and the respective states are called R mode, W mode, and NOP mode. The automatic display function in the conventional manner can be realized in MOP mode operation. Based on the above identification, 2 to 1
The selection circuit 332 selects information S26 of various system keys (keys for CPU start/stop, etc.) in R and NOP modes, and selects information S27 of data keys on the panel (which become write data) in W mode. do. Next, the mode value from the command mode creation circuit 331, the output value of the 2-to-1 selection circuit 332, and key operation instruction information as required, such as the name of the register to be written or read, are compiled into a command format and sent to the shift register 333. Store. An example of such a command format is the fifth command format.
This is shown in Figures 1 and 2.

The above series of operations is performed immediately before the transfer request S21 is sent, and after the shift register 333 is set, the transfer request S21 is sent to the CPU side. The timing circuit 335 activates the transfer request sending circuit 32 at regular intervals and sends the transfer request S21 to the CPU.
While the transfer response S22 is being returned from the CPU 4, the transfer clock is supplied to the shift register 333. Thereby, the transfer command stored in the shift register 333 is sent to the CPU through one of the transfer data lines S23. In addition, in parallel with this transfer, the other transfer data line S
23, serial data from the CPU is stored in the shift register 333. When the transfer response S22 from the CPU is turned off, the command analysis circuit 334 analyzes the received data. The received data is also in the same command format as the transmitted data, and the command analysis circuit 334
The controller determines the operation within the console device based on this and sends out necessary control signals. for example,
When the data from the CPU is panel display instruction data, this operation is called D mode (FIG. 5, 2). In this mode, shift register 3
Panel display circuit 34 corresponding to 33 content bits
The flip-flops inside are set, and a display is made by lighting a panel display lamp or the like.

Next, the operation of the CPU side transfer circuit 42 shown in FIG. 4 will be explained. Incidentally, a schematic situation of data transfer between the console device and the CPU is shown in FIG.
Further, the states of the shift registers of the console device and the CPU during data transfer are shown in FIG. 7, and a time chart of signals related to data transfer is shown in FIG. 8.

Each circuit configuring the transfer circuit 42 on the CPU side is
It operates at the cycle in which a transfer request S21 is sent from the console device 3. When a signal is sent to the transfer request receiving circuit 41, the timing circuit 425 is activated. In the timing circuit 425,
The transfer response sending circuit is activated to send out the transfer response S22 and at the same time supplies a shift clock to the shift register 422. As a result, data is transferred between the console device and the shift register of the CPU as described above. When the predetermined number of transfer bits have been transferred, the timing circuit 425 issues a signal cut-off instruction to the built-in transfer response transmitting circuit and stops the shift clock. Data transfer between the shift registers on the console side and the CPU side is performed via buffers 1 and 2 as shown in FIGS. 7 and 8.

The data received on the CPU side is in the command format as described above, and the data is received by the command analysis circuit 4.
23 identifies R, W, and NOP modes, and based on the result, data or control signals are transmitted from the data system control signal distribution circuit 424.
It is sent to the CPU internal 43. In the R and NOP modes, the CPU internal 43 reads read data according to the read target register name or memory address. Also, according to the system key information
Control operations within the CPU are performed. The read data is
The CPU sets this in the shift register 422 as a D mode command. In the case of W mode, the CPU performs a write operation according to the write target register name or memory address. Further, in order to display the written data on the panel again, the command mode creation circuit 421 automatically changes only the mode to the D mode. The transfer of commands in the shift register 422 set in this way is as follows:
This is performed when the next transfer request from the console device 3 arrives.

The manner in which commands are exchanged between the console and the CPU described above will be summarized with reference to FIG. first,
A register is selected (1) and a display key is pressed (2). When the transfer cycle comes, an R mode command is set in the shift register 333,
Transferred to CPU4. Next, the received data from the CPU is displayed (3) and the register is accessed (4) according to the command sent to the CPU, and the read data is transferred to the shift register 422 of the CPU in D mode by the next transfer cycle. Set. This read data is displayed (7) in the next transfer operation, and at the same time new key operation (6, 7) information is sent to the CPU. Thereafter, such operations are repeated.

Note that the transfer request sending cycle on the console device 3 side is required to be longer than the internal access time in the CPU 4, and it is required to be short enough that human key operations are not accepted more than once within the cycle time.

In the data transfer method shown in Figure 2,
Only the control/clear line S24 is connected by an individual line in order to clear the entire CPU including the transfer circuit 42, but signals such as start, stop, and address stop instructions, which were connected by individual lines in the conventional system, There is no need for a separate line since the line can periodically notify the CPU of its status (on or off). Furthermore, if the system signal has a large number of bits, it is possible to divide it into multiple parts and transfer it to the CPU depending on the command format.

In the above embodiment, the console device is provided with a transfer request sending circuit, but it is of course possible to provide a transfer request sending circuit including a cycle counter on the CPU side.

(6) Effects of the Invention As described above, according to the present invention, in data transfer between the console device and the CPU, a control circuit that realizes an automatic display function is used as a display instead of the asynchronous key operation detection means in the conventional system.・By making it possible to perform only periodic transfer operations by using common keys when pressing keys and store keys, an automatic display function can be easily realized without the need for special dedicated circuits, and the transfer procedure is also uniform. Therefore, the circuit configuration can be simplified. In addition, it is effective as a console device by setting the cycle time to an interval that does not interfere with human operation.
It can also reduce the burden on the CPU. Furthermore,
Regarding various system signals that required connection using individual lines in the conventional method, by accommodating them in commands during periodic transfer, excluding the clear signal, it is possible to eliminate the need for individual lines, and to reduce the need for command transfer in one line. By using bit serial transfer, the number of interface lines can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a data transfer method between a conventional console device and a CPU, and FIG. 2 is a circuit diagram showing a console device and a CPU as an embodiment of the present invention.
Figure 3 is a circuit diagram showing the data transfer method between
Figure 2 is a circuit diagram showing the configuration of the transfer circuit in the console device, Figure 4 is a circuit diagram showing the configuration of the transfer circuit on the CPU side in Figure 2, and Figure 5 is the data transfer method in Figure 2. FIG. 6 is a diagram showing an example of the configuration of a transfer command in the console device of FIG.
FIG. 7 shows the bit configuration of the shift register in FIGS. 3 and 4. FIG. 8 shows the transfer operation in the data transfer method shown in FIG. 2. It is a figure which shows the time chart of. (Explanation of symbols), 1...Console device, 11
... Operation key group, 12 ... Key operation detection and transfer request sending circuit, 13 ... Transfer request circuit for automatic display, 14 ... Data transfer circuit, 15 ...
... Display circuit, 2 ... CPU, 21 ... Transfer request reception and contention control circuit, 22 ... Data transfer circuit, 3 ... Console device, 31 ... Operation key group, 32 ... Periodic transfer request sending circuit , 33...
Data transfer circuit, 34... Display circuit, 331...
Command code creation circuit, 332... Selection circuit, 333... Shift register, 334... Command mode analysis circuit, 335... Timing circuit, 4... CPU, 41... Transfer request receiving circuit,
42...Data transfer circuit, 421...Command/
Mode creation circuit, 422...shift register, 4
23... Command mode analysis circuit, 424...
Data and system control signal distribution circuit, 425
...timing circuit.

Claims (1)

[Claims] 1. A removable man-machine interface connected to a central processing unit to display the internal state of the central processing unit and to provide operational information to the central processing unit. In data transfer between the console device and the central processing unit, display target register selection information in the central processing unit is transferred to the central processing unit at regular intervals in order to automatically perform display operations. A transfer control circuit for executing an automatic display function capable of returning display data from the processing unit is shared for transferring key operation information on the console device, and the display target register in the central processing unit is 2 key operation information on the console device including selection information.
Generates a transfer command converted into a digital number, serially transfers the transfer command to the central processing unit at regular intervals, and at the same time sends return data for the transfer command transferred to the central processing unit in the previous cycle to the central processing unit. A data transfer method characterized by enabling serial transfer from a processing device.