JPS6237542B2 - - Google Patents
Info
- Publication number
- JPS6237542B2 JPS6237542B2 JP6907877A JP6907877A JPS6237542B2 JP S6237542 B2 JPS6237542 B2 JP S6237542B2 JP 6907877 A JP6907877 A JP 6907877A JP 6907877 A JP6907877 A JP 6907877A JP S6237542 B2 JPS6237542 B2 JP S6237542B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- diffusion layer
- type diffusion
- semiconductor substrate
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 40
- 238000009792 diffusion process Methods 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 31
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 5
- 230000005669 field effect Effects 0.000 description 27
- 239000012535 impurity Substances 0.000 description 11
- 238000007796 conventional method Methods 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000001947 vapour-phase growth Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Description
本発明は半導体装置の製造方法に関し、特に電
界効果半導体装置の製造方法に関するものであ
る。一般に電界効果半導体装置は、Ｎチヤンネル
型、Ｐチヤンネル型、及び前者両者を組み合せて
成る相補型の三種類となる。Ｎチヤンネル型電界
効果半導体装置はＰ型半導体基板を用いソース及
びドレインはＮ型拡散層によつて形成される。ま
た、チヤンネルストツパーは半導体基板と同一の
型の拡散層、即ちＮチヤンネル電界効果半導体装
置ではＰ型拡散層によつて形成される。
以下、従来からのＮチヤンネル型電界効果半導
体装置の製造方法を図面を参照して詳細に説明す
る。第１図を参照すると、まずＰ型半導体基板１
に加熱酸化、又は気相成長によつて基板の表面、
裏面に絶縁層２を形成し(a)、続いて、絶縁層２に
選択的に第１の開孔を行い、チヤンネルストツパ
ーとなりうるＰ型不純物を半導体基板１内に拡散
させ、Ｐ型拡散層３を形成する。この表面の開孔
形成のエツチングの際、裏面の絶縁層２は全面除
去される。続いて加熱酸化又は気相成長にて絶縁
層２′を基板の表面・裏面に形成する(b)。次に絶
縁層２′に選択的に、第２の開孔を行う。このと
き裏面の絶縁層２′は全面除去される(c)。次にＮ
チヤンネル型電界効果トランジスタのソース及び
ドレインとなりうるＮ型不純物を第２開孔内に拡
散される。このとき裏面にもＮ型拡散層４を形成
される。先のチヤンネルストツパー形成時に裏面
に形成されてあつたＰ型領域はそれより高不純物
濃度のＮ型拡散層により補償され、この部分は全
体にＮ型となる。その後加熱酸化又は気相成長に
て絶縁層２″を基板の表面・裏面に形成する(d)。
次に基板表面の絶縁層２″に選択的にＮチヤンネ
ル型電界効果トランジスタのゲート領域となりう
る第３の開孔５を行う。このとき図に示すように
基板裏面の絶縁層２″は全面除去される(e)。続い
て、加熱酸化または気相成長にてゲート絶縁膜と
なりうる絶縁層６を形成せしめる。このとき図に
示すように同様の膜が基板裏面に形成される(f)。
続いて選択的にＮ型拡散層４上の絶縁層２″に第
４の開孔を行い、続いて、ゲート電極及び配線と
なりうる元素７を真空蒸着法等によつて付着さ
せ、パターン付けを行い(g)、Ｎチヤンネル型電界
効果半導体装置を完成する。
しかしながら上記従来方法によつて製造された
Ｎチヤンネル型電界効果半導体装置に内蔵された
Ｎチヤンネル電界効果トランジスタのゲート絶縁
膜を形成する加熱処理時に、半導体基板裏面に存
在するＮ型拡散層から外方拡散されたＮ型不純物
元素による汚染により、Ｎチヤンネル電界効果ト
ランジスタにおけるスレツシユホルド電圧の値が
低く及び、スレツシユホルド電圧のバラツキが大
きい欠点があつた。この従来方法においてはＮチ
ヤンネル電界効果半導体装置を収率よく得ること
はできない欠点がある。
本発明の目的は、Ｎチヤンネル型の電界効果ト
ランジスタのスレツシユホルド電圧の値を比較的
高く及びスレツシユホルド電圧のバラツキを小さ
くすることが出来る電界効果半導体装置の製造方
法を提供することである。
本発明の特徴は、Ｐ型の半導体基板の裏面にＮ
型のソースおよびドレイン領域を形成すると同時
に該半導体基板の裏面にＮ型拡散層を形成する工
程と、前記半導体基板の表面および裏面に絶縁層
を形成する工程と、前記半導体基板表面の前記ソ
ースおよびドレイン領域間上の前記絶縁層の部分
を除去してその個所の基板表面を露出し、かつ前
記裏面の絶縁層を全面除去し、前記裏面のＮ型拡
散層を露出せしめる工程と、次に露出せる前記Ｎ
型拡散層を除去する工程と、しかる後に前記半導
体基板のソースおよびドレイン領域間の基板表面
個所にゲート絶縁膜を形成する工程とを有する半
導体装置の製造方法にある。
以下図面を参照して本発明を詳細に説明する。
第１図は従来からのＮチヤンネル型電界効果半
導体装置の製造方法を説明したが、本発明の説明
も第１図を使用し、従来からの電界効果半導体装
置の製造方法と異る部分のみを第２図に示した。
第１図ａ乃至同図ｄまでは従来の製造方法と変る
ところがないため説明を省略する。第１図ｅに示
されるＮチヤンネル型電界効果半導体装置の従来
からの製造方法による、Ｎ型拡散層４の表面濃度
に比較して低い表面濃度を有する半導体基板領域
５の開孔後をみると、半導体基板裏面にＮ型拡散
層４が存在していることに対して本発明において
は第２図に示す如く実施例としてＮチヤンネル型
電界効果半導体装置におけるＮチヤンネル型電界
効果トランジスタのゲート絶縁膜形成の為の加熱
処理時に半導体基板裏面に存在するＮ型拡散層を
除去した方法である。その後の加熱処理時にＮ型
拡散層４に比較して低い表面濃度を有する半導体
基板領域５に加熱処理を施してゲート絶縁膜を形
成させても、半導体基板裏面に存在するＮ型拡散
層４からのＮ型不純物元素の外方拡散がＮ型拡散
層４が除去している為に防止できる。またＮ型不
純物元素による汚染が発生しない為第１図ｇに示
される如くＮ型拡散層４上の絶縁層２″に開孔を
行い、ゲート電極及び配線となりうる元素７を真
空蒸着等によつて付着させ、パターン付け行つて
完成される。かかる本発明によるＮチヤンネル型
電回効果半導体装置に内蔵されたＮチヤンネル型
電界効果トランジスタのスレツシユホルド電圧の
値は従来からの製造方法によつて製造されたＮチ
ヤンネル電界効果トランジスタのスレツシユホル
ド電圧に比較して高く、また本発明によるスレツ
シユホルド電圧のバラツキは従来の方法に比較し
て非常に小さいことが判明した。
表１には、従来からの製造方法によつて製造さ
れたＮ型電界効果半導体装置に内蔵されたＮ型電
界効果トランジスタのスレツシユホルド電圧の値
及びスレツシユホルド電圧のバラツキと本発明に
おける製造方法によつて製造された、Ｎ型電界効
果半導体装置に内蔵されたＮ型電界効果トランジ
スタのスレツシユホルド電圧の値及びスレツシユ
ホルド電圧のバラツキとを対比させて示した。
なお表１に示したスレツシユホルド電圧の値と
バキツキの値は各水準20枚のウエハースを各５点
夫々測定した結果であり、Ｐ型半導体基板として
は４×1015cm-3の不純物濃度を有するボロンドー
プのものを用い、ゲード絶縁膜厚1000Å、基板印
加電圧−5VのＮチヤンネル電界効果トランジス
タの結果である。また、スレツシユホルド電圧の
値は夫々、100点の平均値にて示し、スレツシユ
ホルド電圧のバラツキの値としては夫々100点の
標準偏差を用いて表わした。
The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a field effect semiconductor device. Generally, there are three types of field effect semiconductor devices: an N-channel type, a P-channel type, and a complementary type that is a combination of the former. An N-channel field effect semiconductor device uses a P-type semiconductor substrate, and the source and drain are formed by N-type diffusion layers. Further, the channel stopper is formed by a diffusion layer of the same type as the semiconductor substrate, that is, a P-type diffusion layer in an N-channel field effect semiconductor device. Hereinafter, a conventional method for manufacturing an N-channel field effect semiconductor device will be described in detail with reference to the drawings. Referring to FIG. 1, first, a P-type semiconductor substrate 1
surface of the substrate by heating oxidation or vapor phase growth,
An insulating layer 2 is formed on the back surface (a), and then a first hole is selectively formed in the insulating layer 2 to diffuse a P-type impurity that can serve as a channel stopper into the semiconductor substrate 1, thereby forming a P-type diffusion layer. Form layer 3. During etching to form openings on the front surface, the insulating layer 2 on the back surface is completely removed. Subsequently, an insulating layer 2' is formed on the front and back surfaces of the substrate by thermal oxidation or vapor phase growth (b). Next, a second hole is selectively formed in the insulating layer 2'. At this time, the insulating layer 2' on the back surface is completely removed (c). Then N
N-type impurities that can become the source and drain of the channel field effect transistor are diffused into the second opening. At this time, an N-type diffusion layer 4 is also formed on the back surface. The P-type region formed on the back surface during the previous channel stopper formation is compensated by the N-type diffusion layer with a higher impurity concentration, and this portion becomes N-type as a whole. Thereafter, an insulating layer 2'' is formed on the front and back surfaces of the substrate by thermal oxidation or vapor phase growth (d).
Next, a third hole 5 is selectively formed in the insulating layer 2'' on the front surface of the substrate, which can serve as a gate region of an N-channel field effect transistor.At this time, as shown in the figure, the insulating layer 2'' on the back surface of the substrate is completely removed. be (e) Subsequently, an insulating layer 6 that can serve as a gate insulating film is formed by thermal oxidation or vapor phase growth. At this time, a similar film is formed on the back surface of the substrate as shown in the figure (f).
Next, a fourth hole is selectively formed in the insulating layer 2'' on the N-type diffusion layer 4, and then an element 7 that can become a gate electrode and wiring is deposited by vacuum evaporation or the like, and patterned. (g) to complete the N-channel field effect semiconductor device. However, heating is required to form the gate insulating film of the N-channel field effect transistor built into the N-channel field effect semiconductor device manufactured by the above conventional method. During processing, contamination by N-type impurity elements diffused out from the N-type diffusion layer existing on the back surface of the semiconductor substrate causes the threshold voltage value in the N-channel field effect transistor to be low, resulting in large variations in threshold voltage. This conventional method has the disadvantage that it is not possible to obtain an N-channel field effect semiconductor device with a high yield.It is an object of the present invention to increase the threshold voltage of an N-channel field effect transistor to a relatively high value. An object of the present invention is to provide a method for manufacturing a field effect semiconductor device that can reduce variations in the field effect semiconductor device.
forming an N-type diffusion layer on the back surface of the semiconductor substrate at the same time as forming the source and drain regions of the semiconductor substrate; forming an insulating layer on the front and back surfaces of the semiconductor substrate; removing a portion of the insulating layer between the drain regions to expose the surface of the substrate at that location; and removing the entire insulating layer on the back surface to expose the N-type diffusion layer on the back surface; N
A method of manufacturing a semiconductor device includes the steps of removing a type diffusion layer, and then forming a gate insulating film on a surface area of the semiconductor substrate between the source and drain regions. The present invention will be described in detail below with reference to the drawings. Although FIG. 1 explains the conventional method for manufacturing an N-channel field effect semiconductor device, FIG. It is shown in Figure 2.
Since there is no difference from the conventional manufacturing method from FIG. 1a to FIG. 1d, the explanation will be omitted. FIG. 1e shows a semiconductor substrate region 5 having a lower surface concentration than that of the N-type diffusion layer 4 after opening by the conventional manufacturing method of an N-channel field effect semiconductor device. In contrast to the presence of the N-type diffusion layer 4 on the back surface of the semiconductor substrate, in the present invention, as shown in FIG. This is a method in which the N-type diffusion layer present on the back surface of the semiconductor substrate is removed during the heat treatment for formation. Even if the semiconductor substrate region 5 having a lower surface concentration than the N-type diffusion layer 4 is heat-treated to form a gate insulating film during the subsequent heat treatment, the N-type diffusion layer 4 existing on the back surface of the semiconductor substrate Out-diffusion of the N-type impurity element can be prevented because the N-type diffusion layer 4 removes it. In addition, in order to prevent contamination by N-type impurity elements, holes are formed in the insulating layer 2'' on the N-type diffusion layer 4 as shown in Figure 1g, and elements 7, which can become gate electrodes and wiring, are formed by vacuum evaporation or the like. The threshold voltage value of the N-channel field effect transistor incorporated in the N-channel field effect semiconductor device according to the present invention is determined by the conventional manufacturing method. It was found that the threshold voltage is higher than that of an N-channel field effect transistor, and the variation in threshold voltage according to the present invention is very small compared to that of the conventional method. The value of the threshold voltage of the N-type field-effect transistor built in the N-type field-effect semiconductor device manufactured in this manner and the variation in threshold voltage, and the N-type field-effect semiconductor device manufactured by the manufacturing method of the present invention. The values of the threshold voltage of the built-in N-type field effect transistor and the variation of the threshold voltage are shown in comparison.The values of the threshold voltage and the fluctuation value shown in Table 1 are calculated by comparing 20 wafers of each level with 5 These are the results of point-by-point measurements, using a boron-doped P-type semiconductor substrate with an impurity concentration of 4 x 10 15 cm -3 , a gate insulating film thickness of 1000 Å, and an N-channel field effect transistor with an applied substrate voltage of -5 V. These are the results.The threshold voltage values are each expressed as an average value of 100 points, and the threshold voltage dispersion values are expressed using the standard deviation of 100 points.
【表】
表１に示した本発明の方法とは第２図に示され
た如くＮチヤンネル型電界効果半導体装置におけ
るＮチヤンネル型電界効果トランジスタのゲート
絶縁膜形成の為の加熱処理時に、半導体基板裏面
に存在するＮ型拡散層を除去した方法である。表
１を参照するとＮチヤンネル電界効果半導体装置
に内蔵されたＮチヤンネルトランジスタのスレツ
シユホルド電圧の平均値においては従来方法のス
レツシユホルド電圧（Vt）＜本発明のVtとなり、
標準偏差においても従来方法のVt＞本発明のVt
となつた。スレツシユホルド電圧の平均値につい
て考えるとＮ型拡散層から外方拡散するＮ型不純
物元素の影響はＮチヤンネル型電界効果トランジ
スタの値を小さくする方向に作用する為、本発明
がスレツホルド電圧に悪影響を与えるＮ型拡散層
から外方拡散によるＮ型不純物元素の影響をなく
していることが判る。一方、本発明ではスレツシ
ユホルド電圧の標準偏差の値から考えるとＮ型拡
散層から外方拡散するＮ型不純物元素の影響は、
スレツシユホルド電圧の標準偏差の値を大きくす
る方向に作用する為、本発明がスレツシユホルド
電圧に悪影響を与えるＮ型拡散層から外方拡散に
よるＮ型不純物元素の影響をなくしていることが
判る。[Table] What is the method of the present invention shown in Table 1? As shown in FIG. This is a method in which the N-type diffusion layer existing on the back surface is removed. Referring to Table 1, in the average value of the threshold voltage of the N-channel transistor built in the N-channel field effect semiconductor device, the threshold voltage (Vt) of the conventional method is less than the Vt of the present invention.
Also in terms of standard deviation, Vt of the conventional method>Vt of the present invention
It became. Considering the average value of the threshold voltage, the influence of the N-type impurity element diffused outward from the N-type diffusion layer acts in the direction of decreasing the value of the N-channel field effect transistor, so the present invention has a negative effect on the threshold voltage. It can be seen that the influence of the N-type impurity element due to outward diffusion from the N-type diffusion layer is eliminated. On the other hand, in the present invention, considering the value of the standard deviation of the threshold voltage, the influence of the N-type impurity element diffused out from the N-type diffusion layer is
It can be seen that the present invention eliminates the influence of the N-type impurity element due to out-diffusion from the N-type diffusion layer, which adversely affects the threshold voltage, because it acts in the direction of increasing the value of the standard deviation of the threshold voltage.
第１図は従来の製造方法を工程順に示す断面図
であり、第２図は本発明の実施例を示す断面図で
ある。
尚、図において、１はＰ型半導体基板、２，
２′，２″は絶縁層、３はＰ型拡散層、４はＮ型ソ
ース、ドレイン領域およびＮ型拡散層、５はゲー
ト形成領域、６はゲート絶縁膜、７はゲート電極
及び配線、８は絶縁層。
FIG. 1 is a sectional view showing a conventional manufacturing method in the order of steps, and FIG. 2 is a sectional view showing an embodiment of the present invention. In the figure, 1 is a P-type semiconductor substrate, 2,
2', 2'' are insulating layers, 3 is a P-type diffusion layer, 4 is an N-type source, drain region and N-type diffusion layer, 5 is a gate formation region, 6 is a gate insulating film, 7 is a gate electrode and wiring, 8 is an insulating layer.
Claims (1)
びドレイン領域を形成すると同時に該半導体基板
の裏面にＮ型拡散層を形成する工程と、前記半導
体基板の表面および裏面に絶縁層を形成する工程
と、前記半導体基板表面の前記ソースおよびドレ
イン領域間上の前記絶縁層の部分を除去してその
個所の基板表面を露出し、かつ前記裏面の絶縁層
を全面除去し前記裏面のＮ型拡散層を露出せしめ
る工程と、次に露出せる前記Ｎ型拡散層を除去す
る工程と、しかる後に前記半導体基板のソースお
よびドレイン領域間の基板表面個所にゲート絶縁
膜を形成する工程とを有することを特徴とする半
導体装置の製造方法。1. A step of forming an N-type source and drain region on the front surface of a P-type semiconductor substrate and at the same time forming an N-type diffusion layer on the back surface of the semiconductor substrate, and a step of forming an insulating layer on the front and back surfaces of the semiconductor substrate. Then, a portion of the insulating layer on the surface of the semiconductor substrate between the source and drain regions is removed to expose the substrate surface at that location, and the insulating layer on the back surface is completely removed to form an N-type diffusion layer on the back surface. a step of exposing the N-type diffusion layer, a step of removing the exposed N-type diffusion layer, and a step of forming a gate insulating film at a portion of the substrate surface between the source and drain regions of the semiconductor substrate. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6907877A JPS544080A (en) | 1977-06-10 | 1977-06-10 | Method of producing semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6907877A JPS544080A (en) | 1977-06-10 | 1977-06-10 | Method of producing semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS544080A JPS544080A (en) | 1979-01-12 |
| JPS6237542B2 true JPS6237542B2 (en) | 1987-08-13 |
Family
ID=13392181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6907877A Granted JPS544080A (en) | 1977-06-10 | 1977-06-10 | Method of producing semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS544080A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6434362U (en) * | 1987-08-27 | 1989-03-02 |
-
1977
- 1977-06-10 JP JP6907877A patent/JPS544080A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6434362U (en) * | 1987-08-27 | 1989-03-02 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS544080A (en) | 1979-01-12 |
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