JPS623757Y2 - - Google Patents

Description

[Detailed explanation of the idea]

The present invention relates to an electronic timepiece having a buzzer and a buzzer drive circuit, and aims to improve the effects of functions such as a time signal, half tone and quarter tone. Digital watches have become so multi-functional that there are no watches without alarm or chronograph functions. Among these, watches with an alarm function have a buzzer and a buzzer drive circuit, so a time signal function can be easily added. That is,
10 minute counter, 1 minute counter, 10 second counter, 1
When all the data on the second counter reaches 0, a buzzer ON signal is output to the buzzer drive circuit to sound the buzzer and perform the time signal function. Fig. 1 is a circuit diagram of a conventional clock with a time signal function, including 1 second counter 1, 10 second counter 2, 1 minute counter 3, 10 minute counter 4, NOR gates 5 to 8, AND gate 9, D
type flip-flop (hereinafter referred to as D type FF) 1
0, 11, AND gates 12, 13, a transistor 14, and a buzzer 15. The 1-second counter 1 counts the 1-second signal φs and outputs the 10-second signal φ ₁₀ s and a 4-bit BCD code to the NOR gate 5. Similarly, counter 2 divides the 10-second signal by 1/6 and generates the 1-minute signal φm and the 3-bit BCD code.
Output to NOR gate 6. The same applies to counters 3 and 4. A total of 14 inputs to the NOR gate
When all bit data are at low level, that is,
When N hours 00 minutes 00 seconds (N is an integer from 1 to 12)
The outputs of NOR gates 5 to 8 are all high,
The output of AND gate 9 also goes high and lasts only for one second. The output of AND gate 9 is synchronized to 32Hz from the frequency divider circuit by D type FF10, and
Differentiated by type FF11 and AND gate 12,
Synchronized with the rise of the output of gate 9, it becomes a pulse signal with a width of 1/32 second. The pulse signal is AND
The signal is ANDed with the 4096 Hz signal of the alarm drive frequency by the gate 13, and is input to the base of the transistor 14, which causes the buzzer 15 to sound.
Although the time signal function can be achieved using a relatively simple circuit as described above, the main purpose of the present invention is to further enhance the synergistic effect between vision and hearing by achieving the time signal function through display. The present invention will be explained below with reference to Examples. [Embodiment] FIG. 2 is an external view of an electronic timepiece according to an embodiment of the present invention, which includes 7 segment displays 16a to 16c, a dot matrix display 17, and button switches 18 to 2.
1. Consists of a buzzer 22. The electronic timepiece of this embodiment has an alarm and a chronograph function. The button switch 18 is a mode changeover switch, and each time it is pressed, the mode changes cyclically in the order of time mode → chronograph mode → alarm set mode → time correction mode. Button switch 19 is a lamp button. The button switch 20 is a start/stop button in chronograph mode, and a select button in alarm set and time adjustment modes. The button switch 21 is a lap preset button in the chronograph mode, and a set button in the alarm set and time correction modes. Next, the display section will be explained. The 7-segment type displays 16a to 16c sequentially represent hours, minutes, and seconds in time mode, and 1/100 minutes and seconds in chronograph mode.
Indicates seconds, hours and hours in alarm set mode.
Indicates minutes, AM, PM, and in time correction mode,
16a represents hours, 16b represents minutes, and 16c represents seconds except when the time is being adjusted, and AM and PM when the time is being adjusted. The dot matrix display 17 is a double matrix consisting of 16 vertical x 17 horizontal pixels, in which the signal electrodes running in the vertical direction are cut between the 8th and 9th scanning electrodes from the top, and the lead wires of the signal electrodes are taken out at the top and bottom. Using method 1/8
Display is performed using multiplex drive using a duty voltage averaging method. In the normal time mode, a 5.times.7 dot matrix is displayed in two lines, with the date at the top and the day of the week at the bottom (Figure 3-a). In the chronograph mode, a picture of a running person is displayed (Fig. 3-b), and this picture moves in synchronization with the movement of the chronograph counter. That is, when the start button 20 is pressed, the counter starts running and the person starts running, and when the stop button 2 is pressed, the counter starts running and the person starts running.
When you press 0, the counter stops and so does the person. In the lap state, the person continues running and only the data on the 7-segment display 16 stops. In the alarm set mode, the alarm mark shown in Figure 3-c is displayed to indicate the alarm set mode. In time adjustment mode, when adjusting hours, minutes, and seconds,
The three-digit character "SET" is displayed on the top line, indicating that the time is in time correction mode. When correcting the month and date, "SET" is displayed on the bottom row, the two digits from the left on the top row are the month or day, and the right on the top row is "M" for the month and "D" for the day. Is displayed. Figure 3-d is an example of a dot matrix display when the date is corrected for the 15th. When correcting the day of the week, "SET" is displayed in the upper row, and the day of the month is displayed in three alpha digits in the lower row. The above is the display of each normal mode, but the time signal display of the present invention will be explained. No matter which mode the user sets, at N:00:00, a chime sounds and the bell pictures shown in Figures 4-a to 4-d change in sequence on the dot matrix display 17. Is displayed. That is, the gist of the present invention is to improve the effectiveness of the time signal function by giving the user the image of a bell ringing. The circuit of this embodiment will be described in detail below.
FIG. 5 is a circuit block diagram of the electronic timepiece of this embodiment, which includes a standard signal generation circuit 23, a frequency dividing circuit 24, a time counter 25, a chattering prevention circuit 26, a control circuit 27, an alarm setting counter 28, and a chronograph counter 29. , latch circuit 30 for lapping,
Alarm coincidence detection circuit 31, multiplexer 3
2, 7-segment display decoder 33, 7-segment display segment electrode drive circuit 34, 7-segment display common electrode drive circuit 35, dot matrix display signal electrode drive circuit 36, dot matrix display scan electrode drive circuit 37, It is composed of a matrix display pattern generator 38, a booster circuit 39, a battery 40, a buzzer drive circuit 41, a counter 0 detection circuit 42, and a liquid crystal display 43. generated from the standard signal generation circuit 23
The 32768 Hz signal is frequency-divided by the frequency dividing circuit 24 to become a 1 Hz signal, which is input to the time counter 25. The BCD output of the seconds, minutes, hours, etc. counter in the time counter 25 is passed through the multiplexer 32.
The display decoder converts it into a display segment signal,
The signal enters the 7-segment display segment drive circuit 34 and is displayed on a 7-segment display. In the chronograph and alarm set mode, the channels of the multiplexer 32 are switched by the control circuit 27, and data from the chronograph lap latch circuit 30 and alarm setting counter 28 are input to the display decoder 33, and the 7-segment type It is displayed on the display. The dot matrix display is performed by inputting a pattern designated by a code given from the control circuit 27 in each mode to the dot matrix display signal electrode drive circuit 36. At N hours 00 minutes 00 seconds when the time signal sounds, the TSON signal from the counter 0 detection circuit is high.
state and is added to the pattern generator 38. Then, the pattern generator 38 outputs data to the drive circuit 36 for displaying a bell pattern instead of the pattern that had been displayed up to that point. Although the outline of the electronic timepiece of this embodiment is as described above, the pattern generator and its control will be described in detail below. FIG. 6 is a diagram of the pattern generator of the dot matrix section and its control circuit.
47, NOR gates 48a-d, AND gate 49,
Chronograph 1 second counter 50, frequency dividing circuit 51,
10 day counter 52, 1 day counter 53, October counter 54, January counter 55, day counter 56,
Clocked gate groups 57-65, pattern generator ROM address decoders 66a-c, pattern generator ROM memory cells 67a-
c, pattern generator ROM output latch and buffers 68a-c, liquid crystal drive multiplexers 69a-c, multiplexer 70, and clocked gate control circuit 71. Counters 44-47 are part of time counter 25 in FIG. 5, and NOR gates 48a-d and AND gate 49 detect that the outputs of these counters are 0. The output TSON of the gate 49 is only when the outputs of the counter groups 44 to 47 are all 0.
It becomes high level. Here, we briefly describe the operation when TSON=low. Vertical 16 as shown in Figure 7
If the dot matrix area of 17 x horizontal lines is divided into three blocks, what will be displayed in each block in each mode will be as shown in Table 1 below.

[Table] As mentioned above, there are nine display modes, so the codes that specify these are M ₁ to M ₄ . Also,
There are several types of patterns within one display mode. For example, the ``picture of a running person'' in Chronomode is also 5
There are 0 pictures in the b block in time mode.
-9 numbers will be displayed. Therefore, a pattern code is required to specify which pattern. Furthermore, the dot matrix section is driven by a 1/8 duty multiplex drive;
Scanning codes S <sub>1</sub> to <sub>S 3</sub> are required to specify which scanning signal up to 8 is synchronized. 66a to 66c are pattern generators for each block a to c.
It is a ROM address decoder, and scan codes S <sub>1</sub> to S <sub>3</sub> to A <sub>0</sub> to <sub>A 2</sub> , mode codes M <sub>1</sub> to <sub>M 4</sub> to A <sub>3</sub> to <sub>A 6</sub> ,
Pattern codes are entered in A <sub>7</sub> to <sub>A 10</sub> . A <sub>0</sub>
~A <sub>10</sub> is specified, cells equal to the number of signal electrodes of each block 67a to 67c are specified in parallel,
It is latched by latch circuits 8a to 8c. 68a~
The output of c becomes a control signal for multiplexers 69a to 69c, which designates either an ON or OFF signal for the signal electrode, and drives the liquid crystal. This state continues until the next data is latched into 68a-c. The mode codes M <sub>1</sub> to <sub>M 4</sub> are input to the clocked gate control circuit 71, and the clocked gates 57 to 6
5 is carried out to switch the data entering the pattern code. For example, in the time mode, clocked gates 59, 60, and 65 are used to display the day in blocks a and b and the day of the week in block c.
When it is ON, all other clocked gates are turned OFF, the data of the 10-day counter 52 is input to block a, the data of the 1-day counter 53 is input to block b as a pattern code, and the days are displayed in blocks a and b. In block c, the day of the month is displayed using three alphanumeric characters based on the data from the day of the week counter 56. In chronograph mode, clocked gates 57, 63, and 64 are turned on, other clocked gates are turned off, and chronograph 1 is turned on.
The output of the second counter 50 enters each address decoder as a pattern code for blocks a, b, and c.
The picture of a running person moves in synchronization with the counter 50. In other modes, display is similarly performed according to Table 1. The above was the display when TSON was at low level, but when TSON goes to high level, the multiplexer control terminal select becomes high and the B channel becomes
ON, address decoder A <sub>3</sub> to A <sub>6</sub> all
A high level signal is added to indicate time signal mode. In addition, the clocked gate control circuit 7
The control output of 1 is the clocked gate 58, 63,
64 is turned ON and all others are turned OFF. FIG. 8 shows the internal circuit of the clocked gate control circuit 71, including a mode decoder 72, OR gates 73, 77, AND gates 74, 75, 76,
78 and an inverter 79. The mode decoder 72 is a decoder that generates a control signal for a group of clocked gates from a mode code. When TSON is low, it is as if all gates 73 to 78 do not exist, and the clock gate group is controlled by the mode decoder 72 signal. When TSON becomes high, OR gates 73 and 77 are forced to high, AND gates 74, 75, 76, and 78 are forced to be low, and the 2Hz and 2Hz signals of frequency divider circuit 51 are sent to address decoders 66a to 66c as patterns. This is input as a code and the bell shown in FIG. 4 moves in conjunction with the circuit 51. In this example, we used a picture of a bell swinging, but 16×
Any picture is fine as long as it can be expressed using about 17 pixels. For example, as shown in Figures 9-a to 9-d,
It is also possible to create a pattern in which the ``dolls'' appear and dance in sync with the melody. but,
If the melody is long, the current consumption is too large for a time signal, and the user may feel that the melody is noisy if it appears every hour. Therefore,
It can also be set to ring once a day, for example at noon. As described above, by using the present invention, the effect of the time signal function can be increased and a dream-like product can be provided.

[Brief explanation of the drawing]

Figure 1... Conventional sound-only time signal function circuit diagram 1... Second counter, 2... 10 second counter, 3...
...Minute counter, 4...10 minute counter, 5-8...
NOR gate, 9...AND gate, 10, 11...
...D type FF, 12, 13...AND gate, 14...
...transistor, 15...buzzer. Fig. 2... External view of the electronic watch of the example 16a-c... 7 segment type display, 17...
Dot matrix display, 18-21...button switch, 22...buzzer. Figures 3 a to d: An example of the display of the dot matrix section of the electronic watch according to the embodiment. Figures 4 a to d: An example of the dot matrix display at the time of the time signal. Figure 5: An example of the electronic timepiece according to the embodiment. Clock circuit block diagram 23... Standard signal generation circuit, 24... Frequency dividing circuit, 25... Timing counter, 26... Chattering prevention circuit, 27... Control circuit, 28... Alarm setting counter, 29... Chronograph Graph counter, 30... Latch circuit for wrap, 31... Alarm coincidence detection circuit, 32... Multiplexer, 3
3...7 segment type display decoder, 34...7
Segment type display segment drive circuit, 35...
7 segment type display common drive circuit, 36... Dot matrix display signal electrode drive circuit, 37...
...Dot matrix display scanning electrode drive circuit, 3
8... Dot matrix display pattern generator, 39... Boost circuit, 40... Battery, 41...
... Buzzer drive circuit, 42 ... Time signal detection circuit, 43
...display panel. Fig. 6: Dot matrix pattern generator of the electronic watch of the embodiment and its control circuit diagram 44: 1 second counter, 45: 10 second counter, 46: 1 minute counter, 47: 10 minute counter , 48a-d...NOR gate, 49...AND
Gate, 50... Chrono counter, 51... Frequency dividing circuit, 52... 10 day counter, 53... 1 day counter, 54... October decoder, 55... January decoder, 56... Day of the week counter, 57 ~65...Clocked gate, 66a-c...Address decoder, 67a-c...Pattern generator ROM
Cells, 68a-c...ROM output latch circuit and buffer, 69a-c...Dot matrix display signal electrode drive multiplexer, 70...Multiplexer, 71...Clocked gate control circuit. FIG. 7: Diagram of block division of the dot matrix section of the electronic watch of the embodiment. FIG. 8: Internal circuit diagram of the clocked gate control circuit 71 of the embodiment. 72: Mode decoder, 73, 77: OR
Gate, 74, 75, 76, 78...AND gate, 79...Inverter. FIGS. 9a to 9d are diagrams showing examples of other time signal display patterns.

Claims (1)

[Scope of utility model registration request] a standard signal generation circuit, a frequency division circuit that divides the standard signal of the generation circuit, a first time counter that counts the output signal of the frequency division circuit, and a second time counter that counts the output signal of the first time counter. clock counter,
A counter 0 detection circuit that detects when the contents of the first time counter have become all 0, a sound generating means that generates sound upon receiving an output signal of the detection circuit, and an output of the frequency dividing circuit or the second time counter. an address decoder to which a signal is input; gate means for receiving the output signal of the detection circuit and switching the input of the address decoder to the output signal of the frequency dividing circuit; storing data of a display pattern and controlling readout by the address decoder; memory section,
It has a drive circuit and a dot matrix display section for displaying data in the memory section, and at a specific time, the plurality of display patterns are sequentially displayed on the dot matrix display section according to the output signal of the frequency dividing circuit. An electronic clock characterized by a display.