JPS6237776U - - Google Patents
Info
- Publication number
- JPS6237776U JPS6237776U JP12969185U JP12969185U JPS6237776U JP S6237776 U JPS6237776 U JP S6237776U JP 12969185 U JP12969185 U JP 12969185U JP 12969185 U JP12969185 U JP 12969185U JP S6237776 U JPS6237776 U JP S6237776U
- Authority
- JP
- Japan
- Prior art keywords
- output
- counter
- abnormality detection
- holding
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Control Of Electric Motors In General (AREA)
Description
第１図および第２図は本考案の一実施例の要部
構成を示すブロツク図および各部波形図、第３図
は従来例の電動機回転数異常検出回路の要部構成
を示すブロツク図である。
１…パルスジエネレータ（ＰＧ）、５…リレー
、６…パルスカウンタ、７…デイジタル設定器、
８…デイジタルコンパレータ、９…保持回路、１
０…発信器、１１…遅延回路。
1 and 2 are block diagrams and waveform diagrams of each part showing the configuration of the main parts of an embodiment of the present invention, and FIG. 3 is a block diagram showing the structure of the main parts of a conventional motor rotation speed abnormality detection circuit. . 1...Pulse generator (PG), 5...Relay, 6...Pulse counter, 7...Digital setting device,
8...Digital comparator, 9...Holding circuit, 1
0... oscillator, 11... delay circuit.
Claims (1)
一定時間カウントするカウンタと、該カウンタの
デイジタル量出力および予め設定されたデイジタ
ル量を入力とするデイジタルコンパレータと、該
デイジタルコンパレータの出力を一定時間毎に更
新・保持する保持回路とを少なくとも有し、該保
持回路出力を異常検出信号として得るようにした
ことを特徴とする電動機回転数異常検出回路。 A counter that counts pulse inputs with a frequency proportional to the motor rotation speed for a certain period of time, a digital comparator that receives the digital quantity output of the counter and a preset digital quantity as input, and updates the output of the digital comparator at fixed intervals. - A motor rotational speed abnormality detection circuit characterized in that it has at least a holding circuit for holding, and obtains the output of the holding circuit as an abnormality detection signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12969185U JPS6237776U (en) | 1985-08-26 | 1985-08-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12969185U JPS6237776U (en) | 1985-08-26 | 1985-08-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6237776U true JPS6237776U (en) | 1987-03-06 |
Family
ID=31026487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12969185U Pending JPS6237776U (en) | 1985-08-26 | 1985-08-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6237776U (en) |
-
1985
- 1985-08-26 JP JP12969185U patent/JPS6237776U/ja active Pending