JPS6237789B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a keyed electronic musical instrument, and relates to a synthesizer model having a number considerably smaller than the number of tones that the instrument can produce in response to key operations for generating each tone of a scale. The present invention relates to a key assigner for selectively activating Yule.

In particular, this invention provides a method for shifting a key that was in a depressed state to a released state while a pedal such as a loud pedal on a piano (hereinafter referred to as a pedal) is being depressed. The synthesizer model that was producing a specific musical tone corresponding to the pressed key continues to produce that musical tone, and also produces a musical tone corresponding to the same or different key that is newly depressed. If it is necessary to do so, the synthesizer model that was producing a specific musical tone corresponding to the key that has been shifted to the key-released state is stopped, and the synthesizer model immediately returns to the new key-pressed state. The number of synthesizer models that are considerably smaller than the number of musical tones that can be produced by the instrument is further improved for musical performance. In addition, even in the above case where the synthesizer model that is producing a musical tone stops its production and immediately produces the same or different musical tone, To provide a key assigner for an electronic musical instrument that can produce sounds by dividing musical tones.

First, with reference to FIG. 1, the structure and operation of the main parts of a keyed electronic musical instrument including a key assigner, which is the object of the present invention, will be explained.

Upon receiving the key scanning signal supplied from the key assigner 1 through the key scanning signal output line 2, the key scanning circuit 3 supplies a key signal representing the pressed or released state of each key to the key assigner 1 through the key signal input line 4. do. The key assigner 1 inputs each key code representing the pitch name of each key including the pressed key and each address of a number of registers equal to the maximum number of pronunciations in which the key code is stored to the digital-to-analog conversion circuit 5 and The signal is supplied to the multiplexer 6 sequentially and periodically.
The digital-to-analog conversion circuit 5 converts each key code into an analog voltage (hereinafter referred to as key voltage) corresponding to the code, and applies the analog voltage to the multiplexer 6. The multiplexer 6 distributes this key voltage according to each address of the register storing the key code to be converted, and distributes the key voltage to the sampling and holding circuits 7a to 7h whose number is equal to the maximum number of sounds.
to be applied. Therefore, each of the sampling and holding circuits 7a to 7h corresponds fixedly to each of the addresses whose number is equal to the maximum number of sounds of the register provided in the key assigner 1, and the key code stored in each of the addresses is fixed. Holds the key voltage corresponding to . The key voltages are applied to key voltage terminals 9a to 9h of synthesizer models 8a to 8h, which are fixedly connected to the respective sampling and hold circuits 7a to 7h.

On the other hand, when each key code stored in each address of a register provided in the key assigner 1 is output to the digital-to-analog conversion circuit 5, the key represented by each key code is synchronously pressed. A status indicating the status is supplied to another multiplexer 11 via a status supply line 10. The multiplexer 11 also operates in the same manner as the multiplexer 6, and the control terminals 12a to 12h of the synthesizer models 8a to 8h fixedly correspond to the addresses of the registers.
The status is distributed and supplied to. Therefore, when the status indicating the key pressed state and the key code representing the key in the pressed state are stored in the address of the register corresponding to each of the synthesizer models 8a to 8h, the status and the key voltage are stored. are simultaneously supplied to the corresponding synthesizer model, so that the model produces a musical tone corresponding to the key in the pressed state,
A musical tone signal corresponding to each depressed key is obtained at the output terminals 13a to 13h of each synthesizer model module. In this way, the synthesizer model 8, which can selectively generate only one musical tone among the musical tones corresponding to all the keys, generates a specific musical tone in response to a specific key voltage applied to the key voltage input terminal 9. This is called capture. On the other hand, when a synthesizer is modeled to make it possible to produce a new specific musical tone, it is called release. Once a synthesizer model has been captured, it cannot be captured to produce a new specific musical tone unless it is released.

Now, a keyed electronic musical instrument having the above configuration captures a number of synthesizer models that are considerably smaller than the number of musical tones that the instrument can produce, and generates a specific musical tone corresponding to the key that is pressed. Since the sound is to be produced, the logic for determining the order of capture is an issue in order to effectively perform the capture in terms of musical performance.

In other words, the problem is which synthesizer model should be captured in what order for two or more keys that have entered the pressed state.

In particular, how the state of the pedal is related to the above-mentioned acquisition order has a significant influence on the performance operability of the musical instrument.

Generally, a musical tone does not suddenly disappear when a key is released, but gradually attenuates as the release time unique to that musical tone passes. especially,
When the pedal is depressed, the musical tone will continue until a considerably long release time has elapsed. However, keeping a particular synthesizer model in a captured state to produce a particular note for too long limits the number of synthesizer models that can be selected, and eventually This is disadvantageous because it increases the probability that the synthesizer model cannot be captured in order to generate a musical tone corresponding to a key that transitions to a key state. Therefore, if a key that was in the depressed state is shifted to the released state while the pedal is being depressed, the specific musical tone corresponding to the key that was shifted to the released state will not be produced. In addition to making the synthesizer model that was previously used continue to produce that musical tone, it also makes a musical tone that corresponds to the same or a different key that is newly pressed because all the model units other than the synthesizer model are producing sounds. Only when there is no model to be produced, the synthesizer model that was producing a specific musical tone corresponding to the key that has been shifted to the released state is stopped, and the new key is immediately pressed. It is required to generate musical tones for the same or different keys that have entered the key state.

In conventional key assigners of this type, the status indicating the state of the key consists of one bit, with a logic "1" for the pressed state of the key, and a logic "0" for the released state of the key. Therefore, the fact that the synthesizer model is in the capture state is primarily because it is producing a specific musical tone, and until it is released, it cannot be captured because it is producing a different musical tone. That's what it meant.

Therefore, as in the case where the key is shifted to the released state while the pedal is in the depressed state, even though the synthesizer model is currently producing sound, the key is newly shifted to the depressed state. Previous key assigners were unable to meet this need because there was no logical state that could be captured to produce a musical tone corresponding to a given key.

Therefore, in order to meet the above-mentioned request, this invention
A status composed of 2 bits is provided, consisting of a 1-bit main status indicating whether the synthesizer module is in a generating state and a 1-bit sub-status indicating whether the synthesizer module is in a capturing state, Logic "11" is assigned to a state in which a key is continuously pressed and is producing sound, but on the other hand, a state in which the pedal is not depressed and the key is not released. Logic "00" is assigned to the state in which the pedal is depressed, and logic "10" is assigned to the state in which the pedal is depressed and the key is released, and further, A logic "01" is assigned to a newly detected key press state, and each time a key enters a new key press state, a status of this logic "01" is output once, and then the status is Provide a key assigner that converts to "11".

FIG. 2 shows the configuration of the key scanning circuit 3 in FIG. 1. In the figure, A ₀ to A ₇ and B ₀ to B ₇
are signal lines constituting the key scanning signal output line 2 and the key signal input line 4 shown in FIG. 1, respectively, and
The key scanning signal output line _A0 is commonly connected to one end _{of the key switches Sc1 to SG1} included in the key circuit S1. The other end of the key switch is connected to a key signal input line B ₀ through a sneak prevention diode D.
to _B7 . Key scanning signal output line A ₁
are similarly connected in common to one end of each key switch included in the key switch circuit _S2 , and the other ends of the key switches are respectively connected to key signal input lines _B0 to _B7.
are connected sequentially in parallel. Key circuit S ₃ ~
_S8 is also connected in the same way.

Figure 3 shows the key scanning signal output line in Figure 2.
The assignment of signals to A ₀ to A ₇ and key signal input lines B ₀ to B ₇ is shown. In the figure, the horizontal axis is the time axis, and the numbers attached to the axis indicate the time slot numbers. For example, when a key (not shown) for generating the first octave E (hereinafter referred to as _E1 ) is pressed, the key switch S _E1 linked to the key is closed. On the other hand, key scanning signal output line A ₀
Since the key scanning signals shown as a to h in FIG. 3 are applied to the key signal input lines B0 to _A7 , the key switch circuits _S1 to _S8 sequentially time-divisionally operate to send the key signal input lines _B0 to _B7. have the opportunity to give a signal. Therefore, the first
When the key scan signal appearing in the numbered time slot is applied to the key scan signal output line _A0 , it passes through the closed key switch S _E1 and appears on the key signal input line _B4 . In FIG. 3, i indicates that such a key signal is assigned to the first time throttle on the key signal input line _B4 . Similarly, when the key for generating G# ₅ is pressed, the key signal is assigned to the 8th time slot on the key signal input line _B0 , as shown at j in FIG.

FIG. 4A shows the overall structure of a key assigner which is an embodiment of the present invention. In the figure, 21 is a key scanning signal decoder whose output terminals are connected to key scanning signal output lines _A0 to _A7 . 22 is an 8-bit key signal input register, and the input terminals of each stage are connected to key signal input lines _B0 to _B7 . 23 is a processor that performs information processing including information transfer between registers connected to a common input/output bus and calculations. 24,2
5, 26, 27, and 28 are a first register, a second register, a third register, a fourth register, and an output register, respectively, which are connected to the common input/output bus of the processor; The information to be stored is controlled. In addition, in the embodiment shown in the same figure, the first register 24, second register 25, and fourth register 27 are used for transfer, storage, and other processing in units of one word consisting of 8 bits (also referred to as 1 byte). Because this is done, an address is determined for each word to indicate the location where that word is stored. The numbers arranged vertically at the left end of the register indicate addresses, and the numbers arranged horizontally at the upper end indicate the bit positions of each word.

Furthermore, the first register 24 and the second register 25
In , the memory content of each bit position of each word is divided by diagonal lines, and the symbol written in the upper left of this division indicates the pitch name of the key signal to be stored in each bit position, and The code written at the bottom indicates the state of the key corresponding to the key signal. Here, the key pressed state is displayed as a logical "1", and the key released state is displayed as a logical "0".

First, as explained with reference to FIGS. 2 and 3, the 8-bit key signal appearing in the first time slot for each of the key signal input lines _B0 to _B7 is The data is temporarily stored in the input register 22, and then stored at address 0 of the first register 24 via the processor 23. Now, for example,
When the key for producing the tone _E1 is in the depressed state, the fourth bit position at address 0 becomes logic "1" as shown in a in FIG. 4A.
Next, the word at address 0 of the first register 24 and the word at address 0 of the second register 25 are transferred to the processor 23, and the exclusive OR (also called exclusive OR) of the two is calculated. It is stored in the third register 26. The third register 26 is cleared immediately before each key scan. Subsequently, the word at address 0 of the first register is transferred to the second register 25 via the processor 2, and is stored in place of the word at address 0. Furthermore,
Subsequently, in order to store the key signal appearing in the second time slot at address 1 of the first register 24, the contents of an address counter (not shown) in the processor 23 is incremented to a numerical value of "1". .
This numerical value "1" is transferred to the key scanning signal decoder 21, which decodes it and supplies the key scanning signal with the timing shown in b in FIG. 3 to the key scanning signal output line _A1. . Therefore, the 8-bit key signal appearing at the second time throttle is stored in the key signal input register 22, and then stored in address 1 of the first register 24 via the processor 23. Now, for example, if the keys for producing tones G# ₁ and B ₁ are newly pressed, the 4th key is pressed.
In FIG. A, a logic "1" is stored in the bit position of address 1 shown at b and c. Next, by the same operation as described above, the exclusive OR of the word at address 1 of the first register 24 and the word at address 1 of the second register is calculated, and this and the word 0 stored in the third register 26 are obtained. After calculating the logical sum with the word associated with the address and storing it in the third register, the second register 25
The word at address 1 is replaced with the word at address 1 of the first register 24.

By repeating the above process 8 times, the states of 64 keys at the time of key scanning can be stored in the 8-word first register 24, and the address and bit position can be stored for each key. It can be specified according to the name of the musical tone pronounced by the user.

Furthermore, in the second register, the state of each key at the time of the previous key scan is similarly stored in the address and bit position specified in accordance with the name of the musical note produced by the key, and this is stored in the next time. Ready for key scanning.

For example, if the keys for producing musical tones E ₁ , G# ₁ , and B ₁ are continuously pressed, the first key as shown in d, e, and f in FIG. a second register 25 corresponding to the bit position in register 24 where a logic "1" is stored;
A logic "1" is stored in the bit position. Also,
If the state of each key at the time of the current key scan stored in the first register 24 has changed by any one of the states of each key at the time of the previous key scan stored in the second register 25, A logic "1" is stored in the bit position related to the state change in the third register 26, but as described above,
Since only the keys for sounding E ₁ , G# ₁ and B ₁ are continuously pressed, the corresponding words in the first register 24 and the second register 25 are all equal. Therefore, the exclusive OR of each corresponding word becomes "0", and eventually the third
Each bit position of register 26 also becomes a logic "0". By determining the contents stored in the third register 26 in this manner, it is possible to detect the occurrence of a new key press state or key release state.

Now, the first register 24 and the second register 25
As a result of comparing all words of
is not stored, that is, when a new key press state or a new key release state has not occurred,
The output register 28 outputs a key code to be supplied to the digital-to-analog conversion circuit 5 in FIG. 1, and a status to be supplied to the multiplexer 11 through the status supply line 10. Further, the address of the fourth register 27 is supplied from the processor 23 to the multiplexers 6 and 11. Subsequently, the next key scan as described above is performed again, and the key scan and output of the status and key code are repeated in the same manner.

In this embodiment, the 0th bit position of the register 27 in FIG. 4 is assigned to the main status indicating the sound generation state of the synthesizer model, and the sound generation state is represented by a logic "1". Further, the first bit position of the fourth register 27 is assigned to a sub-status that indicates the pressed state of the key, that is, the captured state of the synthesizer model. Represented by a logic "0".

Additionally, the second through seventh bit positions are allocated for storing key codes. The key codes are arranged sequentially in the first register 24 from the 0th bit position of the word stored at address 0 to the 7th bit position of the word stored at address 7.
This is a binary representation of the arrangement order of the 64 note names.

For example, _E1 is the fourth bit position of the first word, so it is "100";G# ₁ is the first bit position of the second word, that is, the eighth bit position, so it is "1000"; and _B1 is Since it is the 11th bit position, it is expressed as "1011".

Now, as mentioned above, if only the keys for producing musical tones E ₁ , G# ₁ and B ₁ are kept in the pressed state, for example, 0 of the fourth register 27
The address indicates the sound of the synthesizer model, the status "11" indicates the capture state, the key code "100" indicates the musical tone of E ₁ , the status "11" indicates the G
# The key code “1000” indicating the musical note ₁ , and the key code “1000” indicating the musical tone 1.
The address stores the status ``11'' and the key code ``1011,'' which indicates the musical tone of B ₁ , and all the statuses are logical ``00'' because they are cleared before operation starts at other addresses. .

These statuses and key codes stored in the fourth register 27 are processed by the processor 23.
The data from address to address 7 are sequentially transferred via the output register 28 and output. At this time, the contents of the address counter (not shown) of the fourth register provided in the processor 23 are also output. That is, the address of the fourth register 27 where the status and key code transferred to the output register 28 were stored is also output in binary representation.
In this embodiment, since the number of synthesizer models 8 is eight, the fourth register 27 also uses eight addresses.

Now, referring to FIG. 4B, as mentioned above, when only the keys for producing musical tones E ₁ , G# ₁ and B ₁ are in the depressed state, as an example, when G The operation when the keys for producing the musical tones # ₁ and _B1 are shifted to the released state, and the key for producing the musical tone _D1 is further shifted to the pressed state.

First, by one key scan as described above,
The updated memory content of the first register 24 is a logic " ₁ " because E1 is continuously pressed, and G# ₁ and _B1 are released, as shown in a to d in FIG. 4B. It becomes logic "0" because it is in the state, and becomes logic "1" because _D1 is newly brought into the key pressed state. On the other hand, the second register 25 stores the state of each key at the time of the previous scan.
As shown in the figure, E ₁ , G# ₁ and B ₁ are in the depressed state, so the logic is "1". Now, the first
Word at address 0 of register 24 and second register 2
5 and the word at address 0 yields "00100000", and it is detected that a state change has occurred at the second bit position to which _D1 is assigned. This is transferred to the third register 26, and a logic "1" is stored in the second bit position of the register as shown in FIG. Next, if the word at address 0 of the second register 25 is replaced with the word at address 0 of the first register 24, the first word of the second register 25 will be placed at the second bit position as shown at d' in the figure. becomes logical "1". Similarly, the first register 24
The exclusive OR of the word at address 1 of the second register 25 and the word at address 1 of the second register 25 is "10010000".
Therefore, it is detected that a state change has occurred at the 0th and 3rd bit positions to which G# ₁ and _B1 are assigned.
The exclusive OR "10010000" and the second register 2
6 and "00100000" stored by processing the word at address 0 of the first and second registers 24 and 25 is stored in the third register, h,
As shown in i and j, the 0th, 2nd and 3rd bit positions become logic "1". Next, when the word at address 1 of the second register 25 is replaced with the word at address 1 of the first register 24, the result in the same figure is
The bit positions indicated by f' and g' become logic "0".

Such processing is performed by the first and second registers 24,
One or more logical "1"s stored in the third register 26 indicate that a state change has occurred in one or more of all the keys constituting the keyboard by sequentially processing all 25 addresses. can be detected by the presence of

Now, when a change in the state of a key is detected, the processor 23 does not output the status and key code as described above and performs the next key scan, but performs the key release process described below with reference to FIG. Perform processing.

First, in the fourth register 27, a word whose sub-status is logic "1", that is, a word containing a key code indicating a pressed key, is transferred to the processor 23, and the key code is transferred to the first register 24.
Convert to word and bit positions. Such a transformation is referred to as an inverse transformation in this specification.

Up until now, the keys for producing musical tones E ₁ , G# ₁ and B ₁ have been kept pressed, so as mentioned above, the keys for producing the musical tones E 1 , G# 1 and B 1 have been pressed continuously. Key codes indicating E ₁ , G# ₁ , and B _1, respectively, and status "11" indicating key press status
is memorized. Although the operation immediately after the start of operation is described here, as will be described later, there is generally no necessity for the key code and status to be assigned to addresses 0 to 2.

First, when the word at address 0 in the fourth register 27 is inversely converted through the processor 23, the correspondence with the fourth bit position of the word at address 0 in the first register 24 is determined as shown in a in FIG. 5A. be able to. Therefore, if this bit position in the first register is a logic ``1'' as shown in a in the figure, it is erased and a logic ``0'' is written in the bit position as shown in a' in the figure. Make me remember.

Next, when the word at address 1 of the fourth register 27 is inversely transformed to find the correspondence with the 0th bit position of the word at address 1 of the first register 24, a new As a result of key operation, G ₁
Since the key for producing the musical tone is in the released state, a logic "0" is stored in the bit position as shown at b in FIG. 5A. In such a case, the processor 23 outputs the sub-status indicating the key press state in the word at address 1 of the fourth register 27, which includes the key code corresponding to the bit position, as shown in c in FIG. 5A. It is deleted, and a sub-status indicating the key release state, that is, logic "0" is stored instead. Similarly, the fourth register 27
When the key code at the 2nd address of The sub-status of the address is set to logic "0". When such processing is executed for all words whose sub-status is logical "1" in the fourth register 27, a logic value is set in the bit position corresponding to the key that is continuously pressed in the first register 24. ``1'' is stored, and a logical ``0'' is stored in the fourth register 27 as the sub-status indicating the state of the key that has changed from the key-pressed state to the key-released state. Only the logic "1" stored in the bit position of the first register 24 corresponding to the key that is newly depressed remains in the first register 24 after the above processing, as shown in FIG. Therefore, after the above-described processing, the occurrence of a new key press state can be detected by the logic "1" remaining in the first register 24, and the occurrence of a new key press state can be detected. The synthesizer module can be released by setting the sub-status of the fourth register to logic "0".
At this time, even if the sub-status becomes logic "0", the key code in the same word will be replaced by the same or different key code and press in order to capture the synthesizer model corresponding to the address where this word is stored again. It remains until the sub-status indicating the key status is stored at the same address.

Further, a preferred embodiment for the inverse transformation process will be described with reference to FIGS. 5B and 5C.

In FIG. 2B, 29 and 30 are a set of tables, which are also comprised of a read-only storage device.

Now, for example, when inversely converting a key code indicating _E1 stored at address 0 of the fourth register 27, the second to fourth bit positions of the key code are transferred to the processor 23, and the key code is code 3
The address of the first register 24 indicated by the bit, ie, the word stored at address 0, is read out to the processor. Next, the 5th to 7th bit positions of the key code stored at address 0 of the fourth register 27 are transferred to the processor 23, and the code indicated by the 3 bits of the key code, that is, the same as "100" is transferred. The code is found on the table 29, and the corresponding code on the table 30 shown in FIG. 5B is indexed from the code in the table 29 shown in a in FIG. 5B.

Next, as shown in FIG. 5C, when the exclusive OR is calculated between the code shown in b in FIG. 5B and the word at address 0 of the first register 24 that has already been read, Since the opposing fourth bit positions indicated by b are both logic "1",
The bit position becomes logic "0". When this is stored at address 0 of the first register 24, the fourth bit position of the word at address 0 in the first register 24, that is, 0 of the fourth register 27, is stored as shown in FIG.
The bit position assigned to store the state of the key indicated by the key code of the address becomes logic "0". In this way, the storage contents of each bit position of the first register 24' in FIG. 5A are determined.

Next, while referring to FIG.
7, the process of storing the order of occurrence of key release states necessary for assigning to the address corresponding to the oldest released synthesizer model will be explained.

In the figure, 31 is the fifth register and 8
The address of the seventh register 27 consisting of 3 bits is stored in each of the addresses. This register stores the same numerical value as its own address, such as "000" at address 0 and "001" at address 1, before the entire system starts operating. 3
2 is the sixth register, of which the A and B parts are octal counters, and the C part is a binary counter. Before the start of operation, the A and B parts are set to logic "0" ” and a logic “1” is stored in the C section. Further, as explained with reference to FIG. 5A, when the key release process is performed for addresses 1 and 2 of the fourth register 27, first, as shown in a in FIG. It sets the sub-status of address 1 to logic "0" and transfers the binary number "001" indicating the address to the processor 23, and then transfers this to the A section of the sixth register 32 as shown in b in the figure. It is transferred to the address of the fifth register 31 indicated by the content "000", that is, 0, that is, address 0. When this process is completed, 1 is added to the contents of section A of the sixth register 32, as shown in FIG. 32'. Similarly, when the sub-status at address 2 of the fourth register 27 becomes logic "0" as shown in c in FIG. is memorized.

In this way, the address of the fourth register 27 that stores the sub-status indicating the key release state is transferred to the fifth register 31 in the order in which the key release state occurs.
can be memorized. Therefore, the address of the fourth register 27, which stores the key code indicating the key that was released earlier and its sub-status, is stored in the address of the fifth register 31 having a cyclically smaller numerical value.

Note that "addresses with cyclically smaller numerical values" herein include the following cases. For example, if seven synthesizer models are captured with one note left, and two of them are released, the musical tones produced by those two models will be stored at addresses 0 and 1 of the fifth register. The addresses of the fourth register where the key codes corresponding to the key codes are stored are stored, but the address of the fourth register left at address 7 of the fifth register is more important than the model corresponding to the two addresses. The corresponding model is older and released.

That is, even if the address is actually a larger number, it can be understood that it is assigned to a "smaller" address when considering the cyclic address arrangement.

Next, referring to FIG. 6, in FIG. 5A,
A key depression processing means for capturing a synthesizer model by storing a logic "1" indicating the key depression state remaining in the first register 24 in the fourth register 27 as shown in f' will be described.

As shown in a in the figure, the first register 24
In order to detect the logic "1" remaining in the processor 23, the words from address 0 to address 7 are sequentially processed.
Transfer to. For example, by first detecting a logic "1" remaining in the second bit position of the word at address 0,
Create a key code that indicates the note name of the key corresponding to this bit position. For example, the second word of address 0
The bit position corresponds to the pitch name _D1 , and the corresponding key code is "000010". Subsequently, as shown in b in FIG.
, i.e., the content stored at address 3, the address of the fourth register 27 indicated by "011", i.e., the key code "000010" corresponding to the pitch name D ₁ and the pressed key at address 3. The status "11" indicating the state is memorized. At this time, the B part of the sixth register 32 is "011", that is, the number 3, because it has already been set to E ₁ , G# ₁ , and 3 due to the previous operation.
This is because three synthesizer models are being captured in order to produce the three musical tones _B1 .

As explained with reference to FIG. 5D, the content "011" at address 3 of the fifth register 31 is the address of the fourth register 27 that stores the sub-status in which the key was released the earliest, that is, 3. It is equivalent to a street address.

However, since the above explanation relates to the operation immediately after the start of the operation, address 3 of the fifth register 31 simply indicates address 3 of the fourth register 27, but after one cycle of capture and release, The contents of address 3 of the fifth register 31 indicate the address of the fourth register 27 corresponding to the oldest released synthesizer model.

Furthermore, in the operation stage described above, the fourth register 2
The contents from addresses 3 to 7 of 7 correspond to the model modules that have been released in exactly the same way, and the contents of addresses 1 and 2 correspond to the model modules that have been released most recently. Accommodates models that are in a state unsuitable for new acquisition.

Therefore, the key code corresponding to the key that is newly pressed and the key pressed are stored in the address of the fourth register 27 corresponding to the oldest released synthesizer model by the above-mentioned processing means. A status can be assigned to indicate the key state.

Furthermore, each time the above allocation is executed, 1 is added to the contents of the B portion of the sixth register 32, as shown in c in the figure. Therefore, next, the address of the fourth register 27 where the status indicating the key pressed state is to be stored is address 4, which is the second oldest after address 3 and stores the status indicating the key released state.

Next, a means for calculating the number of possible musical tones will be explained with reference to FIG. The number of possible musical tones is the number obtained by subtracting the number of captured synthesizer models from the maximum number of musical tones. The maximum number of musical tones refers to the number of synthesizer models that are equipped.

As explained with reference to FIG. 5D, each time a key release process is executed, 1 is added to the contents of part A of the sixth register 32, and as explained with reference to FIG. , the sixth register 3 every time the key press state is executed.
Add 1 to the contents of part B of 2. Here, for convenience of explanation, the contents of portions A and B of the sixth register 32 are displayed as a bar graph that increases or decreases bit by bit. Now, as shown in FIG. 7A, if all keys are released after four synthesizer models are captured to produce four musical tones, A The content of part A increases, for example, the key release process is executed four times, and the content of part A increases until the seventh
It occupies the position shown at a in Figure A. On the other hand, the contents of part B occupy the position shown in b in the same figure at the time of the previous acquisition, so
There is room for the contents of the section to increase along the arrows in the figure until it completes one cycle, that is, to execute the key press process eight more times. In this state, the contents of each part of the sixth register 32 are as shown in A' of the same figure.

Next, capture is performed sequentially from that state, and the number of executions of key press processing increases, and a carry occurs in part B, which is composed of a counter whose modulus is the maximum number of musical tones.
When the position shown in c in FIG. 7B is reached after completing one cycle, that is, when all the models have been captured, there is no longer any room for key press processing. In order to distinguish this from the state shown in FIG. 7A, when a carry occurs in section B, the contents of section C are inverted. In this state, the contents of each part of the sixth register 32 become as shown in FIG. B'.
This time, on the contrary, when all the keys are released in sequence from that state and a carry has occurred in part A, the contents of part B will be as shown in Figure 7C. As shown, the key press processing can be executed in an increasing manner along the arrow until it completes one cycle. In order to distinguish this state from the state shown in FIG. 7B, when a carry occurs in the contents of section A, the contents of section C are inverted again. In this state, the contents of the sixth register 32 become as shown in C' of the same figure. Since it is impossible for the number of key releases to be greater than the number of key presses in the above operation, the carry in the contents of part B always precedes the carry in the contents of part A.

In the end, a sixth register 32 consisting of a counter that operates as described above is provided, and the value obtained by subtracting the content of part B from the content of part A is multiplied by the content of part C by the maximum number of sounds N. The number of possible musical tones can be calculated by adding . By adopting such a calculation method, compared to other methods, for example, a method that detects and counts when the sub-status of the fourth register 27 is logic "0", it can be calculated in a shorter time. can be processed. The number of possible musical tones is calculated as described above, and this is transferred to a counter (not shown), and each time the assignment of the status indicating the key depression state and the key code related to the key depression state to the fourth register 27 is executed once. Then, 1 is subtracted from the contents of the counter, and when it is detected that the number of possible sounds indicated by the contents of the counter becomes 0, the allocation is stopped. That is, no new acquisitions are made when all synthesizer models have been acquired or have been acquired.

Now, with reference to FIG. 8, processing of the main status and sub-status will be explained. In the figure, 33 is a pedal status signal input register, and 34 is a seventh register for storing the pedal status, each of which is connected to a common input line of the processor 23.

For example, because G# ₁ is currently being pronounced,
The status of the fourth register 27 is at logic "11" as shown at a in FIG. 8A. When the key press processing is completed, first, as shown in b in FIG. Load it into When the pedal is currently depressed and the key corresponding to G# ₁ is released, the key release process described with reference to FIG. 5 is performed for the sub-status, and the fourth register is The status of is forcibly set to logic "10" as shown in c in FIG. 8A. The status shown at c in FIG. 5A referred to to explain the key release process when the pedal is not depressed is logic "00".

Now, when the pedal is in the depressed state as described above, the pedal state signal indicating the depressed state as shown in d in FIG. 8A, logic "1" is input for the pedal state signal. The processor 23 reads this through the register 33, judges this, and immediately displays all the key codes stored in the fourth register 27 and the main/sub status indicating the states of the keys and pedals without performing any state processing on the pedals. It is output from the output register 28.

Regarding the G# ₁ key, which was released while the aforementioned pedal was in the depressed state, the 8th
As shown at c in FIG. A, the main status logic "1" is output, so the corresponding synthesizer model continues to produce sound. However, regarding the key release process described with reference to FIG. 5, since the sub-status is logic "0", it is processed as having already been released. Therefore, the corresponding model is in a state where it can be captured again even though it is currently being sounded.

When the pedal is shifted to the non-depressed state in this state, first, a pedal state signal indicating the non-depressed state is applied to the pedal state signal input register 33, and as shown in e in FIG. Logic "0" is stored as a status indicating that the register is not stepped on. Next, this status is transferred to the processor 23 and judged. If the determination result is that it has not been stepped on as described above, the contents of the seventh register 34 are further determined. In this case, since the logic "1" is stored in the register as described above, the contents of the register are first reset to logic "0" as shown in b' of the same figure, and the contents of the register are reset to the logic "0" as shown in Forcibly change the status ``10'' of the fourth register to ``00'' as shown in . After a similar process is sequentially executed for all addresses of the fourth register 27, the contents of the fourth register are sequentially outputted through the output register 28, and the next key scan is started. If a key state change does not occur in the next key scan, the above-mentioned process is immediately performed without performing key release processing, calculating the number of possible sounds, key press processing, and writing logic "1" to the seventh register. State processing is performed for the pedal. However, due to the state processing for the previous pedal, the seventh
As shown in b' in the same figure, since the contents of the register have been reset to logic "0", the judgment result of the seventh register 34 is reversed, and this time the status of the fourth register 27 changes from "10" to "0". The contents of the seventh register are immediately output one after another without performing the process of converting it to "00". In this way, immediately after processing the key state change, a logic "1" is stored in the seventh register 34, and then the pedal state is determined,
When the pedal is not depressed, the content of the seventh register 34 is further determined, and if the content of the register is logic "1", the content of the register is reset to logic "0" and the By executing the process of converting the status of the fourth register 27, only when the pedal is newly transitioned from the state in which the pedal is depressed to the state in which it is not depressed, all the information in the fourth register 27 can be changed only once. Processing is executed to forcibly change the logical "10" status of the address status to logical "00". Therefore, the number of times the process is performed is kept to the minimum necessary.

Next, when the pedal is not depressed and the key is shifted to the released state, the key release process is executed in the same manner as described above, and then logic "1" is stored in the seventh register. let

Here, the pedal status signal is read into the processor 23 and judged, but unlike the above case where the pedal is in the depressed state, there is no need to wait for the pedal to shift to the non-depressed state. Immediately execute the process for the state in which the pedal is not depressed.

FIG. 8C shows the states of the keys, pedals and synthesizer model.

In the figure, V is the state of the key corresponding to the musical tone G# ₁ , W is the state of the pedal, X is the envelope of the musical tone produced by the synthesizer model corresponding to address 1 of the fourth register 27, and Y is, for example, The state of the key corresponding to the newly pressed musical tone _D1 , Z indicates the name of the musical tone produced by the synthesizer model corresponding to address 1 of the fourth register 27. Also, the horizontal axis is the time axis.

Next, while referring to FIGS. 8B and C,
When the pedal is depressed as shown in a and the key is released as shown in b, there is no other synthesizer model that can be captured. , the operation of capturing a synthesizer model in a sounding state will be described.

In the key press process explained with reference to FIG. 6, the address of the fourth register 27 corresponding to the oldest released synthesizer model is address 3, and the key code of D ₁ and status "11" are assigned here. However, if all other models are in the capture and sound state, b in Figure 8C.
After the key corresponding to G# ₁ is released as shown in FIG.
The key is pressed as shown in c in Figure C.
The key code of D ₁ and status “11” are shown in Figure 8B.
As shown in e, it is assigned to address 1 whose sub status is "0", and the contents of address 1 are
Replaced with D ₁ key code and status "11". That is, the synthesizer model corresponding to address 1 suddenly stops producing the musical tone G# ₁ as shown in f in FIG. 8C, and starts producing the musical tone _D1 as shown in g in the same figure. .

In order to facilitate understanding of the interrelationship of the above operations, an overall flowchart of the key assigner and a flowchart of state processing for the pedals according to the present invention are shown in Tables 1 and 2, respectively.

Next, processing of the main and sub-status will be explained with reference to FIG. Figure 9C shows the state of the key.
The relationship between the main status and the envelope of the musical tone produced by the corresponding synthesizer model is shown.
In the figure, W is the state of the key corresponding to the musical tone G# ₁ , X is the state of the key corresponding to the musical tone _D1 ,
Y is the state of the main status, Z is 1 of the 4th register
The envelope of the musical tone produced by the synthesizer model corresponding to the address is shown. Also, the horizontal axis is the time axis.

Now, as shown in a in Figure 9C, G
# ₁ key is in the depressed state, and the status of logic "10" and the key code of G# ₁ are assigned to address 1 of the 4th register as shown in d in FIG. Even though the corresponding synthesizer model is producing a musical tone of G# ₁ as shown in b, it can be captured to produce the same or a different musical tone as shown in c of the same figure. , and all other models are not in a state where it can be captured, so the key code of musical tone D ₁ corresponding to the key that is newly pressed at address 1, as shown in a in FIG. 9A. will be assigned.

At this time, the key is newly pressed, so as shown in b in FIG. 9A,
A status of "01" is assigned. That is, during the key press process described with reference to FIG. 6, only the sub-status of the word related to the process is changed to logic "1".

Subsequently, the contents of all addresses of the fourth register 27 are sent to the output register 2 via the processor 23.
Output from 8. Therefore, in Figure 9A, c
When outputting the contents of address 1 of the fourth register 27 as shown in FIG. 9C, the status of logic "01", that is, the main status of "0" is once output as shown in d in FIG. 9C.

Next, the status of the fourth register 27 is sequentially determined for all addresses, and the status is set to logic "01".
Converts the status to logical "11". Therefore, the status of address 1 of the fourth register 27 becomes logic "11" as shown at a in FIG. 9B.

Furthermore, the contents of the fourth register 27 after the status conversion are sequentially outputted through the output register 28 for all addresses. Therefore, b in Figure 9B and e in Figure 9C.
As shown in the figure, in order to output the status "11" at address 1 of the fourth register 27,
The synthesizer model corresponding to the address is G# ₁
The sounding of the musical tone D1 is suddenly stopped, and the sounding of the musical tone _D1 is started, as shown at f in FIG. 9C.
At this time, as shown in g in the figure, the fourth register 27
Since the main status output from address 1 changes from logic "0" to logic "1", the synthesizer model uses this state change of the main status to stop sounding a specific musical tone. Therefore, even if the same or a different musical tone starts to be produced immediately, the starting point of the musical tone can be detected. Therefore, even in the above case, it is possible to easily form the envelope of the rising portion of the musical tone corresponding to the newly pressed key as shown in FIG.

If the above processing is not performed, a newly sounded musical tone will be generated as shown by the dotted line i in Figure 9C.
Musical tone G# ₁ where the envelope of D ₁ has stopped sounding
is the same as the envelope that should have continuously.
Such a phenomenon cannot occur with a natural musical instrument such as a piano, and is extremely inconvenient for performance.

In order to facilitate understanding of the interrelationship of the above-mentioned operations, an overall flowchart of the key assigner and a flowchart of the status conversion process according to the invention related to the present invention are shown in Tables 3 and 4, respectively.

Furthermore, it is easy and effective to simultaneously carry out this invention and inventions linked to this invention, and an overall flowchart of such a key assigner is shown in Table 5.

Also, Figure 10 shows the state of the keys, the state of the pedals,
and the mutual assignment relationship with the status of the fourth register. Arrows in the figure indicate the possibility of transition between states. In the same figure, A and B are
These are examples of this invention and an invention linked to this invention, respectively, and C is a case where both inventions are implemented simultaneously.

Note that although a processor is used in the above embodiment, information processing performed using such a processor, such as transfer, calculation of exclusive OR or OR, addition, multiplication, and address modification, etc. It is obvious that the invention can be realized by a known combination of logic circuits such as AND circuits, OR circuits, flip-flops, and shift registers, so it is easy to implement these inventions using these logic circuits.

As described above, according to the present invention, each address of the register of the key assigner to which the key code representing the pitch name of the key in the depressed state is assigned and stored is assigned the main/sub register related to the key code, that is, the key code representing the pitch name of the pressed key. A main status indicating the sound generation state of the musical tone related to the key code and a status corresponding to the address and indicating the capture state of the synthesizer model that controls the sound generation of the musical tone are stored. When the pressed key is released under the condition where the pressed key is released, the forced release means detects this and forcibly changes the settings of both the main and sub statuses related to the key code of the released key to "10". , from then until the pedal is released, when that key or any other key is pressed anew, the key press processing means stores the key code representing the pitch name of the key that was released the earliest, and The key code of the newly pressed key and the main/sub status of "01" are assigned to the address of the register whose sub status is "0" and stored, but at that time, the above settings are forcibly changed. By configuring the address that stores both the main and sub-status of "10" to be the target of key press processing, only if the key is released while the pedal is being depressed, the pedal will no longer be activated. The address of a register that should store the key code of a newly pressed key until it is released, in other words, even if there is no synthesizer model that can be captured to produce the musical note associated with that key code. , the musical tone associated with the newly pressed key can be forcibly generated in the synthesizer model corresponding to the address of the register that stored the key code of the oldest released key. Due to the normal sound prolongation effect of the synthesizer model due to the pressing operation, the probability of keeping each synthesizer model in the sounding state is increased under the condition where the one in the sounding state among multiple synthesizer models is the most radiant. This results in an excellent effect in that the noise level increases, the noise is alleviated, and the utilization rate of the synthesizer model during performance is greatly improved.

At that time, the forcible setting change to the main/sub status "10" by the forced release means is performed only for the released keys detected while the pedal is depressed, and when the pedal is released, the forced Since the default settings are never changed, there are more synthesizer models available than the number of keys that may be pressed at the same time in a normal performance, and the sound of the synthesizer model Even when the pedals are not operated, which poses no danger, the above-mentioned forcible setting changes for both main and sub-status are performed, and as a result, the amount of information processing increases unnecessarily. , has the advantage of effectively preventing information processing, reducing information processing time, and simplifying the device.

Moreover, the key press processing means logically determines the address where the key code of the oldest key that was released is stored, regardless of the amount of attenuation of the musical tone that is actually being produced. Upon detecting a key release while the pedal is being depressed, the forced release means sets both the main and sub registers to "10" to the address where the setting was forcibly changed, and then the key press processing means releases the new key press. Even when assigning and memorizing a key code related to a new key press, it is possible to avoid the inconvenience caused by the attenuation of a musical tone being produced in response to a pedal depression operation, and to assign a key code related to the new key press. Another advantage is that the address to be stored can be reliably determined.

Furthermore, each time the pedal is released, the forced sound stop means detects this and forcibly changes the main and sub-statuses of "10" stored at a predetermined address in the register to "00". By configuring the settings to be changed, the musical tones associated with all keys released while the pedal is being depressed will all enter the release period and stop sounding at the moment the pedal is released, making it a natural musical instrument. It also has the effect of allowing extremely suitable performance expressions like that of a piano.

In addition, the key release processing means resets the main and sub-status to "00", the key press processing means sets the main and sub-status to "01", and the forced release means resets the main and sub-status to "10". When the setting is changed, the forced sound stop means changes the main/sub status to "00", and the output means sequentially reads out the main/sub status from each address of the register along with the corresponding key code and outputs the status. The means of change is
By configuring the system to convert the main/sub status of "01" that was output for one day to "11" in preparation for re-output, the four states that can be expressed by a 2-bit status can be realized by the operation of the configuration of this invention. essential 4
It is allocated to each of the two states without waste, and
These 2-bit main and sub-statuses are output together with the associated key code, and the main status is used as a production command signal for the synthesizer model, and the key code is used as information specifying the pitch of the musical tone produced by the model. , respectively, which not only greatly simplifies the circuit configuration and signal processing for transmitting information between the key assigner and the synthesizer model, but also makes it possible to use the main Since the status is always output as "0" once just before the status changes to "1", the musical tone corresponding to the next pressed key is assigned to the currently producing synthesizer model released by the forced release means. , even if this is to be produced by replacing the musical note that was being produced immediately before, the main status changes from "1" to "0" and then to "1", forming two production command signals. This also has the effect that the musical tone being produced can always be expressed by dividing it into the number of pressed keys.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of the main parts of a keyed electronic musical instrument including a key assigner, which is the object of the present invention. In the same figure, 1...Key assigner, 3...Key scanning circuit, 5
...Digital-analog conversion circuit, 6, 11...
...Multiplexer, 7...Sampling hold circuit, 8...Synthesizer model. FIG. 2 shows the configuration of the key scanning circuit 3 in FIG. 1. In the same figure, A ₀ to _{A 7} ... key scanning signal output lines, B ₀ to B ₇ ...
Key signal input line, _S1 to _S8 ...Key switch circuit. Figure 3 shows the key scanning signal output line in Figure 2.
The assignment of signals to A ₀ to _{A 7} and key signal input lines B ₀ to _{B 7} is shown. 4 to 8A and 8B show the structure of an embodiment of a key assigner according to the present invention. In the figure, 21...key scanning signal decoder, 22...key signal input register, 23...processor, 2
4...First register, 25...Second register, 2
6...Third register, 27...Fourth register, 2
8...Output register, 29,30...Table,
31...5th register, 32...6th register,
33...Pedal status signal input register, 34...
...7th register. FIG. 8C shows temporal changes in the state of the main parts in an embodiment of the key assigner according to the present invention.
In the same figure, the state of the key corresponding to the tone V...G# ₁ , W
...Pedal status, X...Envelope of the musical tone produced by the synthesizer model, Y...Key condition corresponding to the musical tone of _D1 , Z...Pitch name of the musical tone produced by the synthesizer model. FIGS. 9A and 9B show the configuration of an embodiment of a key assigner according to the present invention. FIG. 9C shows temporal changes in the state of the main parts in an embodiment of the key assigner according to the present invention. In the same figure, the state of the key corresponding to the tone W...G# ₁ ,
...D: State of the key corresponding to _{the 1} musical tone, Y: State of the main status, Z: Envelope of the musical sound produced by the synthesizer model. FIG. 10 shows mutual assignment relationships among key states, pedal states, and statuses in each embodiment of the key assigner according to the invention.

Claims (1)

[Claims] 1. The keys for producing each musical tone of the scale are repeatedly and intermittently scanned to detect the pressed or released state of each key, and each detected key pressed or released state is detected. in a key assigner 1 for selectively assigning a number of tones to a number of synthesizer models 8 that are considerably smaller than the number of musical tones that can be produced by an instrument, and activating the models. Key code representing the note name, synthesizer model 8
A register in which a main status indicating the sounding state of the module as "1" and a non-sounding state as "0", and a sub-status indicating the captured state of the module as "1" and the released state as "0" are stored at each address. 27, and key release processing means for resetting both the main and sub-status of the address in which the key code representing the pitch name of the newly detected key in the released state is stored, to "00" among the addresses of the register 27. Among the addresses in the register 27, a key code representing the pitch name of the key that was released the earliest is stored, and a newly detected key code is stored at the address whose sub-status has been reset to "0". a key press processing means that allocates and stores a key code representing the note name of the key in the depressed key state, and sets both the main and sub status of the address to "01"; A forced release means for forcibly changing the settings of both the main and sub-statuses of an address in which a key code representing the pitch name of a newly detected key in a released state while being stepped on is stored to "10"; , forcibly changing the settings of both the main and sub-statuses of "10" at a predetermined address in the register 27 to "00" each time the pedal changes from a state in which the pedal is depressed to a state in which it is not depressed. , output means for outputting the key code and both main and sub-status stored in each address of the register 27 for each address;
It is characterized by having a status conversion means for converting the main and sub status of "01" among the main and sub statuses once output from the output means to the main and sub status of "11" in preparation for outputting again. key assigner.