JPS6237851B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for receiving a reduced carrier wave single sideband signal, and proposes a receiving method that can easily perform AGC on a carrier wave.

Conventionally, one of the reception methods for reduced carrier single sideband signals is
As a first step, the reduced carrier single sideband signal converted to an intermediate frequency by the superheterodyne method is
First, the level of the carrier wave is detected through an ultra-narrow band crystal filter that allows only the carrier wave to pass, and this detection output is used to control the gain of the high frequency stage or intermediate frequency stage (generally automatic gain control =
At the same time, the detected carrier wave is made into a carrier wave with a constant amplitude via an amplitude limiter etc., and this carrier wave with a constant amplitude and a reduced carrier single sideband signal converted to an intermediate frequency are subjected to product detection. A receiving system is being considered that demodulates the signal by adding it to the circuit. However, the problem with this receiving system is that the ultra-narrow band crystal filter for extracting the carrier wave described above is extremely expensive.

One way to solve this problem is to use an amplitude limiter instead of the ultra-narrow band crystal filter mentioned above.
A receiving method can be considered in which a PLL circuit is directly connected to extract the carrier wave, and a product detection circuit demodulates the signal. But in this case
It is very difficult to detect the carrier wave level for AGC, making it difficult to perform AGC. As an improvement to this method, it is possible to detect the envelope of the reduced carrier single sideband signal converted to an intermediate frequency and perform AGC using the DC component contained in the detected output. In this case, the DC component included in the envelope detection output changes depending on the modulation degree as described later, and is preferable.
It is difficult to expect AGC operation.

The present invention solves the above problems and provides good AGC.
This paper proposes a reduced-carrier single-sideband signal reception method that can be operated and implemented at low cost. Two orthogonal synchronous detection circuits are used to perform synchronous detection with the carrier wave and orthogonal detection to perform signal demodulation. Its feature is that it also performs carrier wave level detection for AGC.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram for explaining one embodiment of the present invention.

In FIG. 1, normally, a reduced carrier single sideband signal converted to an intermediate frequency is applied to a first synchronous detection circuit 2 and a second synchronous detection circuit 5 via an input terminal 1.

Now, if the single sine wave signal V(t) having a carrier wave and both sidebands is expressed by the following equation (1), a reduced carrier wave single sideband signal using the upper sideband applied to input terminal 1 is obtained. u(t) is expressed by the following equation (2).

V(t)=(1+m sinω _S t) cosω _C t...(1) u(t)=k cosω _C t+m/2sin(ω _C +ω _S )t......(2) m: modulation degree ω _C : Carrier wave angular frequency ω _S : Signal angular frequency k: Carrier wave reduction index The following equation (3) is shown by decomposing the above equation (2) into orthogonal components, and also shows the amplitude modulation component and phase modulation component. The following equation (4) shows the decomposition into the following.

u(t)=(k+m/2sinω _S t)cosω _C t+m/2cosω _S t sinω _C t ……(3) however The amplitude modulation component shown in equation (4) indicates the detection output obtained by the envelope detector, and it can be seen that the DC detection output changes in accordance with the change in the modulation degree m. This indicates the imperfection when AGC is performed using the envelope detection output as described above.

Now, the colored output obtained from the VCO 4 and the output obtained from the π/2 radian phase shift circuit 6 are further added to the first and second synchronous detection circuits 2 and 5 shown in FIG.

Among these, the output of the first synchronous detection circuit 2 is guided to the output terminal 7 and is added to the above-mentioned VCO 4 via the low pass filter 3. is PLL
Construct a closed loop of types.

Now, if the oscillation frequency of VCO4 is adjusted by changing its bias voltage or the characteristic value of the oscillation element, and the closed loop is in synchronization with the input carrier wave, then the VCO
The output signal P ₁ (t) of No. 4 is expressed by the following equation.

P ₁ (t) = sin (ω _C t + θ) ... (6) where θ: arbitrary phase angle Therefore, P ₁ (t) expressed by this equation (6)
Then, the reduced carrier single sideband signal u(t) expressed by the above equation (2) is applied to the first synchronous detection circuit 2, and the synchronous detection output Q ₁ ( t) is expressed by the following formula. (Consider by removing the carrier wave and its harmonics.) Q ₁ (t) = l ₁ [(k + m / 2 sin ω _S t) sin θ + m / 2 cos θ cos ω _S t] ... (7) However, l ₁ : first synchronous detection Detection Sensitivity of Circuit 2 On the other hand, the output signal P ₂ (t) of the π/2 radian phase shift circuit 6 is expressed by the following equation based on the output signal P ₁ (t) of the VCO 4 expressed by equation 6.

P ₂ (t) = cos (ω _C t + θ) ... (8) Therefore, the output terminal 8 of the second synchronous detection circuit 5
The detected output Q ₂ (t) obtained in is expressed by the following equation. (Again, the carrier wave and its modulated wave components included in the detection output are removed by a simple low-pass filter (not shown), so they will be removed in the following discussion.) Q ₂ (t) = l ₂ [ (k + m/2 sin ω _S t) cos θ - m/2 sin θ cos ω _S t] ...(9) However, l ₂ : Detection sensitivity of the second synchronous detection circuit 5 By the way, in the above equations (7) and (9), θ = 0 Then, Q ₁ (t) and Q ₂ (t) can be simplified as shown in the following equations.

Q ₁ (t)〓 ₌₀ =m/2l ₁ cosω _S t……(10) Q ₂ (t)〓 ₌₀ =kl ₂ +m/2l ₂ sinω _S t……(11) (10), (11 ), when θ=0, only the demodulated signal is obtained at the output terminal 7 of the first synchronous detection circuit 2, and the demodulated signal and the carrier wave are obtained at the output terminal 8 of the second synchronous detection circuit 5. A DC-like signal proportional to the level can be obtained.

As described above, the present invention sets θ=0, operates two synchronous detection circuits to perform orthogonal demodulation, obtains a DC-like signal proportional to the carrier level from one synchronous detection circuit, and uses this DC-like signal effectively. Use it to
It is characterized by AGC operation.

As a concrete means for setting the above-mentioned θ=0, for example, normally, such as controlling the bias voltage of VCO4 or the characteristic value of the oscillation element, etc.
Various phase adjustment means that can be used in PLL circuits may be used.

As is clear from equations (10) and (11), the signal demodulation output is included in both Q ₁ (t) and Q ₂ (t), so it cannot be obtained from either output terminal 7 or 8. You may also use the output provided.

The low-pass filter 3 shown in FIG. 1 is used to remove the demodulated signal component contained in the output of the first synchronous detection circuit 2 and to improve the dynamic response characteristics of the closed loop. , should be designed with considerations similar to those given to low-pass filters included in PLL circuits.

9 in FIG. 1 is the detection output Q ₂ of the synchronous detection circuit 5.
This is a control signal detection circuit that extracts a direct current signal proportional to the carrier wave level as described above.
Specifically, a low-pass filter or the like is used. The output signal of the control signal detection circuit 9 is applied to a controlled block 10 including the first synchronous detection circuit 2, and controls the level of the detected output _Q1 from the synchronous detection circuit 2. This block 10 has the above detection output Q ₁
Any configuration is sufficient as long as the gain of the included amplifier can be controlled (an example is shown in FIG. 2 as a second embodiment), and the detection sensitivity of the synchronous detection circuit 2 can be controlled. This can be realized by various configurations such as those that are made possible.

FIG. 2 shows an embodiment in which the configuration of FIG. 1 is made more concrete. In FIG. 2, blocks and terminals labeled with the same numbers as in FIG. 1 have the same functions as those in FIG. 1, and detailed description thereof will be omitted.

In FIG. 2, the reduced carrier single sideband signal is passed through an input terminal 11 to a voltage controlled variable gain amplifier 12.
, and its output is as in the case of Fig. 1,
It is added to the first and second synchronous detection circuits 2 and 5. A control voltage for the voltage-controlled variable gain amplifier 12 is provided by a low-pass filter 13 that extracts only a DC signal proportional to the carrier level contained in the output signal of the second synchronous detection circuit 5. Therefore, the voltage-controlled variable gain amplifier 12, the second synchronous detection circuit 5, and the low-pass filter 13 constitute a closed-loop AGC circuit.
It goes without saying that the functions of the low-pass filter 13 and a DC amplifier or attenuator may be added as necessary, as in a normal AGC circuit. Further, the first and second synchronous detection circuits 2 and 5 and the voltage-controlled variable gain amplifier 12 shown in FIGS. 1 and 2 can be easily realized by, for example, a double-balanced multiplier circuit, The VCO 4 can also be easily configured, for example, as an LC oscillator or a crystal oscillator using a voltage-controlled variable capacitance diode. Also,
The π/2 radian phase shift circuit 6 can also be realized by various LC type or RC type phase shift circuits, but it should be designed with due consideration to variations in element characteristics, changes over time, temperature characteristics, etc.

FIG. 3 shows a digital signal that performs substantially the same function in place of the above-mentioned π/2 radian phase shift circuit 6, and also operates advantageously with respect to the problems of radial changes and temperature characteristics without adjustment. Figure 3 illustrates another embodiment of the invention using processing means.

Similar to FIG. 2, blocks and terminals labeled with the same numbers as in FIG. 1 have the same functions as those in FIG. 1, and therefore detailed description thereof will be omitted.

In FIG. 3, the oscillation frequency of the VCO 4 is set to 4n (n is any positive integer) times the input carrier wave. This oscillation output is applied to a Johnson type counter 15 via a frequency divider 14 which reduces the frequency to 1/n. A specific example of the configuration of the Johnson type counter 15 is shown in FIG. In FIG. 4, D flip-flops 17, 18 are used and the output from the frequency divider is applied via input terminal 16 to the T inputs of both flip-flops. And output terminals 19, 2
0, an output having a frequency of 1/4 of the frequency of the signal applied to the input terminal 16 and whose phase is shifted relative to each other by π/2 radians is obtained. Since the operation of the Johnson type counter is well known, detailed explanation will be omitted. Therefore, in the configuration of FIG. 3, the two output signals of the Johnson type counter 15 described above are applied to the first and second synchronous detection circuits 2 and 5, respectively.

In the embodiment shown in FIG. 3, a phase-shifted output can be obtained without adjustment, which is advantageous in terms of changes over time and temperature characteristics, and is also suitable for IC implementation.

As detailed above, according to the present invention, it is possible to perform AGC on a reduced carrier wave single sideband signal with a simple configuration, and stably receive and demodulate it.
Since it has a configuration that can be easily integrated into an IC, its industrial value is extremely large.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
FIG. 3 is a configuration diagram showing another embodiment, and FIG. 4 is a configuration diagram showing an example of the configuration of a Johnson type counter. 1...Reduced carrier wave single sideband signal input terminal, 2...
...Synchronous detection circuit, 3...Low pass filter, 4...
...Voltage controlled oscillator, 5... Synchronous detection circuit, 6...
π/2 radian phase shift circuit, 7, 8... demodulation signal output terminal, 9... control signal detection circuit, 10...
...Controlled block, 12...Voltage controlled variable gain amplifier, 13...Low pass filter, 14...1/
n frequency divider, 15...Johnson type counter.

Claims (1)

[Claims] 1. A first synchronous detection circuit, a low-pass filter, and a voltage controlled oscillator are used, and the first synchronous detection circuit has a reduced carrier wave single sideband signal and the same frequency as the reduced carrier wave. A first carrier wave obtained from the voltage controlled oscillator is added, and an output signal obtained from the first synchronous detection circuit is added to the voltage controlled oscillator via the low pass filter to form a closed loop, The phase of the first carrier wave is shifted so that the phase with this first carrier wave is π/
Obtain a second carrier wave different by 2 radians, apply this second carrier wave and the reduced carrier single sideband signal to a second synchronous detection circuit, and include in the output signal of the second synchronous detection circuit. Controlling the output level of the first synchronous detection circuit to be approximately constant using a DC signal proportional to the carrier wave level,
Furthermore, a reduced carrier wave single sideband signal receiving system is characterized in that a demodulated output signal is extracted from the first or second synchronous detection circuit. 2 Set the oscillation frequency of the voltage controlled oscillator to 4n times the input carrier frequency (n is any positive integer), divide the output of this voltage controlled oscillator to 1/n, and then divide it to 1/4 using a Johnson type counter. 2. The reduced carrier single sideband signal receiving system according to claim 1, wherein the first and second carrier waves whose phases are orthogonal to each other are obtained.