JPS6237945A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an excellent minute through hole in the coverage of a second wiring layer, by laminating and arranging first-third masks on a first insulating layer, etching the masks, and thereafter forming a through hole having staircase shaped steps in a self-aligning manner. CONSTITUTION:Through first-third masks 8, 7 and 6, anisotropic etching of the surface part of a first insulating layer 5 is performed, and a through hole pattern 11 is transferred. At this tie time, eaves 9 are provided at the second mask 7. Etching of the insulating layer facing the eaves 9 is started. After the correct etching of the first wiring pattern 11 reaching a first wiring layer 3, a step part 10 is formed around the hole by 20% side etching. Then, the third mask is removed, and a second wiring layer 12 is deposited on the communicating hole having the step part 10. Thus, the excellent minute through hole is obtained in the coverage of the wiring layer 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a technique for forming a contact hole or a through hole formed in an insulator placed between multilayer interconnections.

[Technical background of the invention]

Recent semiconductor devices, especially integrated circuit devices, as typified by VLSI, are trending toward higher performance and higher integration, and this has made it necessary to form fine patterns, and multilayer wiring technology is also important. It has become.

On the other hand, as performance increases, integrated circuit elements are usually equipped with multilayer wiring, but the insulating layers placed between these wiring layers have also undergone various improvements, and are essential for multilayer wiring. The same applies to through hole formation.

It is a well-known fact that, in addition to the isotropic etching technique which has been widely used in the past, an anisotropic etching technique has recently been applied as a technique necessary for forming this through hole. One of them is RI E (Reactive IonEtchi).
ng) method, which is frequently used because of its characteristics of a small amount of side etching during overetching and excellent etching controllability.

By the way, the second method for forming through holes necessary for multilayer wiring is
This will be explained with reference to figures (,) to (e). Semiconductor substrate (2) equipped with functional elements formed by introducing impurities into the semiconductor substrate
0) A silicon oxide layer (21) is provided on the surface by thermal oxidation, and a first wiring layer (22) is formed therein in a predetermined pattern. Of course, this first wiring layer is electrically connected to the functional element through a window opened in the silicon oxide layer (21), and its material is AQ or lI alloy (AIl-) with a thickness of about 1.0 μm. 3i) is usually applied. This first
Plasma CD (Chemical Va) is used in the wiring layer.
Plasma 5 is generated using the Pour Deposition method.
An i3N4 (hereinafter referred to as P-5iN) layer (27) is deposited as shown in FIG. 2(a). Next, the coated surface of the semiconductor substrate (20) is coated with photoresist layers 1 to 1 with a thickness of about 2.0 μm, and the etching speed of the photoresist layer and the P-S j and N layers are the same. Etching is performed under RIE conditions such that the first wiring layer (22) is exposed. This is a so-called etch-back method, and a flat surface with P-5iN arranged between the first wiring patterns can be obtained. A P-3iN layer (23) with a thickness of about 1.0 μm is deposited again on this flat surface, but its cross section is
It is shown in figure (b).

Next, a photoresist pattern (24) is formed by a normal photolithography method, and using this as a mask, P-3iN (23) is etched by an RIE method to form a through hole (25) as shown in FIG. 2(c). is obtained. Furthermore, after removing the photoresist 1 through oxygen ashing method, a second wiring layer (26) having a predetermined pattern and a thickness of about 1.0 μm is formed by ordinary sputtering method and photoetching method as shown in FIG. 2(d).
). This material is the same as the first wiring layer.

[Problems with background technology]

Generally, when a conductive metal is deposited by vacuum evaporation or the like into a window with an opening in an insulating layer formed on the surface of a semiconductor substrate, the thickness of the deposited layer at the bottom becomes significant because it is first deposited on the edge of the opening. It is well known that the smaller the wire becomes, the more likely wire breakage or electromigration will occur. Therefore, when forming this opening, it is essential to provide a taper of 3- to enlarge the diameter on the surface side of the insulator layer, and the taper angle should be set at 45° to 55°.
Ideally, it should be held at 5°.

However, in reality, due to problems such as the selectivity of photoresist to P-SiN, etching speed, and reproducibility of etching conditions, the taper angle is approximately 70° to 80°, as shown in Figure 2 (a).
) The thickness of the second wiring layer in the portion marked with ◯ is only about 15 to 30% of that in the field portion, so that disconnection due to electromigration caused by the operating current as described above is likely to occur.

As mentioned above, the RIE method is applied to make the through holes small and do not require extra space, but P
-5iN, that is, when the interlayer insulating layer has a thickness of 1.0 .mu.m or more, it is necessary to provide a taper, and the photoresist recedes, resulting in large variations in etching dimensions and making it difficult to miniaturize. For example, in an interlayer insulating film with a thickness of 1.0 μm, there will be a variation of about 0.5 μm at 2σ on one side, and a mask of 2 μm
The bottom dimension of the mouth through hole is 3.0μ maximum after etching.
It becomes m mouth. This is shown in FIG. 2(e).

[Purpose of the invention]

The present invention provides a method for manufacturing a semiconductor device having a novel multilayer wiring which overcomes the above-mentioned difficulties, and in particular provides a fine through hole with excellent coverage of the second wiring layer.

[Summary of the invention]

In the present invention, the same R
By applying a mask consisting of a laminate of a material to be etched under IE conditions and a material with high etching selectivity, and further forming a step-like step inside this through hole after etching, a second
We adopted a method to improve the coverage of wiring layers.

[Embodiments of the invention]

The present invention will be explained in detail with reference to FIGS. 1(a) to (e).

A thermal oxidation layer (2) is provided on the surface of a semiconductor substrate (1) having a functional element (not shown) formed by introducing impurities, and a 1.0 μm thick A layer is formed on this layer by a normal sputtering method.
After depositing Q-3i, a first wiring layer (3) having a predetermined pattern is formed by ordinary photolithography and RIE.

Next, a 1.5 μm thick P-
After depositing the 3iN(4) layer, a photoresist is applied, and the surface of the semiconductor substrate (1) is planarized by a resist etch-back method using the RIE method. After removing the photoresist layer, a P-3iN(5) layer is deposited again to a thickness of 1.0 μm to obtain an extremely flat interlayer insulating layer as shown in FIG. 1(a). (5) layer will hereinafter be referred to as a first insulating layer, and the first wiring layer (3) holding this first insulating layer, the semiconductor substrate (1), and the P-3iN layer (
4) (5) are collectively referred to as a support.

Next, a polyimide layer (6) having a high etching selectivity with respect to the first insulating layer is deposited to a thickness of about 0.5 μm, and this layer will be referred to as a third mask hereinafter. Furthermore, a first insulating layer (5
), a P-3iN layer with a thickness of about 0.4 μm was laminated as a second mask (7) that could be etched under the same conditions as the first mask (8), and then a P-3iN layer with a thickness of 1.2 μm was formed as the first mask (8). After depositing an adjacent positive resist layer of approximately
11) and is transferred to the second mask (7) and the third mask (6), the surface portion of the first insulation M (5) is exposed.

Furthermore, RIE method [CFa
/H2=30/10 SCCM, 2. OPa (Pascal: 1torrz13.z Pascal), 600υ]
The surface portion of the first insulating layer (5) is anisotropically etched to transfer the through hole pattern. At this time, the first insulating layer (5) was etched to a thickness of 0.3 μm, and further subjected to highly isotropic 02RIE, conditions 0° = 50SCCM, 25
At the same time as removing the positive resist that is the first mask (8) using Pa, 100I11, the polyimide layer that constitutes the third mask (6) is side-etched by 0.8 μm to form the P-8iN layer that is the second mask (7). A canopy (9) is provided as shown in FIG. 1(C).

Subsequently, RIE, condition CF3/H2=30/IO3
C.C.M.

2. Hisashi (
The first insulating layer (5) facing 9) is etched after the etching of the mask (7) is completed. In this case the second mask (2)
and the first insulating layer (5) are made of the same material.
Etching of the insulating layer (5) is started from a through-hole pattern depth of 0.7 μm. That is, the first insulating layer (5
), a through-hole pattern with a depth of 0.3 μm has already been formed, and when the second mask with a thickness of 0.4 μm is finished etching, the through-hole pattern has a depth of 0.7 μm.
Etching of the first insulating layer (5) located around this through-hole pattern and facing the canopy starts from the time when the etching time reaches m. After just etching to reach the first wiring layer (3), a step (10) was formed around the through hole pattern by 20% side etching. Finally, the third mask (6) is removed, and the through-hole pattern (11) and step part (1) are formed by a known sputtering method.
A 1.0 μm thick A n-3i layer is deposited on 0), and a second wiring layer (12) having a predetermined pattern is completed by ordinary phosphorography and RIE.

In this example, P-5iN was used as the second mask, but it is a material that can slow down the etching speed of the first insulating layer that exists around the through-hole pattern in order to provide a step around the through-hole pattern. It goes without saying that this method can be applied to wirings with more than two layers. That is, it can be obtained by repeating similar steps.

18= Furthermore, in addition to the polyimide applied as a third mask,
A material that can be selectively side-etched with the first insulating layer and the second mask may be used in order to determine the width of the canopy of the through hole without any problem in forming the second mask.

Although the first mask is entirely removed when side-etching the third mask, it is of course possible to remove only the necessary portions around the through holes. If the coverage of the second layer wiring is good, the height difference and width of the canopy are 0.5 each.
It does not have to be 0.8 μm or 0.8 μm, and may be adjusted by adjusting the thickness of the second mask, the etching selectivity of the first insulating layer, and the amount of side etching of the third mask. Although the above-mentioned embodiment exemplifies the formation of through holes, the same process can also be applied to conduction between the semiconductor substrate and the first wiring layer, that is, the formation of contact holes.

〔Effect of the invention〕

The present invention is characterized in that the first to third masks are stacked on the first insulating layer to form a through hole having a step-like step in a self-aligned manner after etching. Therefore, the coverage of the second wiring layer is improved, and as shown in FIG. The resistance to electromigration caused by concentration of operating current is extremely high. Therefore, accidents due to disconnection rarely occur. When forming a through-hole pattern, there is no need to retreat the resist to create a taper, so as shown in FIG. Specifically, the thickness is 1
．． 0 μm insulating film, 0.17 to 0.20 μm at 2σ on one side
Therefore, miniaturization of the through-hole pattern can be easily realized. Furthermore, since a three-layer mask is applied, the photoresist film thickness has been reduced from the conventional 1.5 to 2.5 μm to 0.8 to 1 μm.
．． Since it can be made as thin as 1 μm, a finer through-hole pattern than before can be achieved.

[Brief explanation of drawings]

FIGS. 1(a) to 1(e) are sectional views of each step in an embodiment according to the present invention, and FIGS. 2(a) to 2(e) are sectional views of each step of a conventional method.

Claims (1)

[Claims] A first insulating layer is applied to a support having a flat surface, a first mask made of a different type of insulating layer and a second mask, which can be etched in the same way as the first insulating layer, are stacked thereon. The surface portion of the first insulating layer obtained by transferring it to the laminate is also etched, the first mask is selectively isotropically etched to remove the resist, and the etching step is performed simultaneously or separately. A step is provided on the second mask by a step, and then anisotropic etching is performed on the step to form a step corresponding to the step around the transfer pattern formed on the first insulating layer, and the transferred pattern is A method of manufacturing a semiconductor device, comprising: removing the mask after communicating with the support, and depositing a conductive metal layer in the stepped communication hole.