JPS6238018A - Integrated filter - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an integrated filter with improved filter characteristics in an apparatus for recording and reproducing color video signals such as a VTR.

[Background of the invention]

First, the recording system of the VTR is called "home video technology" (
The explanation is based on the April 1980 Japan Broadcast Publishing Association p94).

FIG. 2 is a block diagram showing a recording signal processing circuit of a VTR. The color video signal input from terminal 1 is AGC
The circuit controls the amplitude. Then, the luminance signal that has passed through the LPF 5 is modulated by the modulation circuit 4, and then passed through the HPF.
5 and is supplied to the adder circuit 11.

On the other hand, the carrier color signal is divided by the BPF 6, and the ACC circuit 7
After the amplitude is controlled by the burst signal amplification circuit 8, only the burst signal is amplified by about 6 dB. This signal is applied to the frequency conversion circuit 9, where the frequency is converted by the carrier signal fc from the BPF 23, and a color signal with a low frequency of 4 of H (fH is the horizontal scanning frequency) is obtained at the output of LPFlo. This signal is mixed with the modulated luminance signal by the adder circuit 11, and is mixed with the modulated luminance signal by the recording amplifier circuit 12. The information is recorded on a magnetic tape (not shown) via the magnetic head 15.

Carrier signal fc is created as follows.

In Figure 2, a voltage controlled oscillator (hereinafter abbreviated as VCO)
191 phase comparison circuit (hereinafter abbreviated as P and C) 18° frequency divider circuit 20 forms an AFC loop, and VCO 19 oscillates at an oscillation frequency 160 times the frequency of the horizontal synchronization signal obtained from the synchronization signal separation circuit 14. are doing. This VCO19
The output of
At the same time as making an H signal, the phase is rotated by 90 degrees for each horizontal scanning period.

On the other hand, VCO17, P, and C16 form an Arc loop,
Frequency 6 synchronized with burst signal (3,58MHz)
．． A 58 MHz signal fs is supplied to the frequency conversion circuit 22.

The 4OfH signal and fs from the frequency dividing circuit 21 are supplied to the frequency conversion circuit 22, which undergoes frequency conversion, selects the sum frequency component by the BPF 25, and generates the carrier signal fc -40.
h + fs is being created. Therefore, if this carrier signal fc = 40fH+fs and the carrier color signal fs from the burst signal amplification circuit 8 are frequency-converted by the frequency conversion circuit 9, and the difference component is selected by LPB"10, 40f.
A color code converted to a low frequency of H is obtained.

Here, the burst signal amplification circuit 8, P, and C16 are pulses obtained by delaying the horizontal synchronization signal g from the synchronization signal separation circuit 14 by the burst gate pulse generation circuit 15 so that the timing almost coincides with the timing of the burst signal. control with it. That is, the burst signal amplification circuit 8 amplifies only the burst signal by 6 dollars, and the P and C16 generate fs that is phase-synchronized with the burst signal.

In this way, the signals recorded on the tape are demodulated into playback video signals by the playback system. The reproduction system is not particularly necessary for explaining the present invention and will therefore be omitted.

Now, the BPF 25 is necessary in order to select only the carrier signal fc −fs +4ojH from the two frequencies fs+40fH and fs −40 frequency-converted by the frequency conversion circuit 22.

To prevent image quality deterioration, fS+4OfH(
4,21MH2) and fs-40k (2,95M)fz
) ratio, and ≧30dB ・・・・・・・・・・・・
... ■l (d: 4.21MHz amplitude + u: 2-95N
it (z amplitude). In order to achieve this, 2.95ME (BP based on the trap characteristics of z)
I am using F.

Portable ■'R, which emphasizes mobility, is small and
Light weight is important. Furthermore, in stationary VTRs whose goal is to reduce set costs, it has become necessary to integrate filters such as BPF.

As a means of achieving this, an integrated arithmetic filter was realized, as shown in the 1981 Conference of the Kansai Branch of Electrical Related Associations, ``Development of a Low-Voltage One-Chip Chroma LSI for VTRs with Built-in Arithmetic Filter'' (Kudo et al., 6 others). has been done.

The contents will be explained below.

FIG. 3 shows a block diagram of the sub-converter arithmetic filter circuit.

Two signals α and α' with a phase difference of 90 degrees from the frequency dividing circuit 21 are input to the multiplier 31 and a multiplier 62, and at the same time, two signals α and α' with a phase difference of 90 degrees from the phase shift circuit 30 are input to the multiplier 31 and the multiplier 62. is input to the multiplier 32. The filter effect is obtained by adding the outputs of the multipliers and the multiplier 32 in a 270 multiplier 66, doubling the desired signal level and setting the interfering signal level to 0.

Expressing this in a formula, the outputs of the multipliers 61 and 32 are as follows.

m, cosω, t*n, cmωlj −' 771
%1 (Q)S (ω, +ω2)t+co! +(ω,-
ω2)t) ・・・・・・・・・・・・・・・・・・
0m2ays (ω, t + −) −n, a
s (ω2 j + 2 ) −2m2'2(μs(ω
, +ω2)t−■(ω1−ωJt) ・・・・・・・・・
... ■Here, ω, -2πx & 58 ω2-2π×629 Horse and rrL2 are the output amplitudes of the phase shift circuit 50, 1 and 2 are the output amplitudes of the frequency dividing circuit 21, and the added output of the amplitude adder 33 is ＋■Formula,■Formula right side＋■
Right side of the equation 1±(m, rL, + m2n ,) cm (ω1+ωz
)t + 工(-1'!--2"2) Saki(ω,-ω2)t
・・・・・・・・・・・・・・・・・・ ■m,
n, M m2n, ・・・・・・・・・・・・・・・
... Since the design is based on ■, the right side of equation ■ is 77L1rL1ct1s(ω1+ω2)t """"
"""' ■The desired signal (d-4, 21MH
Only a single signal component of only z) is obtained.

However, in reality, the desired signal d and the interference (i.
The output signals of 1 and 62 have variations in the amplitude direction and the phase direction, so that the interference signal is not completely canceled, and the 2,95- signal component, which is the interference signal, remains. As a result, the target of Equation 0, 1≧30dB, was sometimes not satisfied.

[Purpose of the invention]

The purpose of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to
The object of the present invention is to provide an integrated filter that can have a sufficient /u ratio.

[Summary of the invention]

An integrated filter that corrects the inherent gain and phase imbalance within the integrated circuit using an external capacitance value.

[Embodiments of the invention]

Examples of the present invention will be described below. First, the causes of d/u deterioration in the conventional integrated filter shown in FIG. 3 will be described. The main cause can be inferred as follows.

(1) Amplitude difference between two signals output from the phase shift circuit 30,
m,”x;m.

(2) The phase difference between the two signals output from the phase shift circuit 30 deviates from 90°.

(3) The amplitude difference between the two signals output from the branch circuit 21,
n,'x,n.

(4) The phase difference between the two signals output from the branch circuit 21 deviates from 90°.

(5) There is a difference between the output levels of multiplier 1 and multiplier 2.

These main causes overlap, eventually resulting in a state in which the interfering signal cannot be completely canceled.

Once the layout of the IC is determined, (1) to (5) become more or less constant values, and as a result, the amount of deterioration '/u also becomes more or less constant values.

The variation between ICs is also the sum of the variations in (1) to (5), and is about 2 to 5 (fB).

That is, when the layout is determined, the sail will vary by only 2 to 3 dB from a constant value. Therefore, by improving the level of this constant value, it becomes possible to satisfy d/u≧30 dB.

FIG. 1 shows an embodiment of the present invention. In Figure 1, the multiplier 6
1, a multiplier 32, and an adder 55 are shown.

The multiplier 61 is shown by a broken line, and the multiplier 32 is symmetrical to this. The adder 33 is implemented by a collector resistor 41. Signals α and α' with a phase difference of 90°, which are output from the frequency dividing circuit 21, are input to 40A and 40B.

A signal α is input to the base of the transistor Q1, and a signal obtained by passing the signal α through an LPF constituted by a resistor 43 and a capacitor [45] is input to the base of the transistor Q2. Similarly, a signal α' is input to the base of the transistor Q3, and a signal obtained by passing the signal α' through an LPF constituted by a resistor 44 and a capacitor i46 is input to the base of the transistor Q4. 6
8 and 59 are input with the phase difference signal 90' from the phase shift circuit 30. Therefore, the multiplier 31 multiplies the signals α and b, and the multiplier 32 multiplies the signals α′
and b' are multiplied. Then, the respective outputs are added by the collector resistor 41.

A signal α is input to the base of the transistor Q1, but
A signal α, which has passed through a resistor 46 and a capacitor 45, is input to the base of the transistor Q2. As a result, high frequency components are differentially input to the bases of transistors Q1 and Q2. That is, the resistance value R1 of the resistor 43
Assuming that the capacitance value of the capacitor 45 is C, the differential input signal is as follows.

Similarly, the bases of transistors Q3 and Q4 have 1, '-
/,'cru. Here, σ is the capacitance value of the external capacitor 46. It will be explained below that by selecting appropriate values for C and C', the inherent gain and phase imbalance caused by the layout can be corrected.

The amount of gain unbalance and the amount of phase unbalance are considered based on the signal α, and α' is a'-a-4, 2, ? when there is a gain and phase difference. (θ+7) ,,,,,,,,
, ■However, 1-4 and θ can be expressed as constants.

In other words, even if unbalance iiA and θ occur, by appropriately selecting C and C' as seen from equations ■ and ■,
It becomes possible to satisfy ■, ■, and ■.

〔Effect of the invention〕

As described above, according to the present invention, by selecting the external capacitance value, variations within the IC can be corrected, and d//+1 can be sufficiently secured.

[Brief explanation of the drawing]

FIG. 1 is a specific circuit diagram of the integrated filter of the present invention, and FIG. 2 is a block diagram showing recording signal processing of a conventional VTR.
FIG. 3 is a diagram showing the principle of a conventional arithmetic filter. 30... Phase shifter, 21... Frequency divider circuit, 31
．． 32... Multiplier, 33... Adder, 45,
46... Capacitor. , l′ ′・ko.

Claims (1)

[Claims] A phase shifter 1 generates two types of signals with an oscillation frequency ω_1 having an amplitude m_1 and an oscillation frequency ω_1 with a phase delay of π/2 and an amplitude m_2, and an oscillation frequency ω_1 with an amplitude n_1 and an oscillation frequency ω_2 with a phase of π/2. A phase shifter 2 that generates two types of signals with a delay and an amplitude n_2, a multiplier 1 and a multiplier 2 that perform multiplication of the outputs of the phase shifter 1 and the phase shifter 2, and the multiplier 1 and the multiplier 2. It consists of an adder 1 that adds the output of the multiplier 2, and the output of the multiplier 1 is m_1cosω.
_1t・n_1cosω_2t is calculated, and the output of multiplier 2 is m_2cos[ω_1t+(π/2)]
・N_2cos[ω_2t+(π/2)] is calculated, and the output of adder 1 is 1/2(m_1n_1+m_
2n_2) cos(ω_1+ω_2)t+1/2(m_
1n_1-m_2n_2) cos(ω_1-ω_2)t
In an integrated circuit that performs operations, m_1n_1=m_
Integration characterized by selecting the capacitance value C1 that determines the amplitude and phase of the input signal of multiplier 1 and the capacitance value C2 that determines the amplitude and phase of the input signal of multiplier 2 so that the relationship 2n_2 holds true. filter.