JPS6238048A - Pcm signal multiplexing system - Google Patents

Abstract

PURPOSE:To decrease a circuit scale and to attain a high circuit integration by attaining an operation separating a high speed signal section and a low speed signal section. CONSTITUTION:A clock extraction circuit 36 at the reception side 3 extracts a high speed clock, which is frequency-divided by a counter 32 to obtain a low speed clock. The low speed clock fL is used to separate a high speed data signal by a demultiplexer 31. A control signal channel detector 33 detects one channel including a frame synchronizing signal among separated signals to check on which order of line in the (n+1) channels a control signal such as a frame synchronizing signal is given. Since the next channel to the detected channel is CH1, a channel sequential switching device 35 is subjected to switching control to connect the output of the demultiplexer 31 to the 1st output line of the output PCM signal line 34.

Description

[Detailed Description of the Invention] [Summary] When multiplexing PCM signals, the frame synchronization signal to be used is transmitted on a control channel, and on the receiving side, the demultiplexed output is rearranged according to the signal detected from the control channel. This is a PCM signal multiplex communication system that controls the

[Industrial Application Field] The present invention is a PCM signal multiplexing method in which PCM signals are multiplexed and transmitted, and on the receiving side, the reception signal is demultiplexed and the order of the multiplexed original signals is rearranged using a frame synchronization signal. Regarding the transmission method.

[Prior Art] FIG. 2 is a diagram schematically showing a conventional PCM signal multiplex communication system. In FIG. 2, l is a transmitting side device, 2 is a signal transmission path, 3 is a receiving side device, 11 is a unit for combining multiple input PCM signal lines, 12 is a frame synchronization signal generator, 13 is a multiplexer, and 14 is a frame synchronization Signal input signal, 3
1 is a demultiplexer, 32 is a counter, 33 is a frame synchronization signal detection device, etc., and 34 is an output PCM signal line.

A frame synchronization signal generated by a frame synchronization signal generator 12 in the transmitting device 1 is time-division multiplexed together with a signal from an input PCM signal line in a multiplexer 13, and transmitted through a signal transmission line 2 formed of, for example, an optical transmission line. The demultiplexer 31 of the receiving device 3 determines whether a frame synchronization signal can be detected for the separated channels. Then, the input signal bits are shifted to position them correctly within the channel from which the frame synchronization signal was taken.

To move the bits in this way, the operation of the counting operation 32 is controlled. When the frame synchronization signal is confirmed several times, it is assumed that frame synchronization has been established, and the reception data of the channel can be retrieved.

[Problems to be solved by the invention] When the transmission speed of PCM signals is not very fast and there are not many, it is possible to use ready-made LSI products for counters, frame signal separation circuits, etc., but when the transmission speed is LM bits/sec. When the speed became so high, it became necessary to assemble individual items of integrated circuits such as gate circuits and flip-flops. At this time, since it is necessary to control the position of the pulse in units of 1 nS as a counter so as to correspond to IM bits/second, it is not possible to obtain a large-scale integrated circuit with good characteristics. Furthermore, since the synchronization process is comprised of a feedbank loop, the delay time of the logic elements that make up the system becomes a problem, resulting in the drawback that the operating speed cannot be sufficiently fast.

In addition, the circuit scale has also increased. Therefore, the purpose of the present invention is to enable separate operation of the high-speed signal section and the low-speed signal section, and to provide a PCM signal multiplex communication system with a circuit configuration using an IC passed through each signal section. There is a particular thing.

[Means for solving the problem] Fig. 1 is a diagram showing the configuration of the present invention, in which 1 is a transmitting side, that is, a PCM signal multiplexing circuit, 2 is a transmission path, and 3 is a receiving side, that is, a PCM signal multiplexing circuit. Separation circuit, 11 is channel c ri
Input PCM signal lines for i to CHn and control signal input are collectively shown, 12 is a frame synchronization signal generator and a control signal generator, 13 is a multiplexer MPX, 14 is an input signal line for frame synchronization signals, etc., and 15 is an input signal line for a frame synchronization signal, etc. 16 is a high-speed clock fn output, 17 is a low-speed clock fL output terminal, 31 is a time division multiplexer DMPX (demultiplexer), 32 is a counter, 33 is a control signal channel detection device, 34 is an output PCM signal line, 35 is a channel order switching device, and 36 is a clock extraction circuit. On the input side to the channel order switching device 35, signals are separated into (n+1) channels, and since the signal lines do not necessarily correspond to the transmission (1 to 1 signal order), one of the output PCM signal lines 34 The rearrangement of the output signal lines of the demultiplexer 31 is controlled so that the uppermost line is the channel CHI.

[Operation] On the transmitting side 1, the high speed clock from the high speed clock rg output 16 is frequency-divided by the counter 15, and the low speed clock ft and the low speed clock f are used to add the channels CHI to CHn and the control signal channel. (n+1) channels are multiplexed by multiplexer 13.

The multiplexed signal is transmitted to the receiving side 3 through the transmission path 2 .

On the reception side 3, a clock extraction circuit 36 extracts a high-speed clock, and a counter 32 divides the frequency to obtain a low-speed clock. The high speed data signal is separated in the demultiplexer 31 using the low speed clock fL. The control signal channel detection device 33 detects one of the channels containing the frame synchronization signal from the separated signals, and determines which line of the (n+1) channels contains the control signal such as the frame synchronization signal. I can fall. Since the channel next to that channel is CHI, the channel order switching device 35 sets the output of the demultiplexer 31 so that it can be connected to the first output line of the output PCM signal line 34.
Switch control.

[Effects of the Invention] As described above, according to the present invention, the counter in the high-speed signal section can perform a frequency division operation using the extracted clock, but the conventional demultiplexer counter needs to perform bit shifting, and therefore cannot operate at high speed. External control of movement was required. After detecting the frame synchronization signal, only switch switching control is performed and the speed is extremely slow. Therefore, since the feedforward operation is used instead of the conventional feedbank operation, the number of circuits that require high-speed operation is reduced, and there are fewer places where the delay time of the logic elements forming the system becomes a problem. Therefore, compared to the conventional circuit, the circuit scale is not large, and high integration is possible, which also has the effect of lower power consumption.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of the present invention, and FIG. 2 is a diagram showing a conventional PCM signal multiplex communication system. ■--Transmission side 2--Transmission line 3-Reception side 11--Manual PCM signal line 12-Frame synchronization signal generator 13-Multiplexer 31-Demultiplexer 32-Counter 33-Control signal channel detection device 35 - Channel order switching device

Claims (1)

[Claims] Time division multiplexing is performed by adding one channel as a control signal channel such as a frame synchronization signal to an n-channel PCM data signal, and the multiplexed signal is transmitted to the receiving side. In the PCM signal multiplexing system, the receiving side includes a time division multiplexing/demultiplexing device (31), a control signal channel detecting device (33), and a channel order switching device (3).
5), and the demultiplexed output is switched by the detection output of the control signal channel detection device (33) so that the channel order of the transmitting side PCM signal and the receiving side PCM signal channel correspond to each other. PCM signal multiplexing method.