JPS6238077A - Data arrangement replacing device - Google Patents

Abstract

PURPOSE:To reduce remarkably a signal processing time required for address designation of a memory device by applying read operation at the same time as write operation. CONSTITUTION:An enable signal 181 is fed for the control of write/read operation and the address is designated by an address designation means 12. An address designation means 12 is a counter 16 outputting count data 161 digitized in 14 bits from '0' to '16383', the count data 161 is inserted to a line fed to the address terminal of a memory device 18 and a shift register 17 outputs a signal while switching the connection order of each terminal by low-order 12 bits at the output terminal of the counter 16. A clock signal 19 is applied to the counter 16 to take the timing of the count-up. The high-order 2 bits of the counter 16 is used as the shift control signal 17 for the changeover of the connection order of the shifter 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data array replacement device that replaces and outputs the array of each data constituting a serially input data group according to a certain rule.

``Prior Art'' In information equipment and the like, in circuits that process a group of data having a certain relationship, the combinations and arrangements of the data are often permuted.

For example, LED array heads are widely used as devices for recording digitized image information on the photosensitive surface of a photosensitive drum, but the data transferred to these heads may also be replaced in a certain arrangement. be.

In general, an LED array head records a line of on-dots or off-dots in one recording operation, and the photosensitive surface of a photosensitive drum or the like is moved at a constant speed with respect to the LED array head and placed on top of this line. Records image information.

The LED array head is supplied with the image signal for one line each time it performs a recording operation. This image signal consists of one whose content is '0' to record an off-dot, and one whose content is '1' to record an on-dot, and there are several dozen of them. If the data is serially transferred to the LED array head, the transfer time becomes long, which hinders speeding up of the recording operation.

Therefore, as shown in FIG. 5, the LED array head 1 is provided with a plurality of shift registers 2 (eight in this example) that can store a fixed amount of image signals, and each shift register 2 is used to store one line of image signals. The image signal 3 is divided and transferred. In this example, the image signal 3 for one line is divided into eight parts each having a fixed amount as shown in the figure, and is extracted as shown by the arrow 4 and transferred to each shift register 2. When the image signals 3 are transferred as indicated by the arrow 4, the image signals 3 are stored in the shift register 2 in the same arrangement.

Moreover, the transfer speed is eight times higher than when it is supplied from a single line.

For example, in this case, as shown in FIG. 6, the image signals stored in the memory device 5 are picked up in consideration of the arrangement for transferring them to each shift register 2, and are once transferred to the shift register 5° that can store eight image signals. Store. Then, the process of transferring the data in parallel to the shift register 2 of the LED array head is repeated.

Here, for example, in an image signal group composed of 4096-bit image signals, each image signal has a value of "0" to "4095".
” and transfer it as described above. First, the image signal is transferred by random access.
Stored in a memory element etc., "0" to "511", "51"
2"~"1023", "1024"~"1535", "
1536” to “2047”, “2048” to “2559”
”, “2560” to “3071”, “3072” to “3”
8 such as 583”, 3584” to 4095”
into two groups. Then, the image signals of each group are sequentially transferred to the shift register 5I starting from the first image signal.

That is, “0”, “512”, “1o24”, “15
36”, “2048”, “256o”, “3072”,
Image signals are picked up in the order of "3584" and serially transferred. After this, “1”, “513”,
Continue like “1o25” and finally “3o71”
, "3583", "4095", and so on, and all data transfer processing is completed.

Such data arrangement replacement processing is performed not only in devices using LED array heads but also in various devices. The data array replacement device had a conventional configuration.

FIG. 7 is a block diagram showing an example of the device.

This device consists of a counter 6, a shifter 7, and a memory device 8. This counter 6 is a 12-bit digital counter, and is an element that outputs count data 6 degrees from "0" to "4o95" in synchronization with the clock signal 9. The shifter 7 is connected to the output terminal of the counter 7 and has the same number of input and output terminals, and when the shift control signal 7I is at the low level "L", the
Connect the two input/output terminals through and input the shift control signal 7.
When 1 is at high level "H", input terminal lN01INI and IN2 become output terminal 0UT9.0UT as shown in Figure 9.
Connected to IO1○UTII, input terminals IN3 to INI
This is an element that switches the connection so that I is connected to the output unit 0UTO to 0[JT8. Such a shifter is
For example, it is constructed by combining three commercially available 4-bit shifters.

In FIG. 7, the output signal 7° of shifter 7 is connected to the address terminal of memory device 8. In FIG. This memory device 8
consists of a random access memory element (RAM), etc., and includes enable and signals 8. for read/write control. When the enable signal 81 is at a low level "L", a write operation of the input data 8□ is performed, and when the enable signal 81 is at a high level "H", a read operation of the stored data is performed. The read output data 83 is serially transferred to the subsequent circuit. Its capacity is 4096 words xl bits.

This device operates as follows. First, the shift control signal 71 is set to "L" to put the shifter 7 into the connected state as shown in FIG. Then, "4096" pieces of input data 82 are serially sent to the memory device 8 in synchronization with the clock signal 9. The counter 6 counts up in accordance with the timing of the clock signal 9, outputs count data 6° from "0" to "4095", and specifies the address of the write operation of the memory device 8. The enable signal 81 is
Every time this address is specified and the input data 82 is input to the memory device 8, it becomes "■(") and controls the write operation.

In this way, the "1" to "4096" data serially input to the memory device 8 are stored in the addresses "0" to "4095".

Next, before data is read from the memory device 8, the shift control signal 71 is set to "H" to switch the connection state of the shifter 7 as shown in FIG. After that, the counter 6 again outputs count data 6 degrees from '0' to '4095'.The enable signal 81 is set to 'L'.
maintains the level and allows subsequent circuit read operations.

As a result, data is picked up in an address order different from the address order in which the write operation was previously performed, and is serially output.

This principle will be explained using an example in which 16 pieces of data are addressed by a 4-bit counter.

If you display 4-bit count data digitally,
From "1" to "16" are as shown in Table 1. Here, Q1 to Q4 indicate the output of each digit of the counter.

(The following is a margin) Table 1 In this first table, each count data consists of the least significant bit Q1 to the most significant bit Q4, but if this order is changed, it becomes as shown in the second table.

Table 2 In other words, as shown in Table 1, addresses are specified by sequentially counting up by 1, and the data written to the memory device is transferred from the upper 2 bits of the count output to the lower. When it comes to the lower 2 bits, it is possible to pick up every fourth piece of data and specify an address. The apparatus shown in FIG. 6 can permute the data arrangement using the same principle.

``Problem to be Solved by the Invention'' However, this data array replacement device cannot start the read operation until after all the data write operations have been completed, so it takes a long time to process the data. There was a problem that it was necessary.

The device of FIG. 10 is an improvement in this respect, and includes a counter 6, two shifters 7.7' and two memory devices 8.8' having the same functions as those used in the device of FIG. ing.

This device attempts to shorten data input/output time by having one shifter 7 and memory 8 perform a write operation while the other shifter 7' and memory 8' perform a read operation. .

Here, the counter 6 repeats the count-up operation from "0" to "4095", and the shifter 7.7' alternately outputs the shift control signal 7I with the opposite content.

7. In response to /, one side performs the connection shown in FIG. 8, and the other side performs the connection shown in FIG. This allows the memory device 8.8'
A write operation is performed on one side, and a read operation is performed on the other side.

This device speeds up data processing, but
Compared to the one shown in the figure, the number of parts was large and the circuit was complicated.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a data array replacement device that can suppress the increase in the number of parts and replace data arrays at high speed.

``Means for Solving Problems S'' The data array replacement device of the present invention stores a predetermined amount of serially input data group in a specified arbitrary address order, and serially stores a specified amount of data group in a specified arbitrary address order. The memory device has a memory device for outputting data and an addressing means for specifying the order of the addresses, and the memory device performs a read operation of one piece of previously stored output data while one address is specified. Immediately after, the process of writing one input data is repeated, and the previously stored data group is output and a new data group is input, and the addressing means writes the data group stored in the memory device. For the address order specified during the write operation,
This method is characterized in that a new address order that achieves replacement of a certain data array is specified during a read operation of the data group.

The addressing means includes, for example, a digital counter and a shifter that is inserted between the output terminal of this counter and the address terminal of the memory device and switches the connection order of the terminals. The next new address order is specified by exchanging the bit connection order.

Alternatively, the addressing means has a plurality of counters, each of which is provided with a carry output terminal for outputting a carry signal generated by carrying its most significant bit, and a separate carry output terminal. Carry input terminals provided on the counter and receiving the carry signals are interconnected to form a ring-shaped configuration, and a gate is provided between the carry output terminal and the carry input terminal,
Closing one of these gates specifies the address order using the count data obtained from the plurality of counters connected in a ring shape, and then opening that gate and closing another gate to specify the next address. Specify a new address order.

"Operation" This device inputs new data immediately after a specific address is specified in a memory device and the read operation of previously stored data is completed, but before that address is switched to the next address. , performs its write operation. Subsequent data will then be stored in the address order for output of the previously stored data. Therefore, when reading that data next time, a new address order is specified that is in a relationship that achieves a certain data arrangement replacement with respect to the address order specified during the data write operation. By repeating such operations, the read operation is performed at the same time as the write operation, so that the signal processing time required for address specification of the memory device can be significantly reduced. Furthermore, it is possible to prevent the circuit configuration from becoming plural.

Further, by using a plurality of counters connected in a ring shape and selecting and switching the position of the most significant bit of the count data, the above address order can be easily switched.

Embodiment (First Embodiment) FIG. 1 is a block diagram showing a first embodiment of a data array replacement device of the present invention.

In the figure, the memory device 18 is a random memory device that stores a predetermined amount of serially input data group 182 in the order of arbitrary addresses specified by the address signal, and outputs the data 183 in the order of the arbitrary addresses specified. This circuit consists of access memory (RAM) elements and the like. To control this read and write operation,
An enable signal 1g is supplied. Further, the address is specified by the address specifying means 12.

The addressing means 12 is inserted between the counter 16 which outputs 14-bit digitized count data 16. from 0 to 16383 and the line which feeds this count data 16. to the address terminal of the memory device 18. and a shifter 17 that switches the connection order of each terminal of the lower 12 bits of the output terminal of the counter 16 and outputs the same.

A tarock signal 19 is supplied to the counter 16 in order to time the count up. This clock signal 19 is also used to determine the timing for transferring input data 18□ from a data transfer device (not shown) to the memory device 18.

The most significant two bits of the counter 16 are used as a shift control signal 172 for switching the connection order of the shifter 17. Table 3 shows the rules for switching.

(Leaving space below) Table 3 As shown in this table, the output signal from the counter 16 is sequentially transferred three bits at a time to the upper side. Count output 16.
exceeds “4095”, its upper two bits are changed to “4095”.
From 00" (LL) to "01" (LH) to "10" (
HL) and “11” (HH). According to this change, the connection order is changed and this becomes “00′°
When it returns to the original connection order, the switching operation is repeated, returning to the initial connection order. Here, for convenience of explanation, symbols A, BSC, and D will be attached to each connection in the order.

The device of this embodiment operates as follows.

First, when no data is stored in the memory device 8, the shifter 17 is set in the connection order A and the counter 16 starts counting up.

Data 182 is sequentially written into the memory device 8 from number "0" to number "4095". This address order is the same as the count data 16□.

Next, at the stage of outputting the data, the shifter 17
The connection order can be changed according to the connection order. Then, firstly, Table 1 and 2.
As explained using the table, the data is at address "0"
, “512”, “1024”, “1536”, “2048”, “256”
0", "3072", and "3584" are read out in this order.

At this time, an enable signal 18□ is supplied to the memory device 18 at the timing shown in FIG. 2, and a write operation (indicated by 182) and a read operation (indicated by 182) are performed.

In FIG. 1, the address signal lasts approximately 50 nanoseconds (ns
The count is increased for each e c) (a in the same figure).

Here, the write operation of the input data 182 is performed during the first half (15 to 20 Cnsec) (FIG. 2B). Then, after a pause of several nanoseconds, a new input data reading operation is performed (C in the same figure). enable signal 1
8. A write operation is performed when “L” level, and “
As described above, the read operation is performed when the signal is at the H'' level.

Normally, when an address signal is input to an address terminal of a memory device, a write operation is performed after waiting a certain period of time until the contents are stabilized, and a similar waiting time is required for a read operation. Of course, the operating time for the counter to create new count data is also added to this. Therefore, the waiting time before and after a data write or read operation becomes quite long when integrated.

Therefore, if you specify the address for the write operation in the order shown in Figure 7 and finish writing all the data, then specify the address for the read operation again and read the data, a considerable amount of data will be generated. Requires operating time. On the other hand, if the write operation is performed immediately after the read operation as in the present invention, the waiting time can be significantly reduced.

Here, for the data written in connection order B in this way, a different address order must be newly specified for the read operation. This can be done in exactly the same way as when switching from the connection order Δ to the connection order Y. That is, as shown in Table 3, the connection order C is obtained by switching to move the top three digits of the connection order B to the lower side.

When this data read operation is performed in the order of addresses designated by connection order C, data to be input immediately thereafter is written at the same time. This operation is as described above. By repeating this operation, in this example,
The original connection order is restored every four rounds, during which data is written in a predetermined address order and output in an address order switched according to a certain rule.

(Second Embodiment) FIG. 3 is a block diagram showing another embodiment of the data array replacement device of the present invention.

In this embodiment, memory device 18 remains unchanged from that shown in the previous embodiment. Further, the addressing means 12 includes three 4-bit binary counters 21 . ~213 and 3 or games) 221 ~
It is composed of 223. Each counter 21. ~2
13 outputs a carry signal 2110-213° for carrying when the count data exceeds the maximum value "1111" and returns to the original "0000". Further, an input terminal is provided in order to count up the least significant bit using this carry signal. In this embodiment, the counters 211 to 213 are configured in a ring shape by connecting their carry input terminals and output terminals to each other. In addition, the carry signal 211° to 21° is connected between each terminal.
3° and counter switching signal 23. OR gates 22□ to 223 are inserted to perform a logical sum with 22□ to 233. Counter switching signals 231 to 233 are high level “H”
, the outputs of the OR gates 221 to 223 are always high, and when the low level is "L", the carry signal 2 is
1. ．． ~213° passes through this gate.

In the circuit having the above configuration, for example, the OR gate 22,
Counter switching signal 23. input to the counter switching signal 23. Only “H”
When the level is set, the counter 21□ to which the output terminal of the OR gate 221 is connected becomes the lowest level, and count data is output.

Next, the counter switching signal 232 is switched to "H" and output. These operations provide three connection orders. This is shown in Table 4.

(Leaving space below) Table 4 To move from connection order A to A in this way, the lower 4 bits are moved to the higher order. The same holds true when moving from connection order B to C. The switching is game) 22+, 222.
The counter switching signal to 22i is “HLL”.
”, “LHL”, and “L L H”.Therefore, this circuit does not require a shifter, and the circuit configuration is simplified accordingly.Reading to the memory device 18 The operation and write operation are exactly the same as those described above, so a description of the overlapping points will be omitted.

In the case of this embodiment, when data is stored from "0" to "4095", during the read operation, this data is "0", "256", "512", "768'', etc.
..."3584" and "3840" are output in this order.

(Application example) FIG. 4 shows an example of a data array replacement device suitable for using the data array replacement device of the present invention as explained using FIG.

This device is for transferring an image signal 31 to the LED array head 1 described above. Further, the image signal 31 is serially transferred from the data processing circuit 5 to the data array replacement device 32. Then, after performing a certain array replacement process, it is transferred to the buffer memory 51. The data is then transferred in parallel to each shift register of the LED array head 1. buffer memory 5
゜ performs the same operation as that previously explained using FIG. 6. In other words, the process of accepting 8 image signals to be supplied to 8 shift registers 2 and then outputting them in parallel (this process is repeated until all the image signals are stored in the shift registers). Arrangement replacement of this data By increasing the speed of transfer, the time required to transfer the image signal to the LED array head is shortened, so that high-speed recording can be performed.

Unlike that shown in FIG. 4, the shift register 2 having 256 bits and 16 stages is suitable for use with the apparatus described using FIG. 3.

"Variation" The present invention is not limited to the above embodiments.

For example, instead of a counter, a microprocessor that performs predetermined calculations and outputs necessary count data may be used. Further, a read-only memory element or the like which outputs count data in a predetermined order may be used. The order of addresses for writing and reading data into the memory device may be changed to various formats other than those illustrated. The replacement format of this data may be selected depending on the purpose. In addition to LED arrays, L
Needless to say, it is also applicable to CD arrays, thermal heads, etc.

"Effects of the Invention" The data array replacement device of the present invention described above can significantly shorten the signal processing time while preventing an increase in the number of parts, and can be used in various devices that require data array replacement. This contributes to improved performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the data array replacement device of the present invention, FIG. 2 is a time chart explaining its operation, FIG. 3 is a block diagram showing a second embodiment of the present invention, and FIG. The figure is a block diagram of a circuit suitable for using the data array replacement device of the present invention, Figure 5 is a conceptual diagram explaining the method of transferring image signals to the LED array head, and Figure 6 is a plot of the circuit. 7 is a block diagram of a conventional data array replacement device used for this, FIGS. 8 and 9 are circuit diagrams explaining the operation of the shifter, and FIG. 10 is another conventional data array replacement device. FIG. 2 is a block diagram showing the device. 12...addressing means, 18...memory device, 16.211-213...counter, 22,
~223...Gate. Applicant: Fuji Xerox Co., Ltd. Agent

Claims (1)

[Claims] 1. A memory device that stores a predetermined amount of serially input data group in an arbitrary specified address order and serially outputs it in an arbitrary specified address order, and specifies the address order. and addressing means, wherein the memory device performs a read operation of one previously stored output data while one address is designated, and immediately thereafter performs a write operation of one input data. By repeating this process, the previously stored data group is output and a new data group is input, and the addressing means specifies the address order specified during the write operation of the data group stored in the memory device. 1. A data array replacement device, characterized in that a new address order in a relationship that achieves replacement of a certain data array is specified during a read operation of the data group. 2. The addressing means consists of a digital counter and a shifter that is inserted between the output terminal of this counter and the address terminal of the memory device and switches the connection order of the terminals, and uses this shifter to change the upper bits of the counter. 2. The data array replacement device according to claim 1, wherein the next new address order is specified by exchanging the connection order between the lower bits and the lower bits. 3. The addressing means has a plurality of counters, each of which is provided with a carry output terminal for outputting a carry signal generated by carrying the most significant bit, and a separate counter. Carry input terminals provided on the terminal and receiving the carry signals are interconnected to form a ring-shaped configuration, a gate is provided between the carry output terminal and the carry input terminal, and one of the gates is closed. , the address order is specified by the count data obtained from the plurality of counters connected in a ring shape, and then the next new address order is specified by opening that gate and closing another gate. A data array replacement device according to claim 1.