JPS6238087A - Picture display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention generates an electron beam for each division when a screen on a screen is vertically divided into a plurality of divisions, and generates an electron beam for each division. The present invention relates to an apparatus for displaying a plurality of lines by vertically deflecting a beam to display a television image as a whole.

Conventional technology Traditionally, cathode ray tubes have been mainly used as display elements for displaying color television images, but conventional cathode ray tubes have a very long depth compared to the screen size, making it difficult to use in thin television receivers. It was impossible to create. Furthermore, as flat display elements, EL display elements, plasma display devices, liquid crystal display elements, etc. have recently been developed.

All of them are insufficient in terms of performance such as brightness, contrast, and color display, and have not yet been put into practical use.

Therefore, in order to achieve a flat display device using an electron beam, the present applicant has filed Japanese Patent Application No. 1986-206], No. 8 (
A novel display device was proposed in Japanese Patent Application Laid-Open No. 57-135590.

This method generates an electron beam for each section when the screen is vertically divided into multiple sections, and displays multiple lines by deflecting each electron beam vertically for each section. However, it displays a television image as a whole.

First, a basic configuration of the image display element used here will be explained with reference to FIG. 6. This display element consists of, in order from the back to the front, a back electrode (1), a line cathode (2) as a beam source, vertical focusing electrodes (3) (3'), a vertical deflection electrode (4), and a beam flow control Electrode (5), horizontal focusing electrode (
6) It consists of a horizontal deflection electrode (7), a beam acceleration electrode (8), and a screen (9), which are housed inside a flat glass bulb (not shown) that is evacuated. has been done. Line cathode as beam source (2)
is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction, and a plurality of such linear cathodes (2) are arranged vertically at appropriate intervals ((2a) to (2) in the figure).
2d) only four are shown). In this example, it is assumed that 15 are provided. them (2a
) to (2o). These wire cathodes (2) are constructed by coating the surface of a tungsten wire with a diameter of 10 to 20 μΦ with an oxide cathode material for thermionic emission. These line cathodes (2a) = (2o) are heated so as to generate a thermionic beam by passing an electric current through them, and as will be described later, they are heated sequentially for a certain period of time starting from the line cathode (2a) above. It is controlled to emit an electron beam at a time. The rear ffl pole (1) suppresses the generation of electron beams from other line cathodes other than the line cathode that is controlled to emit electron beams for a certain period of time, and directs the generated electron beams only in the forward direction. It has the effect of pushing out towards. This back electrode (]) may be formed by a coating film of a conductive material adhered to the inner surface of the rear wall of the Gagaraspal. Moreover, a planar electron beam emitting cathode may be used instead of the back electrode (1) and the linear cathode (2).

The vertical focusing electrode (3) is a conductive plate (11) having a horizontally long slit (10) facing each of the line cathodes (2a) to (20), and collects the electron beam emitted from the line cathode (2). taken out through the slit (10),
and vertically focused. 1 horizontal line (4
00 picture elements) are taken out simultaneously. In the diagram,
Of these, only one section in the horizontal direction is shown.

The slits (10) may be provided with crosspieces at appropriate intervals in the middle, or may be a row of through holes provided in large number at small intervals in the horizontal direction (intervals that are almost touching). It may be configured substantially as a slit. The vertical focusing electrode (3') is also similar.

A plurality of vertical deflection electrodes (4) are arranged horizontally at intermediate positions between the slits (10),
Conductors (
13) (13') is provided. Then, a vertical deflection voltage is applied between the opposing conductors (13) (13') to deflect the electron beam in the vertical direction. In this example, a pair of conductors (13) (1
3') deflects the electron beam from one line cathode (2) vertically to positions corresponding to 16 lines.

The 16 vertical deflection electrodes (4) constitute 15 conductor pairs corresponding to each of the 15 line cathodes (2), so that 240 horizontal lines are drawn on the screen (9) i. Deflect the electron beam to

Next, the control electrodes (5) are composed of conductive plates (15) each having a long slit (14) in the vertical direction, and a plurality of control electrodes (5) are arranged in parallel in the horizontal direction at a predetermined interval.

In this example, 200 control electrode conductive plates (15-1)
~(15-n) are provided. (Only 9 lines are shown in the figure). Each of the control electrodes (5) separates and extracts the electron beam into two picture elements in the horizontal direction, and controls the amount of electron beam passing therethrough in accordance with a video signal for displaying each picture element. Therefore, the conductive plate for the control electrode (5) (
If 20,000 lines of 15-1) to (15-n) are provided, 400 pixels can be displayed per horizontal line. Also,
In order to display images in color, each picture element is displayed using phosphors of three colors, R, G, and B, and each control electrode (5) has R and G for two picture elements.

Each video signal of B is added sequentially. In addition, 200 pairs of video signals for one line (2 pixels per pair) are simultaneously applied to each of the 200 conductive plates (15-1) to (15-n) for control electrodes (5). ] Lines of video are displayed at once.

The horizontal focusing electrode (6) is connected to the slit (14) of the control electrode (5).
) is composed of a conductive plate (17) having a plurality (200) of vertically long slits (16) facing each other, and the electron beam for each pixel divided in the horizontal direction is transmitted in the horizontal direction. Focus into a narrow beam of electrons.

The horizontal deflection electrode (7) is composed of a plurality of conductive plates (18) (18') arranged vertically on both sides of the slit (16), and each electrode (18) ( 18') is applied with six levels of horizontal deflection voltage to deflect the electron beam of each picture element in the horizontal direction, so that two sets of R and G are displayed on the screen (9).

Each phosphor of B is sequentially irradiated to emit light. In this embodiment, the deflection range is two picture elements wide for each electron beam.

The accelerating electrode (8) is composed of a plurality of conductive plates (19) installed horizontally in the same position as the vertical deflection electrode (4), and it directs the electron beam to the screen (9) with sufficient energy. Accelerate to cause a collision.

The screen (9) is constructed by applying a phosphor (20) that emits light when irradiated with an electron beam to the back surface of a glass plate (21), and adding a metal bank layer (not shown). The phosphor (20) has two phosphors of three colors R2O and B for one slit (14) of the control electrode (5), that is, for each one electron beam divided in the horizontal direction. They are provided in pairs and are applied in vertical stripes. The broken lines drawn on the screen (9) in FIG. 5) shows the horizontal divisions displayed corresponding to each of the items. As shown in the enlarged view in Figure 7, one section partitioned by these two has R, G, and B phosphors (20) for two picture elements in the horizontal direction, and 16 lines in the vertical direction. It has a width of 30 minutes. The size of one section is, for example, 1 m in the horizontal direction and IO in the vertical direction.
It is nm.

Note that in FIG. 6, the length in the horizontal direction is greatly expanded relative to the length in the vertical direction for clarity.

In addition, in this example, two R, G, and B phosphors (20) are used for one control electrode (5), that is, one electron beam.
Although only one pair for each picture element is provided, of course, one picture element or three or more picture elements may be provided, and in that case, the control electrode (5) has one picture element or more than three picture elements. R, G, and B video signals for 2 are sequentially applied, and horizontal deflection is performed in synchronization with this.

Next, the basic configuration and waveforms of each part of a drive circuit for displaying television images on this display element will be explained with reference to FIG. First, a driving portion for irradiating the screen (9) with an electron beam to emit raster light will be explained.

The power supply circuit (22) is a circuit for applying a predetermined bias voltage (operating voltage) to each electrode of the display element.
-v1 for 1), V 31 V 3' for the vertical focusing electrode (3) (3'), V6 for the accelerating electrode (8) for the horizontal focusing electrode (6), and V6 for the screen (9). A DC voltage of V is applied.

Next, a composite video signal of a television signal is applied to the input terminal (23), and a vertical synchronization signal V and a horizontal synchronization signal H are separated and extracted in a synchronization separation circuit (24).

The vertical deflection drive circuit (40) includes a vertical deflection counter (2
5), a memory for vertical deflection signal storage (27), and a digital-to-analog converter (39) (hereinafter referred to as a DA converter). As input pulses to the vertical deflection drive circuit (40), a vertical synchronizing signal (2) and a horizontal synchronizing signal (H) shown in FIG. 9 are used. Vertical deflection counter (25) (
8 bits) are reset by the vertical synchronizing signal V and counting the horizontal synchronizing signal H.

This vertical deflection counter (25) counts the effective scanning period (in this case, a period of 240H) excluding the vertical blanking period of the vertical period, and this count output is supplied to the address of the memory (27). be done. The memory (27) outputs vertical deflection signal data (here, 8 bits) corresponding to each address, and the data is sent to the D-A converter (39).
? It is converted into a vertical deflection signal of 27.27' as shown in FIG. 9 (FIG. 8(b)D). This circuit has memory addresses for storing vertical deflection signals corresponding to each line of 240H, and by storing regular data in the memory every 168 minutes, it is possible to obtain vertical deflection signals of 16 levels. can.

On the other hand, the line cathode drive circuit (26) uses the vertical synchronization signal V and the output of the vertical deflection counter (25) to create line cathode drive pulses a-o. Figure 10(a) shows the vertical synchronization signal ■
, shows the relationship between the horizontal synchronizing signal H and the lower 5 bits of the vertical deflection counter (25). FIG. 10(b) shows that each line cathode drive pulse a' to O is calculated using these signals.
We will show you how to make I. In FIG. 10, LSB indicates the lowest bit, and (LSB+1) means the bit one higher than the LSB.

The first line cathode drive pulse a' can be created by an R-S flip-flop using the vertical synchronization signal ■ and the output (LSB+4) of the vertical deflection counter (25), and the line cathode drive pulse b'~0 ' uses a shift 1 register to transfer the line cathode drive pulse a' to the vertical deflection counter (25).
This can be obtained by transferring the inverted version of the output (LSB+3) as a tarok. This drive pulse a
'~0' are inverted and made low potential only during each pulse period,
During other periods, the pulses are converted into linear cathode drive pulses a to 0 with a high potential of about 20 volts (FIG. 8(b)E), and are applied to each of the linear cathodes (2a) to (2o).

Each line cathode (2a) to (20) is heated by passing a current during the high potential period of the drive pulse a-o, and is heated so that it can emit electrons during the low potential period of the drive pulse a-0. State is preserved. As a result, 15 wire cathodes (2a)
From ~(2o), low potential drive pulses a~0 are respectively applied.
Electrons are emitted only during the 1 6 H period when .

During periods when a high potential is applied, the line cathode (2a ) to (2o) is more positive, so no electrons are emitted from the line cathodes (2a) to (20). Thus, in the line cathode (2), during the effective vertical scanning period, the upper line cathode (2a)
Electrons are sequentially emitted from the line toward the line cathode (2o) for each 16H period. The emitted electrons are pushed forward by the back electrode (1), pass through the opposing slits (10) of the vertical focusing electrode (3), and are focused in the vertical direction to form a flat electron beam. .

Next, the line cathode drive pulse a = o and the vertical deflection signal υ,
The relationship with υ' will be explained using FIG. FIG. 11(a) is a waveform diagram of a line cathode drive pulse.

(b) is a waveform diagram of the vertical deflection signal, and (c) is a waveform diagram of the horizontal deflection signal. Vertical deflection signal υ in FIG. 11(b).

υ' is 16H of each line cathode pulse a~0 in Fig. 11(a).
It changes in 18 minute increments during the period and changes in 16 steps.

Both vertical deflection signals υ and υ' have a center voltage of v4, and υ increases sequentially and υ' decreases sequentially.
They are designed to change in opposite directions. These vertical deflection signals υ and υ' are applied to the electrodes (13) and (13') of the vertical deflection electrode (4), respectively, resulting in the electron beams generated from the respective line cathodes (2a) to (20). is vertically deflected in 16 steps, and as mentioned earlier, on the screen (9), one electron beam is deflected so that a raster of 16 lines is drawn sequentially one line at a time from the top.

As a result of the above, electron beams are emitted sequentially from the top of the 15 line cathodes (2a) to (2o) for a period of 16H, and each electron beam is sequentially emitted in one line from top to bottom within 15 sections in the vertical direction. On the screen (9), from the first line at the top to the 24th line at the bottom.
The electron beam is vertically deflected one line at a time up to the 0th line, and a total of 240 raster lines are drawn.

The vertically deflected electron beam is sent to the control electrode (5).
The sample is divided into 200 sections in the horizontal direction by a horizontal focusing electrode (6) and taken out. In Figure 7, one of them
The classification is shown. The amount of this electron beam passing through each section is controlled by a control electrode (5), and is focused horizontally by a horizontal focusing electrode (6) into a single narrow electron beam. The light is deflected in six steps in the direction and sequentially illuminates the R2O, B capacitive light body (20) for two picture elements on the screen (9). FIG. 7 shows the vertical and horizontal divisions. The phosphors corresponding to (15-1') to (15-n) of the control electrode (5) are R, G, and B for two picture elements, but for convenience of explanation, one picture element is R1, G□ IB+ and the other one is R2, G,,
, B2.

In addition, the horizontal deflection drive circuit (41) is composed of a horizontal deflection counter (28) (11 points), a memory (29) that stores horizontal deflection signals, and a D-A converter (38). . The input pulses of the horizontal deflection drive circuit (41) are the vertical synchronization signal ■ and the horizontal synchronization signal ■ as shown in Fig. 12.
(in synchronization with , and uses a pulse 6H with a repetition frequency six times that of the horizontal synchronization signal H. The horizontal deflection counter (28) is reset by the vertical synchronization signal V and counts six times the horizontal pulse 6H. This horizontal deflection counter (28)
is 6 times during 1H, 240HX 6/H= during 1■
It counts 1440 times, and this count output is stored in the memory (
29).

The memory (29) outputs horizontal deflection signal data (8 bits in this case) according to the address, and the D-A converter (38) converts it as shown in Figure 12 (Figure 8 (b) C). , h'. This circuit has memory addresses for storing horizontal deflection signals corresponding to each of 6 x 240 lines, and by storing 6 pieces of regular data for each line in the memory, 6 step waves can be generated during the IH period. horizontal deflection signals can be obtained.

As shown in Figure 12, this horizontal deflection signal is a pair of horizontal deflection signals ri and h' that change in six steps, both of which have a center voltage of v7, h decreasing sequentially and h' increasing sequentially. They change in opposite directions as they move forward. These horizontal deflection signals h' are applied to electrodes (18) and (18') of the horizontal deflection electrode (7), respectively. As a result, each horizontally segmented electron beam is applied to the R, G of the screen (9) during each horizontal period.

B, R, G, B (R1, G1.B,, R,, G,, B
The light is horizontally deflected so that the phosphor of 2) is sequentially irradiated for H/6 periods. Thus, in each line raster, the electron beam is R1, G for each of the 200 sections in the horizontal direction.
□, B□, R2, G2. Each phosphor (20) of B2 is sequentially irradiated.

Therefore, for each horizontal section of each line, the electron beam is
A color television image can be displayed on the screen (9) by modulating it with the video signal of RZI az+B2.

Next, the modulation control portion of the electron beam will be explained. First, the composite video signal applied to the television signal input terminal (23) is applied to the color demodulation circuit (30), where the R-Y and B-Y color difference signals are demodulated and the G-Y color difference signal is demodulated. The signals are matrix-synthesized, and further, they are combined with the luminance signal Y to form each primary color signal of R2O and B (hereinafter R,
G, B video signals) are output. Those R,G
, B. Each video signal is processed by 200 sets of sample and hold circuits (3
1-1) to (31-n). Each sample-and-hold circuit (31-1) to (31-n) has six sample-and-hold circuits for R, G, B1, R2, G, and B2. Those sample and hold outputs are stored in the holding memories (32-], ) to (3), respectively.
2-n).

On the other hand, the reference clock oscillator (33) is composed of a PLL (phase-locked loop) circuit, etc., and in this example, the reference clock 6fsc is six times the color subcarrier fsc.
and a double reference clock 2fSC is generated. The reference clock is controlled to always have a constant phase with respect to the horizontal synchronizing signal H.

The reference clock 2fsc is a deflection pulse generation circuit (42)
signals 6H and H/6, which are six times the horizontal synchronization signal H.
Signal switching pulse for each rip gzp bx+ rz+
Pulses of gz and bz (FIG. 8(b) B) are obtained. On the other hand, the reference clock 6jsc is applied to the sampling pulse generation circuit (34), where it is delayed by one clock period by a shift register, etc., so that the horizontal period (
The effective horizontal scanning period (approximately 52,5μ5ec)
μ5ec), 1200 sampling pulses R□g G, 11 B 11 g R12, G 1□,
B engineering 2. R21, G2□.

B zt+Rzz+ G221 B22~Rnt+ G
r+, Bnl, Rnz+Gn, , Bn, (FIG. 8(b) A) are generated in sequence, and then one transfer pulse t is generated. This sampling pulse R□～Bn
2 corresponds to each picture element when one line of the video to be displayed is divided into 400 picture elements in the horizontal direction, and its position is controlled so as to be always constant with respect to the horizontal synchronizing signal H.

These 1200 sampling pulses R, ~Bn, each form 200 sets of sample and hold circuits (3], -1
) to (31-n), and thereby each sample-hold circuit (31-1) to (31-n)
When one line is divided into 200 parts, each 2
Picture elements R1, G, , B, , R2, G2 . Each B2 video signal is individually sampled and held. 200 pairs of sample-held R1101T 811
R21G2. After the B2 video signal is sampled and held for one line, it is stored in 200 sets of memories (32-1) to (
32-n), the signals are transferred all at once by a transfer pulse and held here for the next horizontal period. This retained R
□.

The signals of G□l Bit R, Gel B2 are applied to switching circuits (35-1) to (35-n). The switching circuits (35-1) to (35-n) each have R11Gll I3t+R2, G2. It is constructed of a tri-state or analog gate having individual input terminals of B and B and a common output terminal that sequentially switches and outputs them.

The output of each switching circuit (35-1) to (35-n) is 200 sets of pulse width modulation (PWM) circuits (37-1)
~(37-n), where the sample-held R1. The reference pulse signal is pulse width modulated according to the magnitude of the B2 video signal and is output. The repetition period of the reference pulse signal is preferably sufficiently smaller than the pulse width of the signal switching pulses rx+gs, +b□, r2゜gzybz, for example, about 1:10 to 1:100. is used.

This pulse width modulation circuit (37-1) to □ (37-n)
The output of 200 conductive plates (15-1) of the control electrode (5) of the display element is used as a control signal for modulating the electron beam.
) to (15-n) individually. Each switching circuit (35-1) to (35-n) receives a switching pulse rz+gzy bz+rxp gzp b applied from the switching pulse generating circuit (36).
Switching is controlled simultaneously by z. The switching pulse generation circuit (36) is the same as the aforementioned deflection pulse generation circuit (42).
) Signal switching pulse from rxp gzy bx+ r
Each horizontal period is divided into 6 and each H/6 switching circuit (35-
1) to (35-n), R1, Gx, Bi, R
2, G2. A switching signal is provided so that each video signal of B2 is time-divided and sequentially outputted and supplied to the pulse width modulation circuits (37-1) to (37-n).
Generate bz.

What should be noted here is that the switching circuit (35-
1) R,,G1. in -(35-n). B...
R2゜G, , B2 video signal supply switching and electron beam R□, GUTB by the horizontal deflection drive circuit (41)
ll R,.

G2. The horizontal deflection for switching the irradiation onto the phosphor B2 is synchronously controlled so that it completely matches both the timing and the order. As a result, when the electron beam is irradiating the R1 phosphor, the irradiation amount of the electron beam is controlled by the R0 video signal, and G□, B
Similarly, R21G 21 B 2 is controlled in the same way, and R, , G1 . B1°R2, G2. B2
The light emission of each phosphor is R□, G1°B, , R2,
G2. Each picture element is controlled by the B2 video signal, and each picture element is displayed by emitting light according to the input video signal. There are 200 sets of such control for one line (2 sets each)
(one picture element at a time) and an image of 400 picture elements per line is displayed.

Furthermore, the processing is performed sequentially for 240H lines starting from the upper line, and one image is displayed on the screen (9).

The above operations are performed on one input television signal.
This is repeated for each field, and as a result, a moving television image is displayed on the screen (9) in the same way as a normal television receiver.

Here, PWM circuits (37-1,) to (37-
b) will be explained in more detail. PWM circuit (3
7-1) to (37-n) basically consist of a 6-bit parallel synchronous counter and a set/reset flip-flop (R5T-F/F) as shown in Figure 1, and the input signal is Load pulse (2fs waveform in the upper row of Figure 2)
(notes the number of pulses of c), tarokku, R, G, B
There are three types of serial data.

As shown in FIG. 2(a), the load pulse is created based on 2fsc, and the IH period is divided into six at equal intervals. Their spacing is 64×±≠8, 1 in 911s
.

There are 8 x 2fso=1 between the above 6 divisions,
One leg guard band is provided. Then, 6-bit data for two picture elements of R, G, B, R, G, and B are applied serially and preset to the parallel synchronous counter using the six guard bands. The conventional output waveform shown in FIG. 2(b) is when all the data are at I (level), that is, the blank screen (modulation degree is 100%).

At this time, since the parallel synchronous counter is operated using fck=2fsc as the reference clock, the output pulse width is 64×2fgo, and the maximum pulse width is 64 digits of the 2fsc pulse. This is the input signal, i.e. the 8th
Outputs R and G of the color demodulation circuit 30 in the figure.

This corresponds to the maximum amplitude of B.

Note that the dashed line in the conventional output waveform in Fig. 2 is
It shows the output when the data of R is halved.

Problems to be Solved by the Invention However, in the above configuration, the clock fck used in the PWM circuit is a single 2fsc.

Since it is commonly used for G and B data, when each data is all high level, the R, G, and B outputs have the same pulse width, as shown in the conventional output waveform of FIG. 2.

Therefore, in order to adjust the white balance, the amplitudes of the outputs R1G and B of the color demodulation circuit 30 shown in FIG.
It was used as input signal data to the M circuit. Therefore, 5. For example, to obtain white balance, -R: G: B
The amplitude of each color signal was adjusted so that the ratio was 76:98:100.

However, this means that if we use the full 6 bits for the B data, then for the R data we will use approximately 374 5 bits.
．． Since it is only equivalent to 5 bits, there is a problem in that the gradation is impaired due to the lack of R intermediate tones, and the image on the display screen becomes unnatural and extremely difficult to view.

The present invention solves the above problems, and provides an image display device that can adjust the white balance without adjusting the amplitudes of the color demodulation signals R,'G,B and without deteriorating the gradation. The purpose is to provide

Means for Solving the Problems In order to solve the above problems, the present invention changes the clock fck input to the counter in the PWM circuit by input data R, which is preset into the counter so as to correspond to the white balance ratio. The configuration is such that the frequency is switched in synchronization with the G and B inputs.

Effect: The present invention has the above-described configuration, and the R and G signals that serve as preset data for the counter in the PWM circuit.

Since the frequency of the reference clock fck of the counter is varied in accordance with the white balance ratio in synchronization with the input signal of B, the minimum step that conventionally determines the gradation is 1/Z f Like sc color 140ns<R,
While it was common to all G and B, the pulse width of this minimum step is variable corresponding to R, a, and B. Therefore, even if the same conventional data is input, an output with the same number of steps and different pulse widths can be obtained, so that the gradation of 6 bits and 64 steps can be made exactly the same for R, G, and B. The fck frequency is adjusted so that this difference in pulse width results in a desired white balance ratio.

EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.

In Fig. 1, (37) is the same PWM circuit as the conventional one, and when the load pulse applied to the preset terminal of the 6-bit parallel synchronous counter (43) is at H level, R, G,
The data of B is sequentially preset and counted up at the frequency of the clock fck, and the ripple carry is output from the RC terminal and input to the set terminal S of the set/reset flip-flop (44), and its Q
From this point on, the output becomes H level. A load pulse is input to the reset terminal R of the set/reset flip-flop (44), and at the rising edge of this pulse, the set/reset flip-flop (44) is reset, and the Q output returns to L level. Therefore, the Q output has a pulse width proportional to the preset value of the 6-bit parallel synchronous counter (43).

(45) shows a block of the present invention, and is a clock frequency control circuit that controls the clock fck of the 6-bit parallel synchronous counter (43). This control circuit (45) is (4
It consists of a phase comparator (APC) (7), a low pass filter (LPF) (48), a voltage controlled oscillator (VCQ) (49), and a programmable frequency divider (46).

The horizontal synchronization signal fn input to the clock frequency control circuit (45) is phase-compared with the output of the programmable frequency divider (46) that divides the output of VCO (49) at A and PC (47), and then VCQ through L P F (48)
(49), while the phase selection pulse φk is input separately.

φQ and φB control the programmable frequency divider (46),
As a result, the clock fCk of the VCO (49) output is controlled to achieve the desired white balance.

FIG. 4 shows the timing of the load pulse and the phase selection pulses φR to φB.

FIG. 3 is a circuit diagram showing a specific example of the clock frequency control circuit (45). The operation will be explained with reference to the figures. The blocks (46) to (49) are similar to those shown in FIG. 1, and the LPF of (47) APCl (48)
For general-purpose IC4044, (49) VCQ
For this, I am using IC4024. Regarding the programmable frequency divider (46), three 4-bit synchronous counters 92 are used, and the data at the preset terminal is controlled by a 4066 analog gate to a desired value corresponding to the white balance. This frequency divider (46)
Assuming that the ratio of is -N, the following equation holds true between fu and fck.

f ck = f H-N -11) Also, in the television signal, there is a relationship between the color subcarrier fsc and fn as fu = '' - fsc, so this can be expressed in equation (1). Substituting and eliminating fn, fck= □ fsc-N - (2)
becomes.

As can be seen from equation (2), by changing the value of N, the frequency of fck can be varied, which means that the minimum step of the PWM circuit output is varied.

FIG. 5 is a graph showing the relationship between fck and N. fsc uses a value of 3.579545 MHz.

Next, to actually make this value of N correspond to the white balance ratio, 1 Normal white balance ratio is S (R): S
(G): S (B) = 76: 98: 100
All you have to do is take the value of the place and make it become.

These 5(R), 5(G), and 5(B) are the input values of the PWM circuit, that is, the amplitudes of the color demodulation outputs R, G, and H of the color demodulation circuit (30) in FIG. 8.

Also, since the ratio is usually determined based on the color of blue,
If fcKRlfcKa is expressed by faKo, then

Furthermore, the reference clock of the image display device to which this embodiment is applied uses 2fsc, and since 2fsc was also used for the clock fck of the conventional PWM circuit, the reference clock f
If we set g = 2 f sc in a, equation (3), (4)
The formula becomes. Therefore, from equation (2), =599 =464, and the frequency division ratio NR+ corresponding to the white balance ratio
No is found. That is, NR: NG: NB=59
It becomes 9:464:455. At this time, the frequency f (!K
Ry f c+c.

As shown in FIG. 5, from equation (2), faKv#9.
42MHz, fcta=7.3M7. Therefore, the maximum pulse width of the PWM output when the margin data is input is 6.79. , G is 8.77, B is 8.971s, and the white balance ratio is certainly 76.
It can be clearly seen that the values are very close to 98:100.

As described above, by varying <fck as shown in FIG. 2(d) so as to correspond to the white balance ratio, as shown in FIG. 2(c),
It is possible to obtain a desired value without excessively deteriorating the gradation (in this example, 64 gradations of 6 bits), and it is possible to arbitrarily set the white balance without causing deterioration of the displayed image. can.

Effects of the Invention As described above, according to the present invention, each R, G.

Any desired white balance can be achieved without degrading the B gradation at all.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a comparison of PWM output waveforms when the present invention is introduced, and FIG. 3 is a diagram of a specific circuit example of the present invention. FIG. 4 is a diagram showing the timing of the load pulse and phase selection pulses φR to φB, FIG. 5 is a graph showing the relationship between fck and N, and FIG. 6 is a diagram showing the basic electrodes of an image display device to which the present invention is applied. Figure 7 is a diagram showing the minimum unit configuration of this image display device on the screen, Figure 8 is a block diagram and waveform diagram of the drive circuit in the device, and Figure 9 is a diagram showing the vertical deflection voltage and horizontal Figure 10 is a diagram showing the correlation with the synchronization signal, Figure 10 is a diagram showing various timing charts, Figure 11 is a diagram showing the relationship between the cathode drive pulse, vertical deflection signal, and horizontal deflection signal, Figure 1
FIG. 2 is a diagram showing the correlation between the horizontal deflection voltage and the horizontal synchronization signal. (2), (2a) to (2o)... line cathode, (3) (
3) ' Vertical focusing electrode, (4) Vertical deflection electrode, (5) Beam flow control electrode, (7) Horizontal deflection electrode, (9) Screen, (20) ... Phosphor, (37) ... PWM circuit, (45) ... Clock frequency control circuit, (46) ... Programmable frequency divider, (47) ... APC circuit, (48) ...・LP
F, (49)...VC○Figure 1~ gi () -,- Figure 3 Figure 5~ Figure 7 2ρ Tsukushichi phrase qlQ-mediated Figure 3 (1)) Cp Figure 9 "17゛□ L-1I shi-・1 °1.: Figure 1θ<a>e'

Claims (1)

[Claims] 1. An electron beam generation source, a screen having a phosphor that emits light when irradiated with the electron beam, a focusing electrode that focuses the electron beam generated by the electron beam generation source, and a screen that focuses the electron beam on the screen. an electrostatic deflection electrode that deflects the electron beam until the electron beam reaches the screen; and a control electrode that controls the emission intensity by controlling the amount of the electron beam irradiated onto the screen, and the pulse that is applied to the control electrode. An image display device equipped with a clock frequency control circuit that modulates the frequency of a basic clock used when a width modulation (PWN) signal is formed by a digital circuit using a counter at a ratio corresponding to white balance.