JPS6238741B2 - - Google Patents

Abstract

PURPOSE:To diagnose a memory bus, etc., in a refresh operation period, by providing a CPU with a priority processing circuit. CONSTITUTION:A refresh control circuit 26 outputs a refresh operation request signal REF to a main memory 22, composed of elements DRAM, at constant intervals. This signal has higher priority than memory access request signals outputted from active modules 241-24n. Once the signal REF is accepted by a priority processing circuit 27, a memory access control circuit 28 outputs a refresh start signal to the main memory 22, which is returned by modules 241-24n via a refresh acceptance signal line 29. In a CPU21, on the other hand, the contents of an address register are held and also sent out to modules 241-24n via a memory bus 25 to be returned there. The CPU compares the returned contents with the previoulsy held contents of the register to diagnose a bus.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device capable of efficient bus diagnosis.

Information processing devices generally include a main memory in which various programs and data are stored. The storage section, which forms the main part of main memory, is dynamic, random, and
It is often composed of access memory (hereinafter referred to as DRAM) elements. In a DRAM element, since its memory cells are of a dynamic type, it is necessary to perform a memory refresh operation periodically in order to retain data, as is well known.

When a main memory whose storage section is a DRAM element is introduced into an information processing device, the configuration differs depending on the refresh control method as shown in FIGS. 1 and 2. FIG. 1 shows a schematic configuration of an information processing device in which a refresh control circuit 2 is provided in a main memory 1.
The element is refreshed. On the other hand, the central processing unit (hereinafter referred to as CPU) 3 is provided with a memory access control circuit 6, which controls access to the main memory 1. That is, a memory access request signal is sent from active modules 5 ₁ to 5n such as channels connected to the memory bus 4.
When REQ ₁ to REQn are output, the memory access control circuit 6 accepts the requests according to predetermined priorities. and,
Address information and the like are transferred from the active module whose request has been accepted to the main memory 1 via the memory bus 4. In this case, the response of the main memory 1 to the access from the active module becomes asynchronous due to the refresh operation by the refresh control circuit 2. This has resulted in a drawback that the control is complicated, that is, the configuration of the memory access control circuit 6 is complicated. In the configuration shown in FIG. 1, when access by the active modules 5 ₁ to 5n conflicts with the refresh operation, the memory bus 4 of the active module (active module 5 ₁ in the figure) is The usage time is indefinite.

On the other hand, FIG. 2 shows a schematic configuration of an information processing apparatus in which a refresh control circuit 11 is provided in a CPU 15 independently of a main memory 12. In this example, the refresh control circuit 11 is regarded as one active module. In the configuration shown in FIG. 2, the refresh operation request signal REF from the refresh control circuit 11 and each memory access request signal REQ 1 - REQ ₁ - from active modules 14 ₁ - 14 n such as channels connected to the memory bus 13 are transmitted. Based on REQn, the request is accepted by the memory access control circuit 16 in the CPU 15 according to a predetermined priority. In this case, as described above, the refresh control circuit 11 is connected to the active modules 14 ₁ to 14n.
Active module 1 because it is considered a module similar to (but has the highest priority)
Main memory 1 for access from 4 ₁ to 14n
Response 2 is of the synchronous type. Therefore, the information processing apparatus shown in FIG. 2 has the advantage that the configuration of the memory access control circuit 16 is simplified. however,
In the configuration of FIG. 2, when a refresh operation is performed in response to a refresh request from the refresh control circuit 11, the active modules 14 ₁ to 1
4n cannot monopolize the memory bus 13 during the refresh operation period, as shown in FIG. Incidentally, the refresh address is generated by updating the refresh address counter 17 in the main memory 12 in response to a refresh start signal from the memory access control circuit 16. Therefore, even during the refresh operation period, the memory bus 13 is not exclusively occupied by the refresh control circuit 11. That is, during the refresh operation period, the memory bus 13
completely open. In other words, in the configuration shown in FIG. 2, during the refresh operation period, the memory bus 13
could not be used effectively.

The present invention has been made in view of the above circumstances, and its purpose is to improve reliability without reducing system efficiency by diagnosing the memory bus, etc. during the refresh operation period when the memory bus is released. The objective is to provide an information processing device that can

Another object of the present invention is to ensure data randomness without requiring special hardware or software by using the contents held in the address register or data register as diagnostic data during bus diagnosis. The aim is to achieve efficient bus diagnosis.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram showing a schematic configuration of an information processing apparatus according to the present invention. In the figure, 21 is the CPU,
22 is a main memory. A storage section (not shown) of the main memory 22 is made up of a DRAM element, and therefore the main memory 22 needs to be refreshed. 23 is a refresh address counter built into the main memory 22. The refresh address counter 23 is updated in response to a memory start signal output from a memory access control circuit 28, which will be described later. The refresh address counter 23 generates a refresh address, that is, a row address.

24 ₁ to 24n are active modules such as channels, and 25 is a memory bus for connecting the active modules 24 ₁ to 24n, the CPU 21, and the main memory 22. 26
is a refresh control circuit. The refresh control circuit 26 outputs a refresh operation request signal REF within a certain period of time in order to retain data in the main memory 22. The refresh control circuit 26 is located at the same level as the active modules 24 ₁ -24n with respect to the main memory 22, as is well known. That is, the active modules 24 ₁ to 2
As seen from the 4n side, as already shown in FIG. 4, the memory access time (the exclusive time of the memory bus 25) after the memory access request is accepted is constant.

27 is a priority processing circuit. This priority processing circuit 27 receives memory access request signals REQ ₁ to 24n outputted from active modules 24 ₁ to 24n.
Based on REQn and the refresh operation request signal REF output from the refresh control circuit 26, requests are accepted according to predetermined priorities. When the priority processing circuit 27 receives a request, it outputs the module number information of the receiving destination, for example, as shown in FIG.
If the recipient is the refresh control circuit 26, a refresh acceptance signal RACK is output.
Note that in the priority processing circuit 27, the refresh control circuit 26 is generally connected to the active module 24.
The priority is set higher than ₁ to 24n. 2
8 is a memory access control circuit. The memory access control circuit 28 outputs a memory start signal or a refresh start signal to the main memory 22 in accordance with the output of the priority processing circuit 27.
control.

29 is a refresh acceptance signal line. The CPU 2
The refresh acceptance signal RACK output from the priority processing circuit 27 of the active modules 24 1 to 24 n is commonly input to each of the active modules 24 ₁ to 24 n. Further, 30 is a module number line. Module number information output from a module number counter (described later) of the CPU 21 via this module number line 30 is transmitted to each active module 24 ₁ to 24 .
Commonly input to n.

Next, referring to FIG. 7, the specific configuration of the main parts of the information processing apparatus of the present invention will be explained. Note that since the internal configuration of each active module 24 ₁ to 24n is basically the same, the active module 24n
1, and illustration and description of other modules will be omitted. In the figure, 31 is a memory address bus, and 32 is a memory data bus. Memory bus 25 consists of a memory address bus 31 and a memory data bus 32. 33 is CPU21
This is an address register that is provided in the memory and stores memory addresses. 34 is address register 3
3 is an output gate that outputs the held contents of 3 onto the memory address bus 31, and 35 is an input gate. Information on the memory address bus 31 is taken into the CPU 21 through the input gate 35. 36 is an output gate, and 37 is an input gate. Output gate 36
is provided in the CPU 21 and outputs the contents held in a data register (not shown) onto the memory data bus 32. Further, information on the memory data bus 32 is taken into the CPU 21 through the input gate 37.

Reference numerals 38 and 39 are output gates provided within the active module 24n, and 40 and 41 are input gates. Output gate 38 outputs, for example, a memory address for main memory 22 onto memory address bus 31, and output gate 39 outputs, for example, write information for main memory 22 onto memory data bus 32. On the other hand, the information on the memory address bus 31 is taken into the active module 24n through the input gate 40, and the information on the memory data bus 32 is taken into the active module 24n through the input gate 41.

42 is a turning gate. The return gate 42 transfers the information taken into the active module 24n through the input gate 40 to the output gate 3.
Turn back to 9.

43 and 44 are or gates. or gate 4
3 takes an OR between a gate signal obtained based on a microinstruction retrieved from a control storage unit (not shown) and the refresh acceptance signal RACK output from the priority processing circuit 27, and controls the opening of the output gate 34. Outputs the control signal. Similarly, the OR gate 44 performs an OR operation between a gate signal obtained based on a certain microinstruction and the refresh acceptance signal RACK, and outputs a control signal for controlling the opening of the input gate 37.

45 is a module number counter. The contents of this counter 45 indicate module numbers that designate the active modules 24 ₁ to 24 n. This counter 45 receives, for example, a refresh acceptance signal output from the priority processing circuit 27.
The count is updated by the trailing edge of RACK. The contents of the counter 45, that is, module number information, are as follows:
It is commonly input to each active module 24 ₁ to 24 n via a module number line 30 . 46
is a comparator. The comparator 46 compares the module number information inputted through the module number line 30 with a unique module number unique to the own module held in a register (not shown), and when a match is detected, the own module is selected. A selection signal SEL indicating this is output.

47 is an AND gate. and gate 47
are selection signal SEL and refresh acceptance signal RACK
is input, and the refresh acceptance signal is input during the period when the (active) selection signal SEL is input.
Output RACK as is. 48 and 49 are or gates. The OR gate 48 takes an OR between a gate signal obtained based on a certain microinstruction and the output of the AND gate 47, and outputs the input gate 4.
Outputs a control signal for 0 open control. Similarly, the OR gate 49 is a gate signal obtained based on a certain microinstruction and the AND gate 47.
A control signal for controlling the opening of the output gate 39 is output. Further, the folding gate 42 is controlled to open according to the output of the AND gate 47. 50 is a comparator. The comparator 50 compares the contents held in the address register 33 and the information inputted through the input gate 37 to detect a match.

Next, the operation of the configuration shown in FIGS. 5 to 7 will be explained. For example, assume that the contents of the counter 45 match the module number of the active module 24n. In this case, the comparator 46 in the active module 24n detects a match, and the comparator 46 outputs a selection signal SEL. In this state, the refresh operation request signal REF is output from the refresh control circuit 26,
It is assumed that the request is accepted by the priority processing circuit 27. As a result, the priority processing circuit 27 outputs a refresh acceptance signal RACK. Then, a refresh start signal is output from the memory access control circuit 28 to the main memory 22, and the area of the refresh address (row address) indicated by the refresh address counter 23 is refreshed. During this refresh operation, as explained in the conventional example, the active module 24
Memory access requests from ₁ to 24n are not accepted, and the memory bus 25 is completely released.

The refresh acceptance signal RACK output from the priority processing circuit 27 is input to the gate terminal of the output gate 34 via the OR gate 43. As a result, the output gate 34 is controlled to open, and the contents held in the address register 33 at that time are outputted onto the memory address bus 31 via the output gate 34. The contents held in the address register 33 are completely unrelated to the refresh acceptance signal RACK (refresh request from the refresh control circuit 26) and are clearly random data.

Further, the refresh acceptance signal RACK is also input to one input terminal of the AND gate 47. The selection signal SEL output from the comparator 46 is input to the other input terminal of the AND gate 47. The AND gate 47 remains open during the period when the selection signal SEL is input, and the refresh acceptance signal RACK input during this period is output as is. The refresh acceptance signal RACK outputted through the AND gate 47 is inputted to the gate terminal of the input gate 40 via the OR gate 48 . As a result, the input gate 40 is controlled to open, and the information on the memory address bus 31 is taken into the active module 24n via the input gate 40. Further, the refresh acceptance signal RACK outputted through the AND gate 47 is also inputted to the gate terminal of the return gate 42. As a result, the return gate 42 is controlled to open, and the active module 24n is connected via the input gate 40.
The information taken in is returned to the output gate 39.

The refresh acceptance signal RACK outputted through the AND gate 47 is also inputted to the gate terminal of the output gate 39 via the OR gate 49. As a result, the output gate 39 is controlled to open, and the information returned by the return gate 42 is transmitted to the output gate 39.
The data is output onto the memory data bus 32 via the memory data bus 32.
Further, the refresh acceptance signal RACK output from the priority processing circuit 27 is also input to the gate terminal of the input gate 37 via the OR gate 44. As a result, the input gate 37 is controlled to be open, and the information on the memory data bus 32 is transmitted through the input gate 37.
It is taken into the CPU 21. And CPU21
The information captured in the address register 33
The comparator 50 compares the contents held by the comparator 50 with the held contents.

As is clear, if the memory bus 25 (memory address bus 31 and memory data bus 32), each output gate 34, 39, each input gate 37, 40, etc. are normal, the information and address taken into the CPU 21 The contents held in the register 33 should match. Therefore, the memory bus 25 and the like can be diagnosed based on the comparison result of the comparator 50. Moreover, memory bus 25
As described above, since the diagnosis is performed during the refresh operation period, that is, during the period when the memory bus 25 is inevitably released, there is no fear that the efficiency of the memory bus 25 will decrease. In other words, according to this embodiment, bus diagnosis can be performed by effectively utilizing the wasted time when the memory bus 25 is idle.

Further, according to this embodiment, unlike a data check based on a validity check method, for example, all bits of data are directly compared on a one-to-one basis, so that the integrity of bus data can be reliably detected. Furthermore, the content held in the address register 33 as diagnostic data is completely random data, allowing extremely reliable bus diagnosis (detection of data integrity). Furthermore, since random data (diagnosis data) can be obtained without using special hardware or software, bus diagnosis can be performed at extremely low cost.

Note that in the above embodiment, the address register 33
Although the case has been described in which the contents held in a data register (not shown) are used as diagnostic data, the same effect can be obtained even if the contents held in a data register (not shown) are used as diagnostic data. In this case, the data movement will be opposite to that of the previous embodiment, and the direction of the folding gate 42 will need to be changed. Further, a bidirectional gate may be used as the return gate, thereby enabling bidirectional data checking. Furthermore, the same implementation is possible even if the memory bus is a DMA (direct memory access) bus. Furthermore, in the embodiment described above, the refresh acceptance signal RACK outputted from the priority processing circuit 27 is used as the bus diagnosis timing.
The timing signal is not limited to this, and any timing signal that is output during the refresh operation period may be used.

As described in detail above, according to the information processing apparatus of the present invention, highly reliable bus diagnosis can be performed with an extremely simple configuration and without reducing system efficiency.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing a schematic configuration of a conventional information processing device, FIGS. 3 and 4 are timing charts for explaining the features of FIGS. 1 and 2, respectively, and FIG. 5 is a schematic configuration diagram showing one embodiment of the information processing device of the present invention, FIG. 6 is a functional explanatory diagram of the priority processing circuit in the above embodiment,
FIG. 7 is a block diagram specifically showing the main structure of the above embodiment. 1, 12, 22...Main memory, 2, 11, 26
...Refresh control circuit, 3, 15, 21...
Central processing unit (CPU), 4, 13, 25...Memory bus, 5 ₁ ~ 5n, 14 ₁ ~ 14n, 24 ₁ ~
24n...Active module, 6, 16, 2
8...Memory access control circuit, 29...Refresh acceptance signal line, 30...Module number line, 33...Address register, 34, 36, 3
8, 39...Output gate, 35, 37, 40, 4
1...Input gate, 42...Return gate, 4
6,50... Comparator.

Claims (1)

[Claims] 1 A main memory with dynamic random access memory and one or more active modules that access this main memory, assigned a unique module number, and located at the same level as this active module. A refresh control circuit, and a memory access control for accepting requests to the main memory according to a predetermined priority based on a refresh request issued from the refresh control circuit and a memory access request issued from the active module. a central processing unit having a circuit; a memory bus for connecting the central processing unit, the active module, and the main memory;
output means for outputting the content held in the address register or data register in the central processing unit at that time onto the memory bus when a refresh request is accepted by the refresh control circuit; selection means for selecting one of the memory buses; and return means for returning the information on the memory bus to the active module selected by the selection means when a refresh request is accepted by the refresh control circuit; a transfer means for transferring the returned information to the central processing unit via the memory bus; and a detection means for detecting a match between the transferred information and the contents held in the address register or the data register. An information processing device comprising: