JPS6238902B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a digital image processing circuit for reproducing images with high density. Conventionally, high-density reproduction of images has been carried out using software (programs) using experimental equipment or general-purpose simulation systems for research. However, such conventional devices require time to perform processing based on programs. Further, since a minicomputer or a microcomputer equivalent to the minicomputer is used, the cost is high, and there are problems in that the operator must be a computer expert. The present invention has been made to solve these conventional problems, and provides a digital image processing circuit that has a simple and inexpensive configuration, can improve image quality, and can be easily used without specialized knowledge. With the goal. In order to achieve this object, the present invention provides a scanner unit that performs line scanning of an image and outputs it as pixels, a shift register that stores image data obtained from this scanner unit, and a plurality of predetermined bit outputs of this shift register. a read-only memory that receives the output of this comparator and the output of the shift register as address data and outputs output pixel data; It is equipped with an output buffer circuit that outputs an output at a timing, and a plotter section that outputs an image according to the output of the output buffer circuit, and reproduces an image with high density. Embodiments of the present invention will be described below with reference to the accompanying drawings. First, the interpolation algorithm of the high-density image reproduction method to which the embodiment of the present invention is applied will be explained. Figure ₁ shows the columns _of input pixels. n pixels (in this embodiment, n=1680; only three are shown in the figure) are lined up in the direction. Assume that a line scan up to column _X3 is currently being performed and the results are stored. At this time, it is assumed that the pixel S _q is the processing target and four pixels O ₁ , O ₂ , O ₃ , and O ₄ are outputted for the input pixel S _q as shown in FIG.
It is assumed that the input pixel is represented by 1 pixel and 5 gradations (3 bits), and the output pixel is represented by 1 pixel and 2 gradations (1 bit). The correspondence between input pixels and output pixels is set as shown in Table 1.

[Table] (In Table 1, the input pixel becomes blacker as the number of density levels increases, and the output pixel density is 0, white, 1
indicates black. ) That is, input pixel S _q
In addition to considering the density of the input pixel S _q , the density of the input pixels S ₁ and S ₃ located above and below the input pixel S q is compared, and the density of the input pixels S ₂ and S ₄ located to the left and right of the input pixel S _q is compared. This determines the density of the output pixels O ₁ , O ₂ , O ₃ , O ₄ , for example, the input pixel S _q
When the density level of is 1, the density of input pixel S ₁ is less than the density of S ₃ , and the density of input pixel S ₂ is greater than or equal to the density of S ₄ , the output pixel O ₁ ,
The concentrations of O ₂ , O ₃ , and O ₄ are assumed to be 0, 0, 1, and 0, respectively. FIG. 3 shows an embodiment of an image processing circuit according to the present invention. Here, we will perform image processing on an A4 size manuscript. In this example, the input gate
IG uses a scanner system to line-scan the image and converts the analog data obtained through A/D conversion (5-value 3
The data that has been converted into bits is input serially for each line. The output terminal of the input gate IG is connected to the input terminal of the shift register SRA. As shown in FIG. 4, in the shift register SRA, 2 bits of the first line, 1680 bits of the second line, and 1679 bits of the third line are serially connected, and among them, the input pixels S ₁ to _{S 4} of FIG. The 1st, 1680th, 3361st, 1682nd, and 1681st bits corresponding to Sq and _Sq can be output in parallel. (Note that the value of 1680 bits comes from the fact that if we assume that 8 lines per 1 mm are scanned for image reproduction of an A4 size original, 210 times as many bits as that are required.)The input data is 3 Since it is a bit, three of the configurations shown in FIG. 4 are overlapped to form a three-dimensional memory system as shown in FIG. If the coordinates are determined as shown in Figure 5, Figure 4 shows the xy plane. Table 2 shows the input pixels S _q , S ₁ to _{S 4} in the coordinate system of FIG.

[Table] Shift register SRA is 2+1680 in one plane
There is a capacity of +1679=3361 bits, so overall
It has a capacity of 3361 x 3 = 10083 bits. Of the 3-bit density data of each input pixel S _q , S ₁ to _{S 4} that is output in parallel from the shift register SRA, S _q is directly input to the address pointer ADP, and the density data of input pixels S ₁ and S ₃ are input directly to the address pointer ADP. ,and
The concentration data of S ₂ and S ₄ are input to the first comparison section and the second comparison section of the comparator COM, respectively, in order to compare these values. The output of the first comparison section of the comparator COM becomes 1 when S ₁ ≧S ₃ , and the output of the second comparison section becomes 1 when S ₂ ≧S ₄ . comparator
The two output terminals of COM are connected to the input terminal of address pointer ADP, and the address pointer
ADP ultimately shows the density data of input pixel S _q 3
A bit signal, a signal indicating the density comparison result of input pixels S ₁ and S ₃ , and a signal indicating the density comparison result of input pixels S ₂ and S ₄ are input. The address pointer ADP is a comparator with a signal indicating the density level of the input pixel _Sq , as shown in Figure 6.
5-bit latch 61 that receives the COM output signal
and a 1-bit flip-flop 62. Due to the nature of the algorithm, the number of output data is four times the number of input data (twice the speed of the clock signal), so the clock signal CL2 that sets the output speed in Figure 6 is set to the input speed as shown in Figure 7. Clock signals CL1 and 2 to set
It has twice the speed. Flip-flop 62 serves to produce the lowest bit of the current address. That is, the 3-bit data indicating the density of the input pixel S _q , the signal indicating whether S ₁ ≧S ₃ , and the 5-bit signal indicating whether S ₂ ≧S ₄ are _q (bit 2 to bit 0), S ₁ ≧
Read-only memory arranged like S ₃ , S ₂ ≧ S ₄
It is configured to specify the address of the ROM, and one bit is added to the lower order for the purpose of doubling the speed. After all, the address pointer ADP
The output has a 6-bit configuration. The read-only memory ROM serves as a conversion table to implement Table 1. That is, the 6-bit output of the address pointer ADP is used as addresses _A0 to _A5 , and the 2-bit data _D1 is output at a timing slightly later than the timing at which the flip-flop 62 is operated in response to the clock signal CL2 applied via the delay circuit DT. It outputs D ₀ . D ₀ corresponds to output pixels O ₁ and O ₂ in FIG. 2, and D ₁ corresponds to output pixels O ₃ and O _4, respectively. The output data D ₁ and D ₀ are specified according to Table 1, but the read-only memory ROM
This can be achieved by configuring the contents as shown in FIG. The read-only memory ROM has a configuration of 50 (octals) x 2 (bits) = 80 (bits). The output _D1 of the read-only memory ROM is input to the shift register SRB, and the shift register SRB can handle eight A4-sized manuscripts/
When scanning in mm, it is configured as a 210 x 8 x 2 = 3360 bit serial-in, serial-out shift register. The output to the printer system is 2 lines for every 1 line of input, and the 9th
As shown in the figure, after one line of data is output by D ₀ , the data stored in the shift register SRB before the next one line is input.
It is necessary to ensure that D ₁ is output. Shift register SRB is an output buffer register for this purpose. The output _D1 of the register and the output _D0 of the read-only memory ROM are supplied to the plotter system via the output gate OG. In the embodiment of the present invention having such a configuration, the density level of the input pixel _Sq is 1, the density level of the input pixel _S1 is higher than the density level of the input pixel _S3 , and the density level of the input pixel S2 is higher than the density level of the input pixel _S2 . If the concentration level S of ₄ is smaller than ₄ , "001" is output from the output line indicating S _q of the shift register SRA, and the comparator
The output of the first comparison section of COM becomes "1", the output of the second comparison section becomes "0", the input of the address pointer ADP becomes "00110", and the input of the address pointer ADP becomes "00110".
The outputs A ₅ , A ₄ , A ₃ , A ₂ , A ₁ , A ₀ are “00110X”
becomes. (Here, X is a bit generated by the flip-flop 62.) When the clock signal CL1 is input, the flip-flop 62 is set and its output becomes "1", and the effective address output from the address pointer ADP becomes 001101. Become. Next, when the clock signal CL2 is input, the flip-flop 62 is reset and its output becomes 0, and the effective address output from the address pointer ADP becomes 001100. Since the clock signal CL2 delayed by the predetermined time by the delay circuit DT acts as a read clock signal for the read-only memory ROM, the data 00 specified by the address 001100 is output from the read-only memory ROM _. Output as ₀ . Output data D ₁ (=0) passes through shift register SRB, and output data D ₀ (=
0) are output as they are to the plotter system via the respective output gates OG. Clock signal CL2 is the second clock signal CL1.
Since it has twice the speed, the next clock signal CL1
Clock signal CL2 is input before
Flip-flop 62 is set and read-only memory ROM outputs data 01 specified by address 001101. The first output data 00 corresponds to the output pixels O ₃ and O ₁ , and the current output data 01 corresponds to the output pixels O ₄ and O ₂
corresponds to In other words, it is possible to obtain output pixels according to Table 1. Similarly, the output pixels set in Table 1 can be obtained for various input pixel densities. FIG. 10 shows the configuration of an image processing system using the embodiment according to the present invention. This image processing system consists of a scanner system, an image processing system, a plotter system, and a control system for controlling these three systems. The scanner system includes a line scanner 31 that scans a document at a density of 8 lines/mm and outputs an image signal under the control of a system control unit 32 using a microcomputer, and an A/ It consists of an A/D converter that performs D conversion and outputs pixel signals (corresponding to the above S ₁ to S ₄ and S _q ). The image processing system is composed of the pixel processing circuit shown in FIG. The plotter system consists of a plotter 35 which receives data D ₁ and D ₀ output from a pixel processing circuit 34 under the control of a system control section 32 and plots output pixels at a density of 16 lines/mm. By adopting such a configuration, high-density image reproduction can be performed and image quality can be improved. FIG. 11 shows the use of the above-described embodiment of the present invention in a facsimile machine. In FIG. 11, on the transmitting side, a scanner 41 scans a document image, an A/D converter 42 converts the resulting image signal into a digital signal, and this digital signal is transmitted via an image compression circuit 43 and a modem 44. sent to the receiving side. On the receiving side, the image processing circuit 46, which is the embodiment of the present invention described above, receives digital image data (input pixels) via the modem 45, outputs output data D _{1 and D 0, and outputs the output data D 1} and D ₀ to the plotter 47.
reproduces images with high density. In the above embodiment, the resolution of the line scanner is 8.
lines/mm, and the resolution of the output plotter was set to 16 lines/mm, but if the following relationship is satisfied: (resolution of output plotter) = (resolution of line scanner) x 2, by changing the frequency of the clock signal, the above The example can be used as is. Further, the present invention can be applied to any device in which the output pixel density is higher than the input pixel density. As is clear from the above description, the present invention has the effect of being able to reproduce images with high density and improving image quality with a simple and inexpensive configuration. Further, the image processing circuit according to the present invention has the advantage that it can be used not only by experts but also by general users.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing input pixels, FIG. 2 is an explanatory diagram showing the relationship between input pixels and output pixels, FIG. 3 is a three-dimensional block diagram of an image processing circuit according to the present invention, and FIG. The diagram shows the shift register in Figure 3.
A block diagram showing the detailed configuration of the SRA, Figure 5 is an explanatory diagram showing the configuration of the shift register SRA in three dimensions, and Figure 6 is the address pointer ADP of Figure 3.
A block diagram showing an example of a configuration, FIG. 7 is a time chart showing clock signals CL1 and CL2 input to the address pointer ADP in FIG. 6, and FIG. 8 shows the storage contents of the read-only memory in FIG. 3. Figure 9 shows the input signal and output signal D ₀ , D ₁
10 is a block diagram showing an example of the configuration of an image processing system constructed using the embodiment shown in FIG.
1 is a system configuration diagram showing a facsimile system using the illustrated embodiment; FIG. S ₁ , S ₂ , S ₃ , S ₄ , S _q ...input pixel, O ₁ , O ₂ ,
O ₃ , O ₄ ... Output pixel, IG ... Input gate, SRA
...Shift register, COM...Comparator, ADP...
...address pointer, ROM...read-only memory, SRB...shift register, OG...output gate, 61...latch circuit, 62...flip-flop.

Claims (1)

[Claims] 1. A scanner unit that performs line scanning of an image and outputs n pixel data as one column of image data, a shift register that sequentially stores the pixel data obtained from this scanner unit, and a pixel data stored in this shift register. Regarding the pixel, the p-nth pixel data and the p+nth pixel data are compared to obtain the first result, and the p-1th pixel data and the p+1th pixel data are compared to obtain the second result. a comparator that obtains the result of the p-th pixel, and a ROM that receives the pixel data of the p-th pixel, the first result, and the second result as address data and outputs four small pixel data for the p-th pixel. and,
An output for dividing the four small pixel data into two first half small pixel data and two second half small pixel data, and outputting the first half small pixel data and the second half small pixel data separated by a cycle of 2n small pixel data. buffer circuit and the output from this output buffer circuit.
A digital image processing circuit comprising: a plotter section that forms an image using 2n small pixel data as one column of image data.