JPS6238937A - Protection digit processing system for floating point arithmetic - Google Patents

Abstract

PURPOSE:To decrease arithmetic steps of firmware and to shorten an execution time by making a protection bit correction through hardware. CONSTITUTION:Mantissas of two operands to be added or subtracted are set in operand registers 1 and 2. Exponents of the two operands are compared for digit matching and when it is decided that, for example, the mantissa in the operand register 2 is shifted to right, a selector 4 is so controlled to select the low-order digit input. The low-order bits of the mantissa shifted and outputted from the least significant digit of the operand register 2 are shifted and inputted to a protection digit register 5 from the side of a G bit, so a rounding carry logic circuit 6 makes correction of (00)+(G,R) in addition and (00)-(G,R) in subtraction as to G, R, and S bits in the protection digit register 5 to generate a rounding carry on the basis of the results, thereby applying the carry to an ALU.

Description

[Detailed Description of the Invention] [Summary] Normally, when performing floating-point addition and subtraction, a shift is performed to align the digits of the two operands.

At that time, the precision of the effective digits is guaranteed by shifting by the length of the effective digit plus the guard digit and after 9 rounds using the data of the guard digit, but the data of the guard digit is used during addition and subtraction. Since different processing is required depending on the time, this can be easily and quickly executed using a dedicated hardware mechanism.

[Industrial application field]

The present invention relates to an arithmetic unit for a computer, and particularly to a method for processing guard digits in floating point arithmetic.

(Prior art) Data in floating point format consists of an exponent part and a mantissa part. In the case of addition and subtraction, when the exponent parts of two operands are different, the mantissa part is added to make them match. Shift correction (digit alignment) is required.

For mantissa shift correction, it is sufficient to prepare a register with a length twice as long as the effective digits, but because the amount of hardware such as ALU (arithmetic operation unit) increases, the protection bit length is usually set to the effective digit length. This is replaced by adding a three-digit bit called a node.

FIG. 5 is an explanatory diagram of protection bits. G.R.

S represents three bits that constitute the protection bit.

G bit (Guard bit), R bit (Round bit), S bit (S bit) respectively.
called a "ticky bit".

When shifting the mantissa to the right, the lower bits of the mantissa shifted out from the LSB are sequentially shifted into each of the G, R, and S bits. S-bi-node accumulates previous input bits. That is, if there is even one "1" in a bit lower than the R bit, it becomes "1" and is held until it is reset by a microinstruction. Further, the S bit is separated from the shift operation in the case of a left shift, and "0" is input to the R bit.

In addition and subtraction of floating point numbers, in order to guarantee accuracy within the significant digits, the operation is performed by adding the number of digits of the protection bits mentioned above to the number of significant digits, and after the operation is completed, the calculation is performed according to a certain logic based on the value of the protection bits. Generates a rounding carry,
Rounding is done.

FIG. 6 is a diagram showing the states of the protective vias (G, R, and S) during addition. A, B are operands +”I+82 is A, B
The exponent parts, f, , f, represent the mantissa parts of A and B, respectively.

Here, if e is >82, then in order to match the exponent part e2 of operand B to el, the mantissa part f2 of B is set to (e
l-02) It is necessary to shift the digits to the right to align the digits. As a result, the protection bits G, R, and S of operand A are (
000) but.

The protection bits G, R, and S of operand B take predetermined values based on the lower (el-ez) bits shifted out from the LSB of f2.

In the case of such addition, A's (G, R, 5-OOO
) is (G, R, S) of 10B, so rounding can be performed using B's G, R, and S as they are.

On the other hand, in the case of subtraction, A's (G, R.

5=OOO) - B's (G, R, S) operation is required, and the firmware allows operand B's (G, R, S
) correction, specifically (00)-(G.

R) is complemented (S is not complemented because it indicates the presence or absence of 1'' in the lower bits).

By the way, in a computer that uses the floating point addition/subtraction method with such protection bit correction, the AI and U for significant digit calculations are
Subtraction correction of the protection bits is normally performed by firmware using a flag register for the protection bits.

FIG. 7 shows the processing flow of addition and subtraction using the method described above. After reading the operands, performing exponent operations, and adjusting the mantissa digits, the case of addition and the case of subtraction are separated.
In case of addition, add mantissa.

Rounding is performed in the order of result storage, but in the case of subtraction, mantissa subtraction and guard bit correction are performed separately, and then rounding is performed.
Indicates that the results will be stored.

[Problem that the invention seeks to solve]

In conventional floating-point addition and subtraction processing that uses protection bits, the protection bits are corrected by firmware in the case of subtraction, so the calculation time is longer and the control is more complex than in addition. Ta.

[Means for solving problems]

The present invention uses an ALU that has only the word length of the mantissa to perform correction operations for guard bits when performing addition and subtraction.

By providing a dedicated hardware mechanism separate from the ALU, without relying on firmware processing.

This is intended to speed up processing.

FIG. 1 is a diagram showing the basic configuration of the present invention.

In fig.

1 and 2 are operand registers that hold input operands.

3 is an operand register, and an ALU (arithmetic unit) that performs arithmetic operations such as addition and subtraction on the input operand 2.

4 is a selector for selecting one of operand registers 1 and 2;

5 is a protection digit register that holds G, R, and S protection bits.

6 is a rounding carry logic circuit that performs subtraction correction of protection bits and rounding carry generation.

[Effect]

The mantissas of the two operands to be added or subtracted are set in the operand register 1.2.

To align the digits, compare the exponents of the two operands,
For example, when it is decided to shift the mantissa of the operand register 2 to the right, the selector 4 is controlled to select the lower manual input.

The lower bits of the mantissa shifted out from the least significant digit (LSB) of operand register 2 are sent to guard digit register 5.
The shift from the G-bit side to the G-bit side is performed manually.

The round carry logic circuit 6 inputs G, R,
For S bit, (00) + (c,
R), and then performs the correction of (00)-(G,R) when executing the subtraction, and generates a round carry based on the result,
Apply to ALU.

FIG. 2 is a processing flow of addition and subtraction using the inventive formula. Operand read as shown.

After exponent calculation and mantissa digit alignment are performed sequentially, in the case of addition, mantissa addition, rounding, and result storage are performed, and in the case of subtraction, mantissa subtraction, rounding, and result storage are performed.

In this way, correction of the protection bits in the case of subtraction is performed in hardware, reducing the time required for processing the protection bits that was conventionally performed in firmware, and making it possible to perform rounding processing for additions and subtractions that are almost the same. It can be done in time.

〔Example) FIG. 3 is a block diagram of one embodiment of the present invention.

In the figure, 1 and 2 are operand registers.

3 is the ALU, 4 is the selector, and 5 is the guard digit register.

6 is a rounding carry logic circuit, 7 is a protection focus correction circuit, 8
9 represents a rounding carry generation circuit, 9 represents a selector, and 10 represents an internal bus. Further, CNTL-1 to CNTL-4 are control signals given based on microinstructions.

CNTL-1 is given by a microinstruction that compares the exponent part of the operand stored in the operand register and the operand register 2 to determine its magnitude. For example, the operand register having the smaller operand is controlled to always be 11HR.

CNTL-2 is provided to control writing to guard digit register 2. For example, when the lower bits of the mantissa shifted out from the operand register or 2 are shifted in, or the guard bits G, R, and S read from the guard digit register 2 are rounded to the carry logic circuit 6.
It is given when rewriting the result corrected by the protection bit correction circuit 7 into the protection digit register 2.

CNTL-3 connects the protection bit correction circuit 7 and the rounding carry generation circuit 7 in the rounding carry logic circuit 6 to
Given for sequential functionalization.

CNTL-4 selects the round carry Rc generated by the round carry generation circuit 7 as the carry input C4n of the ALU 3 in the selector 9, or selects the carry C from the lower data.
This is given to instruct whether to select the fixed value "0" or "1".

Under the control of these control signals CNTL-1 to CNTL-4, a protection pill is generated based on the lower bits of the mantissa shifted out from one of the operand registers.
-G, R, and S are first read out from the guard digit register 5 to the guard bit correction circuit 7, corrected only during subtraction, and written back to the guard digit register 5.

Next, the corrected protection bits (G, R, and S) are read out from the protection digit register 5 to the rounding carry generation circuit 8 and used to generate the rounding carry Re.

The generated round carry Re is input to Cin in accordance with the calculation timing of the ALU 3, and the rounded calculation result is output to the internal bus 10.

FIG. 4 shows a logic table of the protection bit correction circuit 7. Depending on whether the operation is addition (a+J+J) or subtraction (sub), and whether it is a hold designation or an update designation, GR3 as shown in Figure 9
Perform the conversion.

〔Effect of the invention〕

According to the present invention, since the protection bit correction is performed by hardware, it is possible to omit the protection bit correction step specific to the subtraction operation, so that the number of firmware calculation steps and the execution time can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, and FIG. 2 is a processing flow when performing addition and subtraction according to the method of the present invention. 3 is a block diagram of one embodiment of the present invention, FIG. 4 is an explanatory diagram showing a logic table of the protection bit correction circuit in the embodiment of FIG. 3, and FIG. 5 is an explanatory diagram showing the configuration of the protection bit, FIG. 6 is an explanatory diagram showing the state of the protection bit during addition, and FIG. 7 is a processing flow when performing addition and subtraction using the conventional method. In FIG. 1 and 2: Operand register 3: ALU 4; Selector 5: Guard digit register 6: Rounding carry logic circuit Patent applicant Panama Acom Co., Ltd. Representative patent attorney Fumihiro Hase (one other person) ri sweat 11 power ￥ JllZ] Fuuka 9 support fire example groove kusu 3"-') n7- η2 country 1 heavy bee h'+t, ia end then value ball village tea ゛j and power 4 flash addition training Prostitute 1 to ° Tsunt calendar L 11 U1 Reiki i- Caution 4b, ■ (Raku% 40,000 reparation mouth IE ``-''--''-1: Hieshit 7 彊1*:
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Claims (1)

[Claims] In a computer that executes floating point operations using an arithmetic operation unit (3) and a guard digit register (5), subtraction correction of the guard bit set in the guard digit register (5) is provided. A dedicated round-carry logic circuit (
6), and when performing floating point subtraction, after aligning the mantissa digits, the mantissa subtraction operation is performed, and at the same time the round-carry logic circuit (6) is activated.
A guard digit processing method in floating point arithmetic, characterized in that a guard bit set in a guard digit register (5) is subtracted and corrected to generate a round carry.