JPS6239816B2 - - Google Patents

Info

Publication number
JPS6239816B2
JPS6239816B2 JP56158993A JP15899381A JPS6239816B2 JP S6239816 B2 JPS6239816 B2 JP S6239816B2 JP 56158993 A JP56158993 A JP 56158993A JP 15899381 A JP15899381 A JP 15899381A JP S6239816 B2 JPS6239816 B2 JP S6239816B2
Authority
JP
Japan
Prior art keywords
pattern
patterns
memory
defect
actual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56158993A
Other languages
Japanese (ja)
Other versions
JPS5860538A (en
Inventor
Shogo Matsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56158993A priority Critical patent/JPS5860538A/en
Publication of JPS5860538A publication Critical patent/JPS5860538A/en
Publication of JPS6239816B2 publication Critical patent/JPS6239816B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Description

【発明の詳細な説明】 本発明はパターン検査方法に係り、特に二つの
実パターンの映像信号を比較してパターンの良否
を判定するパターンの比較検査方法の改良に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern inspection method, and more particularly to an improvement in a pattern comparison inspection method that compares video signals of two actual patterns to determine the quality of the pattern.

半導体装置の製造等に使用されるフオトマスク
を検査する装置に、フオトマスク上に整列形成さ
れている複数個の同種実パターンを、二個づつ順
次比較照合して検査するパターン表面検査装置が
ある。この方式に於ては、二個の実パターンの映
像信号同士を重ね合わせ、これら映像信号の差信
号を検出し、該差信号の有無によりパターンの良
否が判定されていた(差信号が検出されたパター
ンは不良判定される)。
2. Description of the Related Art As an apparatus for inspecting photomasks used in the manufacture of semiconductor devices, there is a pattern surface inspection apparatus that sequentially compares and inspects a plurality of real patterns of the same type formed in alignment on a photomask two by two. In this method, the video signals of two real patterns are superimposed, the difference signal between these video signals is detected, and the quality of the pattern is determined based on the presence or absence of the difference signal (if the difference signal is detected, patterns are judged to be defective).

しかし上記従来の方式に於ては、例えばマスク
基板上に複数の同種実パターンをステツプ・アン
ド・リピート法等により投影配列する際の、ステ
ージ送りの機械的誤差や振動等のために実パター
ン間の相対位置がずれて形成されている場合に
は、二個の実パターンの映像信号を重ね合わせた
際に、該位置ずれ部に相当する差信号が検出さ
れ、被検査実パターンはパターン内に欠陥がない
場合でも不良と判定されるという問題があつた。
However, in the above-mentioned conventional method, for example, when projecting and arranging multiple real patterns of the same type on a mask substrate by the step-and-repeat method, mechanical errors and vibrations in stage feeding cause problems between the real patterns. If the relative position of the actual pattern is shifted, when the video signals of the two actual patterns are superimposed, a difference signal corresponding to the positional shift will be detected, and the actual pattern to be inspected will be detected within the pattern. There was a problem in that even if there were no defects, it was determined to be defective.

本発明は上記問題点に鑑み、標準とする実パタ
ーンと被検査実パターン間の相対的な位置ずれに
起因する差信号即ち凝似欠陥信号をパターン内の
欠陥によつて生ずる本来の欠陥信号と区別して良
否の判定を行う比較検査方法を提供し、検査精度
を向上せしめることを目的とする。
In view of the above-mentioned problems, the present invention distinguishes a difference signal caused by a relative positional shift between a standard actual pattern and an actual pattern to be inspected, that is, a condensed defect signal, from an original defect signal caused by a defect in the pattern. The purpose of the present invention is to provide a comparative inspection method for distinguishing and determining pass/fail, and to improve inspection accuracy.

即ち本発明は、基準とする実パターンと被検査
実パターンの映像信号パターンを重ね合わせて、
両映像信号パターンの差信号パターンを検出し、
該差信号パターンの有無により欠陥パターンを判
別するパターン検査方法に於て、上記差信号のう
ちで、基準とする映像信号パターンの対向する二
辺の同じ側にそれぞれ接し、且つ該接辺と等しい
長さを有する一様な幅の差信号パターンを、他の
差信号パターンと区別して、欠陥表示対象から除
外する工程を有することを特徴とする。
That is, the present invention superimposes the video signal patterns of the reference real pattern and the real pattern to be inspected,
Detects the difference signal pattern between both video signal patterns,
In a pattern inspection method for determining a defective pattern based on the presence or absence of the difference signal pattern, among the difference signals, the difference signal is in contact with the same side of two opposing sides of the reference video signal pattern, and is equal to the tangent side. The present invention is characterized in that it includes a step of distinguishing a difference signal pattern having a length and a uniform width from other difference signal patterns and excluding it from defect display targets.

以下本発明を実施例について、第1図に示す本
発明の方法の一実施例に用いるパターン検査装置
に於ける主要構成ブロツク図、第2図a乃至cに
示す一実施例に於ける工程上面図及び、第3図に
示す他の一実施例に於ける工程上面図を用いて詳
細に説明する。
Examples of the present invention will be described below. Fig. 1 is a block diagram of the main configuration of a pattern inspection apparatus used in an embodiment of the method of the present invention, and Figs. A detailed explanation will be given using the drawings and a top view of the process in another embodiment shown in FIG.

本発明の方法に用いるパターン検査装置は例え
ば第1図に示すように、被検査マスク1を固定す
るステージ2、一対の光学系(顕微鏡)3a,3
b光電変換装置を具備した一対の映像信号パター
ン形成部4a,4b、一対の信号二値化部5a,
5b、一対の画面メモリ形成部6a,6b、一対
の画面メモリ外形認識部7a,7b、メモリパタ
ーン外形比較部8、欠陥メモリ外形認識部9、欠
陥メモリ形状検査部10、不良信号出力部11、
出力ゲート12を有してなつている。
For example, as shown in FIG. 1, the pattern inspection apparatus used in the method of the present invention includes a stage 2 for fixing a mask 1 to be inspected, a pair of optical systems (microscopes) 3a
b A pair of video signal pattern forming units 4a, 4b equipped with a photoelectric conversion device, a pair of signal binarizing units 5a,
5b, a pair of screen memory forming parts 6a and 6b, a pair of screen memory outline recognition parts 7a and 7b, a memory pattern outline comparison part 8, a defective memory outline recognition part 9, a defective memory shape inspection part 10, a defective signal output part 11,
It has an output gate 12.

該装置に於ては被検査マスク1上に複数個整列
形成されている同種類のマスク実パターンが、順
次一対の光学系3a,3bに下に移動されて比較
検査がなされる。第1図はマスク実パターンAを
基準パターンとしてマスク実パターンBの比較検
査を行つている状態を示しており、この状態に於
て光学系3a,3bによつて投影されたマスク実
パターンA及びBの光学像を、それぞれ先ず映像
信号パターン形成部4a,4bに於てアナログ映
像信号パターンに変換する。次いで該アナログ映
像信号パターンはそれぞれ信号二値化部5a,5
bを介して二値化し、画面メモリ形成部6a,6
bに於てそれぞれのパターンの画面メモリを形成
する。この状態を表わしたのが第2図aで、図中
Maは基準となるマスクパターンAの画面メモリ
パターン、Mbは被検査マスクパターンBの画面
メモリパターンを示している。次いでこれら画面
メモリパターンはそれぞれ画面メモリ外形認識部
7a,7bに於てその輪郭を1〔メモリビツト〕
の幅で認識する。この状態を表わしたのが第2図
bで、図中Caは基準となるマスク実パターンA
の外形(輪郭)メモリパターン、Cbは被検査マ
スク実パターンBの外形(輪郭)メモリパターン
を示す。次いでこれら外形メモリパターンをメモ
リパターン外形比較部8に於て重ね合わせて比較
し両外形メモリパターンCa,Cb間の差異を検出
し、その差異を欠陥と見做し、欠陥外形認識部9
に於て該欠陥の外形メモリパターンを認識する。
この状態を示したのが第2図cで、この際マスク
実パターンの内部には欠陥がなく、A、B実パタ
ーンの相対位置がX方向のみに僅かにずれている
場合には、欠陥の外形メモリパターンD1,D2
は、基準とするマスクパターンAの外形メモリパ
ターンCAのY方向に向かう二辺の全域に接して
その片側に一定の幅で表われる。従つて基準外形
メモリCAのX,Yそれぞれの方向に向く辺の長
さをxc1,xc2及びyc1,yc2とし、欠陥の外形パ
ターンD1,D2の長さをそれぞれyd1,yd2、その
幅をxd1,xd2、その間隔をxsとすると、xs
c1(但しxc1=xc2)、yd1=yc1、yd2=yc2
d1=xd2となる。なおこれらの点は欠陥形状検
査部10に於て、欠陥の外形メモリパターン
D1,D2と基準となるマスクパターンAの外形メ
モリパターンCaとを対比して確認する。なお第
2図cには理解を容易にするために、マスク実パ
ターンAの画面メモリMaとマスク実パターンB
の画面メモリMbを重ね合わせた状態が附記して
あり、D′1,D′2はそれぞれD1,D2に囲まれた領域
を示している。そして欠陥の外形メモリパターン
が上記を満足している場合には、該外形検査部1
0からゲート部12にOFF信号を送り、既にメ
モリパターン外形比較部8からの異常の指令によ
り不良信号出力部11から出力されている不良信
号を、該ゲート部12に於てOFFとする。
In this apparatus, a plurality of mask actual patterns of the same type, which are formed in alignment on the mask 1 to be inspected, are sequentially moved down to a pair of optical systems 3a and 3b for comparative inspection. FIG. 1 shows a state in which a comparison inspection is performed on a mask actual pattern B using the mask actual pattern A as a reference pattern, and in this state, the mask actual pattern A and the mask actual pattern B projected by the optical systems 3a and 3b are shown. The optical images of B are first converted into analog video signal patterns in video signal pattern forming sections 4a and 4b, respectively. Next, the analog video signal patterns are passed through signal binarization units 5a and 5, respectively.
The screen memory forming portions 6a, 6
In step b, a screen memory of each pattern is formed. This state is shown in Figure 2a.
Ma indicates the screen memory pattern of mask pattern A as a reference, and Mb indicates the screen memory pattern of mask pattern B to be inspected. Next, the outlines of these screen memory patterns are determined by 1 [memory bit] in the screen memory outline recognition units 7a and 7b, respectively.
It is recognized by the width of . This state is shown in Figure 2b, where Ca is the reference mask actual pattern A.
Cb indicates the outer shape (contour) memory pattern of the mask actual pattern B to be inspected. Next, these external memory patterns are superimposed and compared in a memory pattern external shape comparison section 8, and a difference between both external memory patterns Ca and Cb is detected.The difference is regarded as a defect, and the defect external shape recognition section 9
In this process, the external memory pattern of the defect is recognized.
This state is shown in Fig. 2c. In this case, if there is no defect inside the mask actual pattern and the relative positions of the A and B actual patterns are slightly shifted only in the X direction, there is a defect. External memory pattern D 1 , D 2
appears with a constant width on one side of the reference mask pattern A, which is in contact with the entire two sides of the external memory pattern C A in the Y direction. Therefore, the lengths of the sides facing the X and Y directions of the reference contour memory C A are x c1 , x c2 and y c1 , y c2 , and the lengths of the defect contour patterns D 1 and D 2 are y d1 , respectively. , y d2 , their widths are x d1 , x d2 , and their interval is x s , then x s =
x c1 (however, x c1 = x c2 ), y d1 = y c1 , y d2 = y c2 ,
x d1 = x d2 . These points are determined by the defect shape inspection unit 10 as a memory pattern of the defect outline.
Confirm by comparing D 1 and D 2 with the external memory pattern Ca of the mask pattern A serving as a reference. In addition, for ease of understanding, the screen memory Ma of the mask actual pattern A and the mask actual pattern B are shown in FIG.
The state in which the screen memories Mb of are superimposed is also shown, and D' 1 and D' 2 indicate the areas surrounded by D 1 and D 2 , respectively. If the external shape memory pattern of the defect satisfies the above conditions, the external shape inspection section 1
0 to the gate section 12, and the defect signal that has already been output from the defect signal output section 11 in response to the abnormality command from the memory pattern outline comparison section 8 is turned off at the gate section 12.

なお該欠陥パターンの外形検査工程に於て、マ
スク実パターンAとBの間にY方向のみの相対位
置ずれがあつた場合を示したのが第3図で、この
場合基準形外形メモリCAの辺の長さをxC1,xC
及びyc1,yc2とし、欠陥の外形パターンD3
D4の長さをそれぞれxd3,xd4、その幅をyd3
d4、その間隔をysとすると、ys=yc1、xd3
c1、xd4=xc2、yd3=yd4となる。
In addition, FIG. 3 shows a case where there is a relative positional deviation only in the Y direction between mask actual patterns A and B in the defect pattern outline inspection process, and in this case, the reference shape outline memory C A Let the length of the sides be x C1 , x C
2 and y c1 , y c2 , and the external pattern of the defect D 3 ,
The length of D4 is x d3 , x d4 , and its width is y d3 ,
If y d4 and the interval is y s , then y s = y c1 , x d3 =
x c1 , x d4 = x c2 , y d3 = y d4 .

そしてピンホールや遮光膜残渣等からなる本来
の実パターン欠陥は、欠陥部の形状が上記の条件
を総べて満たすことはあり得ない。従つて本来の
欠陥を有する実パターンは、該工程に於て上記凝
似欠陥と区別して認識され、該外形検査部10か
らゲート部12にON信号を送り、ゲートをONし
て不良信号出力部12からの信号を外部に出力せ
しめる。
In the case of actual pattern defects such as pinholes and light-shielding film residues, the shape of the defective portion cannot satisfy all of the above conditions. Therefore, an actual pattern having an original defect is recognized in this process separately from the above-mentioned condensed defect, and an ON signal is sent from the outer shape inspection section 10 to the gate section 12 to turn on the gate and output a defect signal to the defect signal output section. The signal from 12 is output to the outside.

上記実施例に於ては本発明の方法を行うに際し
て、実パターンの光学像をデジタル電気信号に変
換して行つたが、本発明の方法はアナログ電気信
号のままで行うこともできる。又本発明の方法は
半導体基板上に整列形成された複数個の同種実パ
ターンの比較検査にも適用できる。更に又本発明
の方法は実パターンの描画データメモリと被検査
実パターンを対比する際にも適用できる。
In the above embodiments, the method of the present invention was carried out by converting the optical image of the actual pattern into a digital electrical signal, but the method of the present invention can also be carried out using analog electrical signals as they are. Furthermore, the method of the present invention can also be applied to comparative inspection of a plurality of real patterns of the same type formed in alignment on a semiconductor substrate. Furthermore, the method of the present invention can also be applied when comparing the drawing data memory of the actual pattern with the actual pattern to be inspected.

以上説明したように本発明によれば基準とする
実パターンと被検査実パターンの映像信号を重ね
合わせて、両映像信号パターンの差信号パターン
を検出し、該差信号パターンの有無により欠陥パ
ターンを判定するパターン検査方法に於て、基準
とするパターンと被検査パターン間の相対位置ず
れに起因する凝似欠陥を、パターン内部の本来の
欠陥と区別して被検査パターンの良否判定を行う
ことができるので、検査精度が大幅に向上する。
また位置ずれを修正するための回路や機構が不要
であり、構成が簡単となり、さらに位置ずれが大
きい場合でも容易に適用できる。
As explained above, according to the present invention, the video signals of a reference real pattern and a real pattern to be inspected are superimposed, a difference signal pattern between the two video signal patterns is detected, and a defective pattern is detected based on the presence or absence of the difference signal pattern. In the pattern inspection method for determining the quality of the pattern to be inspected, it is possible to distinguish the coagulated defects caused by the relative positional deviation between the reference pattern and the pattern to be inspected from the original defects inside the pattern. Therefore, inspection accuracy is greatly improved.
Further, there is no need for a circuit or mechanism for correcting positional deviations, the configuration is simple, and furthermore, it can be easily applied even when positional deviations are large.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に用いるパターン検
査装置の主要構成ブロツク図、第2図a乃至cは
本発明の一実施例に於ける工程断面図、第3図は
他の一実施例に於ける工程断面図である。 図に於て、1は被検査マスク、2はステージ、
3a,3bは光学系(顕微鏡)、4a,4bは映
像信号パターン形成部、5a,5bは信号二値化
部、6a,6bは画面メモリ形成部、7a,7b
は画面メモリ外形認識部、8はメモリパターン外
形比較部、9は欠陥メモリ外形認識部、10は欠
陥メモリ形状検査部、11は不良信号出力部、1
2は出力ゲート部、Aは基準となるマスク実パタ
ーン、Bは被検査マスク実パターン、Ma,Mbは
画面メモリパターン、Caは基準パターンAの外
形メモリパターン、Cbは被検査パターンBの外
形メモリパターン、D1,D2,D3,D4は欠陥の外
形メモリパターン、xs,ysは外形メモリパター
ンの間隔を示す。
FIG. 1 is a block diagram of the main configuration of a pattern inspection device used in one embodiment of the present invention, FIGS. 2 a to c are process sectional views in one embodiment of the present invention, and FIG. 3 is another embodiment. It is a process sectional view in . In the figure, 1 is the mask to be inspected, 2 is the stage,
3a and 3b are optical systems (microscopes); 4a and 4b are video signal pattern forming units; 5a and 5b are signal binarization units; 6a and 6b are screen memory forming units; 7a and 7b
1 is a screen memory outer shape recognition section, 8 is a memory pattern outer shape comparison section, 9 is a defective memory outer shape recognition section, 10 is a defective memory shape inspection section, 11 is a defective signal output section, 1
2 is the output gate section, A is the reference mask actual pattern, B is the mask actual pattern to be inspected, Ma and Mb are screen memory patterns, Ca is the external memory pattern of the reference pattern A, and Cb is the external memory of the pattern B to be inspected. The patterns D 1 , D 2 , D 3 , and D 4 are defect outline memory patterns, and x s and y s are intervals between the outline memory patterns.

Claims (1)

【特許請求の範囲】[Claims] 1 基準とする実パターンと被検査実パターンの
映像信号パターンを重ね合わせて、両映像信号パ
ターンの差信号パターンを検出し、該差信号パタ
ーンの有無により欠陥パターンを判定するパター
ン検査方法に於て、上記差信号パターンのうち
で、基準とする映像信号パターンの対向する二辺
の同じ側にそれぞれ接し、且つ該接辺と等しい長
さを有する一様な幅の一対の差信号パターンを、
他の差信号パターンと区別して欠陥表示対象から
除外する工程を有することを特徴とするパターン
検査方法。
1. In a pattern inspection method in which the video signal patterns of a reference actual pattern and the actual pattern to be inspected are superimposed, a difference signal pattern between the two video signal patterns is detected, and a defective pattern is determined based on the presence or absence of the difference signal pattern. , among the difference signal patterns, a pair of difference signal patterns of uniform width that are in contact with the same two opposing sides of the reference video signal pattern and have the same length as the tangent sides,
A pattern inspection method comprising the step of distinguishing from other difference signal patterns and excluding them from defect display targets.
JP56158993A 1981-10-06 1981-10-06 Inspecting method for rattern Granted JPS5860538A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56158993A JPS5860538A (en) 1981-10-06 1981-10-06 Inspecting method for rattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56158993A JPS5860538A (en) 1981-10-06 1981-10-06 Inspecting method for rattern

Publications (2)

Publication Number Publication Date
JPS5860538A JPS5860538A (en) 1983-04-11
JPS6239816B2 true JPS6239816B2 (en) 1987-08-25

Family

ID=15683872

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56158993A Granted JPS5860538A (en) 1981-10-06 1981-10-06 Inspecting method for rattern

Country Status (1)

Country Link
JP (1) JPS5860538A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132129A (en) * 1983-01-19 1984-07-30 Hitachi Ltd Inspection device for defect
JPS62113436A (en) * 1985-11-13 1987-05-25 Toshiba Corp External appearance inspection method for semiconductor pellet

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50127574A (en) * 1974-03-27 1975-10-07
JPS6043657B2 (en) * 1975-08-22 1985-09-30 株式会社日立製作所 Object condition inspection method

Also Published As

Publication number Publication date
JPS5860538A (en) 1983-04-11

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