JPS6239849B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a free-running frequency fixing scheme for a VCO during input frequency interruption in a PLL circuit.

A PLL (Phase Locked Loop) circuit includes a phase comparator and a VCO (voltage controlled oscillator) and produces an output frequency f ₀ synchronized with the input frequency fi. Here, if N and M are integers and the relationship is fi = N/Mf ₀ , then N,
An M frequency dividing circuit may be provided. If the frequency division ratio cannot be reduced to a small, manageable number, a method is used in which a portion of the output pulses are removed. The PLL circuit in Figure 1 includes a phase comparator PC, a voltage controlled oscillator VCO, N,
It includes M frequency divider circuits 10, 12, 2 frequency divider circuits 14, 16, and an inhibit circuit 18. Ignoring the inhibit circuit 18, this circuit has fi/2N
=f ₀ /2M holds true, and f ₀ =M/Nfi. When the inhibit circuit 18 removes the pulses with the output frequency f ₀ at a ratio of n out of m by the inhibit pulse IP, the output side frequency f ₀ ' of the circuit becomes f ₀ '=m-n/mf ₀ , so that fi /2N=f ₀ ′/2M holds, so f ₀ = M/N・m/m−
It becomes nfi. For example, fi = 97.728MHz, f ₀ =
99.255MHz, N=M=8, m=130, n=2. Figure 2 shows the input frequency fi, inhibition pulse IP, and output pulse f ₀ ', N, M after pulse inhibition.
(Here, N=M) Outputs a, b after frequency division,
An example of the waveform of the frequency-divided outputs c and d is shown below. Since the phase comparator PC is essentially an exclusive OR gate, when it receives such outputs c and d, it produces the output shown in FIG. 2e. The output f ₀ ′ after pulse inhibition is
Control information such as frame pulses and service pulses may be inserted into the inhibited and pulseless portions.

As shown in Fig. 2e, the input and output frequencies fi,
When f ₀ has the above relationship, the inputs c and d of the phase comparator PC are shifted by half a cycle, and the output e is a rectangular wave with a frequency twice that of these inputs c and d and a duty of approximately 50%. becomes. If the input and output frequencies deviate slightly from the above relationship, for example, the output d becomes the output c
Shifts to the right or left in the drawing, in the former case the duty of the output d becomes small, in the latter case it becomes large, the DC component changes, the output frequency f ₀ changes, and the operation returns to the above relationship. . By the way, the above is the case in the steady state, but when the input fi is interrupted, the oscillator VCO enters a free-running state. At this time, the input of the phase comparator PC is only d without the above c, so the output e becomes equal to d, and the DC level (average value) of d controls the oscillator VCO. This output d
is the output of the divide-by-2 circuit 16, that is, the flip-flop, and the duty is also 50%. That is, the output is the same as the output of the phase comparator when the input and output frequencies satisfy the above relationship. In addition, the phase comparator
This is the reason why the divide-by-2 circuits 14 and 16 are provided at both input ends of the PC. In other words, this is because we want to obtain a rectangular wave with a duty of 50%, which satisfies the requirement that the VCO oscillation frequency must match the predetermined center frequency even when the input is interrupted. Circuit 1 for input and output frequency relationship
4 and 16 are both divided by 2, so it is the same as not having them.

However, the situation becomes different when pulse inhibition is performed. _d1 in FIG. 2 is a rectangular wave in a portion where pulse inhibition is performed, and this portion has a larger pulse width than other portions. The DC level of a square wave with a duty of 50% is the pulse amplitude A.
However, if there is a wide portion such as the portion _d1 , that is, a portion where the duty is greater than 50%, the DC level will be slightly higher than A/2. On the other hand, if the pulse inhibition is performed in the portion corresponding to between each pulse of the output d, the interpulse period in that portion becomes large and becomes equivalent to inverting the waveform in Fig. 2d. The DC level will be slightly lower than A/2. In the former case, the free-running frequency is higher than when the input fi is applied, and in the latter case, it is lower. Which state to take is determined by the initial state of the circuit, and since this initial state is not always constant, one of the above two states will occur randomly. In this way, the free-running frequency randomly takes on a slightly larger or smaller state.
This causes problems such as making it difficult to synchronize the subsequent circuits.

The present invention attempts to deal with such a problem, and includes a circuit that divides an input signal of frequency fi by two,
a phase comparator whose one input is the output of the frequency divider circuit; a controlled oscillator which receives the output of the phase comparator and outputs a pulse with a frequency f ₀ ; In a PLL circuit comprising a circuit that inhibits at a ratio of 1 to 2, and a circuit that divides the output of the inhibit circuit by at least 2 and uses the frequency as the other input of the phase comparator, The fixed running frequency system is characterized in that when a disconnection of the input signal is detected, the inhibit is stopped and the output of the controlled oscillator is directly guided to the frequency divider circuit. In this way, the pulse is not partially removed, so a wide pulse as shown in Fig. 2 _d1 is not generated, and only a square wave with a duty of 50% is generated, and the free-running frequency is made equal to the normal output frequency. I can do it.

FIG. 3 shows an embodiment of the invention. The same parts as in FIG. 1 are given the same reference numerals, and 20 is an input disconnection detection circuit, and 22 is an inhibit stop circuit. As shown in FIG. 4, the input disconnection detection circuit includes an integrating circuit 2 consisting of a NAND gate (inverter) 24, resistors R ₁ and R ₂ , a capacitor C, and a power supply -V.
6, a threshold circuit 28 such as a Schmitt trigger. The inhibit stop circuit 22 is an OR gate 22
a and the inverter 22b, and the inhibit circuit 18 is composed of a NAND gate. To explain the operation, while there is an input fi, the output of the inverter 24 is a clock, and the capacitor C is at an intermediate level between H (high) level and L (low) level -|V _H |+|V _L |/
It is charged to a voltage of 2. Since the threshold value V _th is an intermediate value between the high level V _H and the previous voltage value - | V _H | + | V _L | is at the L level, the output of the inverter 22b is H, and the output of the OR gate 22a is also H (high), so the NAND gate 18 is open and allows the output pulse _f0 of the VCO to pass through as is. When the inhibition pulse IP becomes H level, the output of the OR gate 22a becomes L, closing the NAND gate 18 and inhibiting the passage of the output _f0 . Further, when the input fi disappears, the output of the inverter 24 becomes H, and the capacitor C is charged to a voltage of _VH , which exceeds the threshold value _Vth . Therefore, the output of the circuit 28 becomes H, and whether the inhibit pulse IP is L or H, the output of the OR gate 22a is H, so the NAND gate 1
8 is always open to stop the inhibit operation and output
Let f ₀ pass through as is.

FIG. 5 shows another embodiment, and FIG. 6 is a specific example thereof. In this embodiment, a clock switching circuit 30 is provided to switch between an inhibited clock, ie, pulses of frequency _f0 , and an uninhibited clock. That is, 32, 34, 36, 38 in Figure 6
4 is a NOR gate, and 40 is a gate that generates the order (as is) and inverted output of the output CI of the clock loss detection circuit 20. When there is input fi, detection output CI is L
level, so Noah gate 34 is closed and Noah gate 36 is open. Therefore, the NOR gate 32 becomes effective and inhibits the clock _f0 by the inhibit pulse IP. The clock inhibited by gate 32 passes through NOR gates 36 and 38 and becomes the output f ₀ '. When a clock disconnection is detected, the detection output CI goes to H level, gate 34 opens, and gate 36 closes. Therefore, the clock f ₀ is output as is through the gates 34 and 38 without passing through the inhibiting gate 32.

As explained above, according to the method of the present invention, the free-running frequency of the PLL circuit can be made constant by the simple means of stopping pulse inhibiting when there is no input, which is extremely effective. In the embodiment, the N and M frequency dividing circuits 10 and 12 have input and output frequencies fi,
Depending on the ratio of f ₀ , one or both may be omitted. Further, the voltage controlled oscillator VCO may be replaced with an appropriate one such as a current controlled oscillator (CCO) as long as the oscillation frequency is changed by a control signal.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a PLL circuit, Fig. 2 is a waveform diagram for explaining its operation, and Fig. 3 is a diagram showing the first example of the present invention.
FIG. 4 is a block diagram showing an example of the circuit of the main part of FIG. 3, FIG. 5 is a block diagram showing a second embodiment of the present invention, and FIG. FIG. 3 is a diagram showing an example of a main part of the circuit. In the drawing, 14 and 16 are frequency divider circuits, PC is a phase comparator, VCO is a controlled oscillator, 18 is an inhibit circuit, 20 is an input disconnection detection circuit, 22 is an inhibit inhibit circuit, and 30 is a clock switching circuit.

Claims (1)

[Claims] 1. A circuit that divides an input signal of frequency fi by two, a phase comparator that takes the output of the frequency divider by two as one input, and a control that inputs the output of the phase comparator and outputs a pulse of frequency _f0 . an oscillator, the controlled oscillator, a circuit that inhibits the output pulses of the controlled oscillator at a ratio of n out of m, and the output of the inhibit circuit is divided by at least 2 and used as the other input of the phase comparator. In a method of fixing the free-running frequency of the controlled oscillator when there is no input signal in a PLL circuit comprising a circuit, when disconnection of the input signal is detected, the inhibiting is stopped and the output of the controlled oscillator is directly switched to 2. A free-running frequency fixed method characterized by leading to the frequency dividing circuit side.