JPS6239850B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a stabilizing circuit for an A/D converter that can obtain a stable digital conversion output against noise and fluctuations in an analog input signal near each threshold value of the A/D converter. A/D converters are widely used in various devices to convert analog signals into digital signals corresponding to the signal levels. As an example, in the case of a device as shown in Fig. 1, an analog signal at a level set by a signal generation source (DC) 1 is converted into a digital signal by an A/D converter 2, and the next stage performs digital signal processing. Assume that it is input to circuit 3. In this case, if the analog input signal level is near the threshold level of the A/D converter 2, the DC level or the threshold level of the A/D converter 2 may be affected by temperature changes, power supply fluctuations, or induced noise. There is a problem in that the digital conversion output fluctuates due to fluctuations caused by such factors, which may lead to malfunction of the next stage circuit 3. That is, when the full scale of the input signal of the A/D converter 2 is X _FS and the number of bits of the digital signal is N, the A/D converter 2 converts ΔX=X _FS / ² every (2 ^N -1) Threshold level of...X _i
-1 , X _i , X _i+1 , X _{i+2 .} . . are set as shown in FIG. When an analog signal at a level such as A in the figure is input here, a digital signal is converted and output by comparing the level with the threshold level. At this time, assuming that the period of the command pulse of the A/D converter 2 (reciprocal of the sampling frequency) is sufficiently short compared to the fluctuation period of the input signal,
As shown in the figure, the LSB of the digital signal is inverted each time the analog signal exceeds each threshold level. This is also true when the conversion is not done binary, in which case at least one bit of the N-bit output is inverted. This bit inversion also applies when the analog signal fluctuates over a long period or a short period due to noise etc. (as shown in _B1 and _B2 in the figure), and is preferable for the A/D converter 2. There is no such thing. Taking these circumstances into consideration, the inventors of the present invention performed a conversion operation only when the analog input signal changes beyond a predetermined level, thereby preventing malfunctions due to level fluctuations and noise, and eliminating small noise components. A stabilizing circuit for an A/D converter that can always perform stable digital signal conversion even for analog input signals including . FIG. 3 is a schematic diagram showing an example of the proposed circuit, and FIG. 4 is a diagram for explaining its operation.
In FIG. 3, an analog input signal x is multiplied by an input coefficient of 0.5 via a first coefficient multiplier 11, and then led to an adder 12 where it is added to a positive feedback signal to be described later. The A/D converter 13 inputs the addition signal z from the adder 12, converts it into, for example, a binary N-bit digital signal, and outputs it.
This digital signal is led to a predetermined circuit (not shown) as a digital conversion output of the analog input signal x, and is also supplied to the latch circuit 14. The latch circuit 14 holds the digital signal for at least one conversion operation period of the A/D converter 13, and stores it anew each time the A/D converter 13 updates its digital output signal. do. In other words, the latch circuit 14 is the A/D converter 13
After latching the digital output of
The previously latched digital output is held until the converter 13 obtains a new converted digital output in the next conversion operation. However, latch circuit 1
The digital output held at 4 is led to a D/A converter 15 and converted into an analog signal y.
Note that this D/A converter 15 is connected to the latch circuit 14.
It also functions as a local D/A converter with a delay function. The analog signal y is then led to the second coefficient multiplier 16, multiplied by a coefficient of 0.5, and supplied to the adder 12 as a positive feedback signal (0.5y). These latch circuits 1
4. The D/A converter 15, the coefficient multiplier 16, and the adder 12 constitute a positive feedback loop of a stabilizing circuit for the A/D converter 13. Then, the A/D converter 13 performs a digital conversion operation on the analog signal z of z=0.5x+0.5y. Now, the minimum quantization precision (conversion step width) ΔX of the A/D converter 13 is the full scale of the A/D converter 13 _.
It is assumed that ΔX=X _FS /2 ^N (N: number of conversion bits). Then, the level of the digital conversion output X _i (i=0, 1, 2, 3, ~, 2
^N ) is output for the level range of the analog signal z: X _i z<X _i+1 =X _i +ΔX. In other words, when the level range of the analog signal z is in the range from X _i to X _i+1 , the A/D converter 13
Outputs a digital conversion signal corresponding to _i . The stabilizing circuit described above acts on this A/D converter 13 as follows. Now, it is assumed that the analog input signal x changes as shown in FIG. 4, and the A/D converter 13 performs a conversion operation that is sufficiently faster than the rate of change of the analog input signal x. At the initial stage, if the level range of the analog input signal x is (X ₀ x < X ₁ ) and the output level of the A/D converter 13 is X ₀ , then the adder 12
The analog signal z ₁ inputted to the A/D converter 13 via is z ₁ =0.5x+0.5X ₀ . The possible level range of this analog signal z ₁ is 0.5X ₀ +0.5X ₀ z ₁ <0.5X ₁ +0.5X ₀ ......(1) Rewritten as X ₀ z ₁ <X ₀ +0.5ΔX<X ₁ shown. Therefore, the A/D converter 13 outputs a digital signal having the initial value X ₀ and stabilizes it. When the level of the analog input signal x increases and its level range becomes (X ₁ x < X ₂ ), the output signal z ₂ of the adder 12 becomes z ₂ =0.5x+0.5X ₀ , and its level The range is 0.5X ₁ + _{0.5X 0} z _{2 <} 0.5X _{2 + 0.5X 0} However, since the signal _z2 does not exceed the level _X1 , the A/D converter 13 maintains the digital signal output at the level _X0 . That is, even if the analog input signal x changes in the level range (X ₀ x<X ₂ ) at the initial stage, there is no change in the digital conversion output. Furthermore, the level range of analog input signal x is (X ₂
x < X ₃ ) _, the level _{range of} the addition signal z ₃ is _{X 0} + _{ΔXz 3} < The conversion output level of the D converter 13 is
It changes to X ₁ (X ₀ +ΔX). As a result, the positive feedback signal changes to 0.5X ₁ , and the addition signal z' ₃ is expressed as z' ₃ = 0.5x + 0.5X ₁ , and the level range is finally X ₁ < X ₁ + 0.5ΔXz' ₃ < X ₁ +ΔX=X ₂ (5). In other words, the addition signal z changes discontinuously by 0.5ΔX. Then, when the analog input signal x increases to the range (X ₃ x < X ₄ ), the output level of the A/D converter 13 similarly increases.
X ₂ (=X ₁ +ΔX), and following this, the addition signal z discontinuously changes by 0.5ΔX again. Similarly, as the level of the analog signal x increases, the output level changes by ΔX, and the addition signal z increases with discontinuous changes of 0.5 ΔX. Note that the addition signal z is the same as the analog input signal x.
It goes without saying that when the signal changes within a range that does not exceed the levels of X ₀ , X ₁ , X ₂ . On the other hand, due to the above change, the level of the analog input signal x is in the range (X ₁ x < X _{i +1} ), and the output level of the A/D converter 13 at that time is X _i-1
Assume that The addition signal z' _i-1 at this time is given by z' _i-1 = 0.5x + 0.5X _i-1 (6). Then, when the level of the analog input signal x changes to the range (X _i-1 x<X _i ), the level of the signal x becomes smaller than X _i because the level of z′ _i-1 is first passed to the lower side. At this point, the conversion output level changes from X _i-1 to X _i-2 .
As a result, the addition signal z drops discontinuously by 0.5ΔX. Then, from that point of change, a change of 0.5x is shown corresponding to a change in signal x. To summarize the above, the addition signal z given to the A/D converter 13 shows a continuous change of 0.5x in response to the change in the analog input signal x, and also changes depending on the threshold value of the A/D converter 13. It shows a discontinuous change of 0.5ΔX every time the specified level is crossed. Moreover, the above-mentioned discontinuous change of 0.5ΔX occurs in the direction of increase when the analog input signal increases, and conversely occurs in the direction of decrease when it decreases. In other words, the level X _i (i=0, 1, 2,
. Therefore A/D
A dead zone of 0.5ΔX is given to the converter 13. Therefore, even if the analog input signal x slightly changes around the level defined by the threshold value, so-called fluctuations due to fluctuations in the minimum bit (LSB) of the A/D converter 13 will not occur. The state is maintained stably as shown in FIG. Furthermore, since the addition signal z always corresponds to the input signal x, it is possible to obtain the output of the A/D converter 13 that corresponds to the analog input signal. However, although the above-mentioned stabilization method has the excellent feature of being able to obtain a stable digital value against fluctuations and noise in the analog input signal,
There are still some problems. For example, there are problems such as a delay in step response as shown in FIG. 5, and waveform distortion as shown in FIG. Now, when input signal level x is converted to quantization step number (QN), QN = 0.5 to QN = 100.5
Considering the response of a step signal that changes over time, when a command signal ( COMND ) is given to operate the A/D converter 13, the addition signal (feedback signal) z is initially equal to the sum of the input signal x and the output y. Since it represents the average level, the output level of the A/D converter 13 steps up to QN=50. However, this change in the output of the A/D converter 13 still does not correspond to the input signal, so if the command signal is further repeated in sequence, the output of the A/D converter 13 will be QN = 75, It changes sequentially as 87, 93, etc. Finally, it converges to a stable point QN=99 corresponding to the analog input signal x. That is, in this case, the digital conversion output will not converge unless the conversion operation is repeated seven times. Further, in the case of 256 quantization levels, 8 iterative conversion processes are required, and generally convergence of the digital output is achieved by k conversion processes for a step response of 2 ^k quantization levels.
In other words, this shows that the step response is poor. Regarding waveform distortion, as shown by the response characteristics to the triangular wave in FIG. 6, waveform distortion occurs due to hysteresis characteristics. This is the average value z of the input signal x and the output signal y of the D/A converter 15.
This is because the input signal x is A/D converted after being compensated by . Note that N in the figure indicates a waveform of a component in which distortion is superimposed on quantization noise, and D in the figure indicates a waveform indicating a distortion component. As is clear from these waveforms, the stabilization method described above causes a relatively large amount of waveform distortion for one quantization step. The present invention has been made in consideration of such circumstances, and its purpose is to prevent malfunctions of the A/D converter due to level fluctuations and noise of analog input signals, and to prevent malfunctions of A/D converters that include minute noise components. To provide a simple and highly practical A/D converter stabilization circuit that always performs stable digital conversion processing even for analog input signals, improves step response, and reduces conversion waveform distortion. There is a particular thing. That is, in the present invention, the stabilizing circuit previously proposed in Japanese Patent Application No. 54-88769 basically constitutes a cyclic filter as shown in the flowchart of FIG. 7, and H _(z) = 0.5/(1- This was done with a focus on having a transfer function characteristic of 0.5z ^-1 ). Note that z ^-1 indicates a delay of 1/sampling period, and z is expressed as z=exp(j2π). Therefore, if we apply inverse function processing to the above signal processing as shown in the flowchart of Figure 8 as G _(z) = (1-0.5z ^-1 )/0.5, we will end up with H _(z) ×G _(z) = 1, and A/D conversion processing is performed with the transfer function set to 1, making it possible to effectively achieve the above-mentioned purpose. Embodiments of the present invention will be described below with reference to the drawings. FIG. 9 is a schematic configuration diagram showing the first embodiment, in which the same parts as the circuit shown in FIG. 3 are denoted by the same reference numerals. The analog input signal x is input to the first adder 12 after passing through the coefficient multiplier 11 , where it is added to the feedback signal and supplied to the A/D converter 13 . The latch circuit 14 latches the digital output signal of the A/D converter 13, delays the analog input signal by one sampling period, and outputs the delayed signal. This delayed output is converted into an analog signal by the D/A converter 15, and then a coefficient of 0.5 is applied by the coefficient unit 16.
The feedback signal is generated by multiplying . This signal processing loop is the same as the circuit shown in FIG. 3 above. On the other hand, the one sampling period delayed output of the digital signal outputted via the latch circuit 14 is sent to the second adder 1 via the digital coefficient unit 17.
8. The above digital coefficient unit 17
For example, the digital signals input in parallel are shifted by 1 bit and then multiplied by a coefficient of 0.5. The second adder 18 is composed of a digital adder, and the digital output signal of the A/D converter 13 is inputted to the other end. The second adder 18 is connected to the A/D converter 13
The digital output signal of x is added to the digital signal of one sampling period before which has been multiplied by a coefficient of 0.5 via the latch circuit 14 and the coefficient multiplier 17, and the digital conversion output of the stabilized analog input signal x is added thereto. It has gained. This circuit configured in this way is equivalent to the 10th circuit.
The signal flow diagram in FIG. In the signal flow diagram shown in FIG. 10, solid lines indicate the flow of analog signals, and broken lines indicate branches of the flow of digital signals. Also, the numerical value attached to each branch is the gain of each signal flow, Q is the quantization operation (A/D conversion),
Q ^-1 indicates an inverse quantization operation (D/A conversion) and Z ^-1 indicates a delay of one sampling period. If the effect of quantization is ignored (Q = Q ^-1 = 1), this corresponds to the flowcharts shown in Figs. 7 and 8 connected in cascade with Z ^-1 in common, Its transfer function is 1. However, in reality, since Q≠1 and Q ^-1 ≠1, it is undeniable that some errors occur. Thus, the response of the circuit configured as described above to the step waveform is a sharp rise without delay, as shown by the solid line _Yc in FIG. It should be noted that oscillation of one quantization step occurs during the period in which the command pulses are repeatedly applied as shown in FIG. 8, but this is caused by a quantization error. Further, such a step waveform response is obtained by the configuration in which the transfer function described above is set to 1. Also, if we look at the triangular waveform response, the input signal x
When the level of Y c increases, initially Y _c shows the correct value, but when the next command is received it becomes one quantization step lower. Further, when the level of the input signal x decreases, the second Y _c and subsequent ones show correct values, and only the first Y _c shows a value one quantization step lower. Furthermore, in the circuit proposed earlier, the digital conversion output is Y itself, so when compared with this, it can be seen that the present circuit is not so advantageous in terms of waveform distortion. As described above, according to the present circuit, the step response problem of the above circuit can be effectively solved without impairing the characteristics and advantages of the stabilization circuit proposed by the present inventors. . Moreover, it can be realized by a simple configuration in which a signal delayed by one sampling and multiplied by a constant of 0.5 is added to the output of the A/D converter 13. In other words, it is possible to always perform stable digital conversion with good step response without causing malfunctions due to the influence of analog signal level fluctuations, noise, etc. By the way, according to the circuit of the first embodiment described above, it is possible to improve the step response, but it is also possible to reduce waveform distortion and improve the characteristics. FIG. 13 is a schematic structural diagram of a second embodiment showing an example thereof. This configuration diagram shows a signal flow diagram with functional blocks added, and the output of the A/D converter 13 and the output of the latch circuit 14 are respectively guided to the logic operation unit 21, and the outputs of the logic operation unit 21 are It is configured to set a flag 22 and generate a compensation signal in accordance with this flag information. The compensating signal is then led to the third adder 23 and added to the output Y _c of the second adder 18 to finally obtain digital conversion data A. Considering that an error of one quantization step occurs in the triangular waveform response in the previous embodiment, the logic operation unit 21 generates a compensation signal according to the control flow shown in FIG. 14 in order to compensate for this, and outputs it. It is added to Y _c . To briefly explain the control flow shown in FIG. 14, first, the determination unit (i) performs the calculation "Y-YZ ^-1 ", and the output Y of the A/D converter 13 and the value before one sampling are calculated. The magnitude of the output YZ ^-1 is determined. When the result of the above calculation is positive, the flag is set to "1" (ii), and when the result is negative, the flag is set to "0" (iii). When the flag "1" is set, the third adder 23 outputs the output Y _c of the second adder 18 as is (iv). Further, when the flag "0" is set, the third adder 23 adds one quantization step level "1" to the output Y _c of the second adder 18, and outputs this as digital conversion data. (v). Further, when the two are equal according to the determination shown in (i) above, the calculation output becomes zero, so the flag determination shown in (vi) is performed. Then, depending on the state of the flag at the previous sampling point, that is, when the flag is set to "1", one quantization step level is added, and conversely, when the flag is "0", Second
The adder 18 operates to directly output the output Y _c of the adder 18 . By performing such compensation control, the output changes as shown in A in FIGS. 11 and 12, and waveform distortion is reduced without impairing the step response characteristics obtained in the first embodiment. Further improvements will be made. That is, in FIG. 12, N is a waveform in which quantization noise and distortion are superimposed. The solid line is the waveform for waveform Y, and the dotted line is the waveform for waveform A. Furthermore, FIG. 6D depicts only the distortion component of the waveform relative to A, and it can be seen that the distortion component is much smaller than in FIG. 6D. FIG. 15 shows the configuration of the control unit 21 and flag circuit 22 that operate according to the above control flow, and includes a determination circuit 25, a flip-flop (flag circuit) 26 that is reset by the output of this determination circuit, and It is composed of an AND circuit 27 and an OR circuit 28 that perform logical operations on these outputs. According to such a circuit, a logical output (compensation signal) as shown in the following table is obtained, and the third adder 23 compensates the output Y _c according to this.

[Table] Note that Q in the above table indicates that the state before the condition change is maintained. Thus, the error of one quantization step under the specific conditions in the first embodiment is effectively compensated, and highly accurate and stable digital conversion data can be obtained. Note that the present invention is not limited to the above embodiments. In the embodiment, the latch circuit 14 is shared to stabilize both, but separate latch circuits may be used. It goes without saying that other delay means may be used instead of the latch circuit. Furthermore, the signal to be applied to the second adder may be generated in analog form, and may be A/D converted and added, or the elements of each loop may be shared as appropriate. Furthermore, the dynamic range of the analog signal, the number of bits of the digital conversion output, etc. may be determined according to the specifications. In short, the present invention can be implemented with various modifications without departing from the gist thereof. Now, the stabilizing circuit according to the present invention, which has the various advantages as described above, can be incorporated into various devices and used. FIG. 16 shows an example in which the A/D converter and its stabilizing circuit according to the present invention are incorporated into a level adjuster.
It is represented by 1. This block 31 is given an arbitrary analog voltage value obtained by dividing the potential of a DC power supply 32 by a variable resistor 33. The block 31 to which this analog voltage value is input outputs a digital signal corresponding to the voltage value, as described above.
This is converted into a digital multiplier (multiplier) 34
is giving to This multiplier 34 receives, for example, a digitally encoded audio signal as input, multiplies this digital input signal by a previous digital signal, that is, a coefficient value, and outputs the result. Now, assuming that the above-mentioned digitally encoded input signal is expressed in 12 to 16 bits, when multiplication is performed while maintaining significant digits, generally block 31 is used.
Also requires 12 to 16 bits of control signals from the If this is multiplied by an 8-bit control signal and the control signal is unstable, there is a risk that the information in the lower several bits of the input signal will be completely lost and become meaningless. However, when multiplication control is performed using a digital control signal stabilized and error compensated by the circuit of the present invention (block 31), since the signal is highly accurate and stable,
Bits are enough to achieve this purpose. Further, at this time, the multiplication process is not adversely affected by the instability of the power supply 32 or the noise components caused by the resistor 33, so that it is extremely effective as a digitally controlled level adjuster. Moreover, it has the advantage that a signal with a high number of bits can be stably controlled by a digital signal with a small number of bits, and it can be constructed easily and at low cost. As detailed above, according to the present invention, the step response delay and waveform distortion of the A/D conversion output stabilized by positive feedback are corrected by the feedforward type correction means using delay addition processing. Always stable A/R with excellent conversion characteristics and no malfunctions caused by minute level fluctuations or noise.
Enables D conversion operation. Furthermore, since the quantization error is compensated according to the magnitude of temporally adjacent sampled values, the A/D converter has a simple and highly practical configuration that always performs highly accurate A/D conversion with good reliability. A circuit can be provided here.

[Brief explanation of the drawing]

Figure 1 is a diagram to explain the function of the A/D converter, Figure 2 is a signal level diagram to explain the A/D conversion operation, and Figure 3 is the stability of the A/D converter proposed earlier. Figures 4 to 6 are diagrams showing the operating characteristics of the circuit, and Figures 7 and 8 are diagrams showing the operating characteristics of the circuit.
The figure is a signal flow diagram schematically showing the transfer characteristics of A/D conversion processing, FIG. 9 is a schematic configuration diagram showing the first embodiment of the present invention, and FIG. 10 is an equivalent signal flow diagram of the embodiment circuit. 11 and 12 are diagrams showing the operating characteristics of the embodiment circuit, respectively, and FIG. 13 is a schematic signal flow diagram showing the second embodiment of the present invention.
FIG. 4 is a diagram showing a control flow, FIG. 15 is a diagram showing a main part configuration of the second embodiment, and FIG. 16 is a diagram showing an outline of a system configured using the present invention. 11...Coefficient unit, 12...First adder, 13
...A/D converter, 14...Latch circuit, 15...
...D/A converter, 16...Coefficient unit, 17...Coefficient unit, 18...Second adder, 21...Control unit, 22...Flag circuit, 23...Third adder.

Claims (1)

[Scope of Claims] 1. A first adder that adds an analog input signal and a positive feedback signal and supplies it to an A/D converter; delay means for delaying the input signal by one sampling period; means for converting the delayed output into analog and multiplying it by a factor of 0.5 to generate the positive feedback signal; and an auxiliary device for multiplying the delayed output by a factor of 0.5. A stabilizing circuit for an A/D converter, comprising a second adder that adds a signal and a digital signal output from the A/D converter and outputs the result. 2. A first adder that adds the analog input signal and the positive feedback signal and supplies the result to the A/D converter, and converts the digital signal converted and output by the A/D converter into one sample of the analog input signal. Means for period delay, analog conversion of this delayed output, and
means for generating the positive feedback signal by multiplying the delayed output by a factor of 0.5; and a second addition for adding the auxiliary signal obtained by multiplying the delayed output by a factor of 0.5 and the digital signal output from the A/D converter. means for comparing and determining the magnitude of the level of the output digital signal of the A/D converter and the delayed output, and generating a correction signal according to the determination result to output the digital output of the second adder. 1. A stabilizing circuit for an A/D converter, comprising a third adder that adds to a signal. 3. The means for generating the positive feedback signal includes a local D/A converter that converts the digital delayed output into analog;
0.5 to the analog output signal of this local D/A converter.
3. A stabilizing circuit for an A/D converter according to claim 1 or 2, comprising a coefficient multiplier for multiplying by a multiplication factor. 4. The correction signal generated by level determination of the output digital signal of the A/D converter and the delayed output is determined when the delayed output is large, and when the digital signal and the delayed output are equal and one standard cycle before the level determination. The A/D converter according to claim 2, wherein when the output digital signal becomes large, the A/D converter generates one quantization step level, and under other conditions, it generates a zero level signal. D converter stabilization circuit.