JPS623986B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage capacitor-free semiconductor memory device having essentially only one insulated gate field effect transistor.

Conventionally, MOS memory is a dynamic memory with one transistor and one capacitor that is used as a large capacity memory, but in a sense this is
In addition to being an element memory, capacity limitations are essential. In contrast, Nikkei Electronics magazine
``Dynamic RAM Cell without Storage Capacitor'', January 22, 1979 issue, pages 44-45, and 1979 issue of the same magazine, 1
“Not using storage capacitors 1” on page 216 of the August 8th issue
A one-transistor memory element that holds holes has been proposed for the N-channel MOS type, as described in "Proposal of Tiger-type Dynamic RAM," but the writing operation is complicated and there is little operational margin. It seems that it is not necessarily sufficient.

The purpose of this invention is to simplify the writing operation and
It is an object of the present invention to provide a memory element with a novel configuration that has sufficient operational margin.

According to the present invention, in a semiconductor memory device that does not require a storage capacitor and has substantially only one insulated gate field effect transistor, an isolation layer provides electrical isolation between the semiconductor memory device and an adjacent semiconductor memory device. A channel region of the insulated gate field effect transistor and a highly doped first semiconductor layer of the first conductivity type are arranged so as to face each other across a first conductivity type semiconductor layer partitioned by
The channel region, which is a region between the source and drain regions of the second conductivity type, is provided with a second impurity layer of the first conductivity type directly under the gate insulating film, and a second impurity layer of the first conductivity type immediately below the gate insulating film. A third impurity layer of a second conductivity type on the first impurity layer is provided directly under the impurity layer, thereby forming a potential well of majority carriers directly under the gate insulating film. , the majority carriers are selectively injected and held in the potential well by controlling the potential between the first impurity layer and the source and/or drain region; The gate electrode and the source and/or
Alternatively, a semiconductor memory element characterized in that the state of held charges can be read out by controlling the potential with respect to the drain region can be obtained.

Embodiments of the present invention will be described below with reference to the drawings. In the following, embodiments of the present invention will be described using an N-channel MOS insulated gate field effect transistor, but it can be easily analogized to a P-channel type field effect transistor.

Referring to FIG. 1, which shows an embodiment of the present invention, a P-type semiconductor layer 2 is formed on an N-pole semiconductor substrate 1 by, for example, epitaxial growth or a P-well. By forming the oxide film layer 10, the element regions of the epitaxial layer 2 are electrically isolated from each other. Note that PN junction isolation may be used instead of the insulation isolation using the oxide layer 10. Next, an N-type impurity layer 3, a P-type impurity layer 4, a gate oxide film 5, a gate electrode 6, a source and drain N ⁺ diffusion layer 7,
form 8. Further, numeral 9 is a P ⁺ diffusion layer forming word W in FIG. This is deeper than 3.

FIG. 2 shows the structure of a memory in which a MOS transistor having such an element structure is used as a memory cell.
The RX electrode is used as a word line for reading, the P ⁺ buried region 9 (W) and gate electrode 6 are used as word lines for writing, and the source and drain are used as bit lines.

The write operation is performed as follows. Make W negative, Y
When set to GND, the holes accumulated in the area 4 of the cell are sucked out to 9 through 2. Since holes are not sucked out in the columns where Y is positive, cells from which holes are sucked out can be selected by W and Y. Next, holes are injected into the region 4 of the cell by applying a negative bias to the gate X and setting Y to GND.
In this way, when gate X is set to negative and Y is set to GND, the holes accumulated in layer 2 exceed the potential peak of layer 3, are attracted by the negative bias of gate X, and are injected into layer 4. . Since holes are not injected in columns where Y is at a positive potential, holes can be selectively injected into cells by selecting X and Y.

Readout is performed by selecting a cell by selecting RX and Y, and by detecting a change in threshold current, that is, a change in conductivity, depending on the amount of holes injected into the region 4 of the transistor. I can do it.

As is clear from the above description, the semiconductor memory device according to the present invention has a simpler write operation than the conventional semiconductor memory device having substantially only one insulated gate field effect transistor.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are a sectional view and an equivalent circuit diagram, respectively, of an embodiment of the present invention. 2... Semiconductor layer of first conductivity type, 3... Third impurity layer of second conductivity type, 4... Second impurity layer of first conductivity type, 5... Gate insulating film, 6... Gate electrode, 7... source region of second conductivity type, 8... second
Drain region of conductivity type, 9... High concentration first impurity layer of first conductivity type, 10... Field oxide film.

Claims (1)

[Claims] 1. In a semiconductor memory device that does not require a storage capacitor and has only one insulated gate field effect transistor, the semiconductor memory device is partitioned by an isolation layer that provides electrical isolation between the semiconductor memory device and an adjacent semiconductor memory device. A channel region of the insulated gate field effect transistor and a highly concentrated first impurity layer of a first conductivity type are provided so as to face each other with a semiconductor layer of a first conductivity type interposed therebetween; The channel region, which is the region between the conductive type source and drain regions, includes:
By providing a second impurity layer of the first conductivity type directly below the gate insulating film, and a third impurity layer of the second conductivity type on the first impurity layer immediately below the second impurity layer. , a memory element in which a potential well of majority carriers is formed directly under the gate insulating film, wherein majority carriers are formed in the potential well with the first impurity layer and the source and/or;
selectively implanted and held by controlling the potential with the drain region, and held by controlling the potential between the gate electrode on the gate insulating film and the source and/or drain region. A semiconductor memory device characterized by reading out the state of charge.