JPS623988B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a current non-saturation type field effect transistor that is compact and has a high gain constant.

An example of a conventional field effect transistor of this type is shown in FIGS. 1 and 2. In the figure, 1 is a semiconductor substrate (for example, P type), 2 is an insulating film for element isolation, 3 is a source high impurity concentration layer (for example, n type), 4 is a drain high impurity concentration layer (for example, n type), and 5 is a source electrode. , 6 is a gate electrode, 7 is a drain electrode, and 8 is a gate insulating film. When the drain potential V _D is positively applied to the source electrode V _S , the source potential V _S
By applying a positive gate potential V _G to the semiconductor substrate 1, electrons are induced at the interface between the semiconductor substrate 1 and the gate insulating film 8, and conduction is established between the source and drain. Figure 3 shows the voltage and current characteristics. V _G -
Under the condition of V _S >V _D -V _S , the drain conductance increases as V _D -V _S increases, and the drain current I _DS increases. However, V _G −V _S
Under the condition of V _D -V _S , the channel layer of electrons induced at the interface between the semiconductor substrate 1 and the gate insulating film 8 disappears near the drain high impurity concentration layer 4, and the drain conductance becomes extremely small. Therefore, under the condition of V _D -V _S 〓V _G -V _S , the drain current I _DS hardly increases with respect to an increase in V _D -V _S and is saturated. Another drawback is that the gain constant gm (≡αI _DS /α(V _G -V _S )) also saturates as the drain current I _DS saturates.

In order to eliminate these drawbacks, the present invention allows electron current and hole current to flow by applying a forward bias to the drain electrode, thereby causing either the electron current or the hole current to change to the gate potential. The object of the present invention is to provide a field effect transistor configured so that the current always flows without being constrained by a surface potential well, and the current is made non-saturated. The drawings will be explained in detail below.

FIG. 4 and FIG. 5 are examples of the present invention, and
8 is a source electrode, 9 is a drain electrode, 9' is a gate insulating film, 10 is a semiconductor substrate, 11 is an insulating film, 1
2 is a channel layer, that is, a semiconductor active layer (for example, n-type, with a concentration of 1×10 ¹⁴ to 1×10 ¹⁶ and a thickness of 2 μ to 2000
Å), 13 is a semiconductor high impurity concentration layer (for example, n
14 is a semiconductor high impurity concentration layer (for example, p
15 is a semiconductor high impurity concentration layer (for example, n-type with a concentration of 1×10 ¹⁸ or more and a thickness of 1000 Å or more) that prevents depletion of the interface region between the gate insulating film 9' and the semiconductor active layer 12; 16 is a gate electrode (for example, a p-type semiconductor layer).

To operate this, for example, the source potential V _S and the substrate potential V _X are made equal. Further, V _D -V _S is set to a positive value larger than the built-in voltage V _B at the junction between the semiconductor active layer 12 and the semiconductor high impurity concentration layer 14 . First, when V _G −V _S is equal to or smaller than a certain voltage V _T , as shown in FIG. 6a, most of the semiconductor active layer 12 is depleted (indicated by diagonal lines in the figure) and there are almost no electrons. However, holes are induced at the interface between the gate isolation film 9 and the semiconductor active layer 12. However, due to the presence of the semiconductor high impurity concentration layer 15, there is no conduction between the semiconductor active layer 13 and the semiconductor high impurity concentration layer 14. Next, as shown in FIG. 6b, when V _G -V _S is larger than V _T but smaller than the voltage V _FB at which the interface between the gate insulating film 9' and the semiconductor active layer 12 becomes a flat band, the gate insulating The depletion layer that had been expanding from the interface between the film 9' and the semiconductor active layer 12 shrinks, and a conductive channel is formed near the interface between the semiconductor active layer 12 and the insulating film 11. Semiconductor active layer 12 and semiconductor high impurity concentration layer 1
Mutual injection of holes and electrons occurs near the boundary with 4, and current flows. However, if the formed conductive channel layer is thin, the resistance of the channel layer becomes higher than the resistance of the junction between the semiconductor active layer 12 and the semiconductor high impurity concentration layer 14, so that the drain current I _DS
is dominated by the resistance of the channel layer. Gate potential V
As _G increases, the depletion layer shrinks and the channel layer resistance decreases, so the drain current I _DS increases. The relationship between the drain current I _DS and V _D -V _S in this state is shown as depletion mode D in FIG. Drain current I _DS is approximately proportional to V _D −V _S .

Further, as shown in FIG. 6c, when V _G -V _S >V _FB , electrons are induced at the interface between the gate insulating film 9' and the semiconductor active layer 12, so that the channel resistance further decreases. Therefore, when the channel resistance becomes equal to the junction resistance, the drain current I _DS is dominated by the characteristics of the junction between the semiconductor active layer 12 and the semiconductor high impurity concentration layer 14, and has an exponential function with respect to the change in V _D -V _S. It seems to increase. Drain current I _DS in this state
Figure 7 shows the relationship between V _D -V _S and
Shown as Mode E.

As shown in FIG. 6, for example, when the channel layer is an n-type semiconductor, after a conductive channel is formed, a large number of electrons are bound to the interface between the gate insulating film 9' and the semiconductor active layer 12, and the gate Affected by electrical potential. However, the holes are removed from the gate insulating film 9'.
and the semiconductor active layer 12. Therefore, the electron current is V _D −V _S > like the conventional example.
It is saturated when V _G -V _S , but the hole current is not saturated.

Because of this effect, the drain current I _DS does not saturate as the drain potential V _D increases, but increases monotonically.

As explained above, since the field effect transistor of the present invention is a current non-saturation type, the first factor is the gain constant.
gm is an increase in drain potential V _D or gate potential V _G
It has the advantage that it increases monotonically as . Second, since the channel resistance is high in the depletion mode, there is an advantage that when the gate potential is constant, the resistance between the source and drain terminals exhibits a substantially constant value regardless of the drain potential. Third, in the enhancement mode, forward current characteristics of the junction are obtained, so there is an advantage that the operating resistance is sufficiently lower than that of the conventional device.

If the field effect transistor of the present invention is used in an operational amplifier, it is effective to realize an amplifier having a higher gain than the first advantage. Furthermore, if applied to a gain control resistor element in an automatic gain control circuit, the second advantage is that it is effective in realizing a circuit in which the gain can be controlled over a wide range. Furthermore, if applied to elements for logic circuits or control circuits, it is more effective than the first and third advantages in realizing high-speed logic circuits or switches with low operating resistance.

[Brief explanation of the drawing]

1 and 2 are conventional examples, FIG. 3 is a diagram of the same operating characteristics, FIGS. 4 and 5 are field effect transistors of the present invention, FIGS. The figure shows the same operating characteristic diagram. 8... Source electrode, 9... Drain electrode, 10
... Semiconductor substrate, 11 ... Insulating film, 12 ... Semiconductor active layer, 13, 14, 15 ... Semiconductor high impurity concentration layer, 16 ... Gate electrode.

Claims (1)

[Claims] 1. A channel layer formed of a semiconductor conductive layer on an insulating substrate, a first terminal formed by introducing a high concentration impurity of the same conductivity type as the channel layer into the upper surface of the channel layer, and the first terminal. Separately from the terminal, a second terminal is formed by introducing a high concentration impurity of a conductivity type different from that of the channel layer into the upper surface of the channel layer, and a second terminal is formed on the upper surface of the channel layer between the first terminal and the second terminal. an insulating layer disposed on the surface; a third terminal formed of a semiconductor layer or a metal layer on the insulating layer; and a third terminal disposed on the surface above the channel layer in a local area between the first terminal and the second terminal. A field effect transistor comprising a high impurity concentration layer of the same conductivity type as the channel layer.