JPS6240694A - Circuit for sensing leakage current - Google Patents

Abstract

PURPOSE:To obtain an automatically controlled leakage current sensing circuit by generating a refreshing start control signal from an inverter so as to again charge the capacity of a monitor circuit and starting a leak operation with an optimal operating margin and simultaneously discharging the output of the inverter so as to prepare the operation for the next leak sense output. CONSTITUTION:At a node N3 of the monitor 11 the threshold VTP of a Pch element Q2 is lower than a power source voltage VDD and a moving margin Vmgm is higher. By reducing a voltage to VDD-VTP due to the leakage of the capcities of C1 and C2, the pch element Q3 of the inverter 12 is turned ON, and the voltage comes to VDD if the nch element Q4 is turned OFF. This change is detected 27, and the voltage is inversed 22 into VDD and reduced to VSS after delayed 28. By the electric potentials of N6 and N11 a pulse is generated from an AND gate 23 and the refreshing operation is started. After delayed 34, N1 is charged to VDD-VTP, boosted by the parasitic capacity of Q2 and outputted to N3. The terminal N4 of the C1 is temporarily reduced to VSS through the inverter 32 and returned to VDD, and then N3 is charged to the initial voltage again. N12 is delayed 34 and 37 and rises to VDD. Then Q4 is turned ON and discharges N6 to VSS to provide for the next charge.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a semiconductor memory device, particularly a dynamic RAM.
The present invention relates to a leakage current sensing circuit used in a refresh circuit of (random access memory).

[Technical Background of the Invention] Some of the recent dynamic RAMs have an automatic refresh circuit mounted on the memory chip to automatically perform a refresh operation, thereby facilitating usage and peripheral circuitry. This automatic refresh circuit includes, for example, an oscillator 81 and a refresh address counter 82 as shown in FIG. 8, and automatically sets a refresh address when the memory is in normal operation, that is, when data is not being written or read. and performs a refresh operation. In this case, if the leakage current of the memory cell is not taken into consideration in the refresh operation, the current consumption of the refresh circuit will become larger than necessary. In other words, the above leakage current increases as the ambient temperature rises, so in order to perform automatic refresh operation over all temperatures, it is necessary to set a short refresh cycle with a certain margin, assuming the case where the leakage current is the largest. This is because it has to be set.

Under these circumstances, in order to reduce the power consumption required for refreshing, an MO8 storage device was developed in Japanese Patent Application Laid-Open No. 1983-1982 that adopted a fully automatic refresh method that controls refresh operations to be performed automatically at the maximum necessary frequency. 56
This method has been proposed in Publication No. 291. Zarani, this MO
An automatic refresh El control circuit with lower Ir4 power consumption than that of the 8 storage device has been proposed in Japanese Patent Application No. 172754/1983 filed by the applicant of the present application. A circuit according to one embodiment is shown in FIG. The basic operation of this automatic refresh method is to control the start of the refresh operation or the intermittent interval by detecting that the holding voltage of the capacitor in the leak monitor circuit has decreased due to leakage and has fallen below a predetermined value. It is something. In FIG. 9, the leak monitor circuit 91 has one storage capacitor C and one N-channel MO8 type transfer gate Q connected in series so as to have the same configuration as a memory cell (not shown). It is composed of

Note that 92 is a precharge/discharge type CMO.
It is an S inverter.

By the way, if the amount of charge charged in the capacitor C of the leak monitor circuit 91 is inappropriate, the time required for the holding voltage of the capacitor C to become equal to or less than a predetermined value, that is, monitor the leak time, is It cannot be said that this accurately reflects the actual leakage time in the memory cell. In consideration of this point, a specific example for appropriately charging the capacitor of the leak monitor circuit has been proposed in Japanese Patent Application No. 1986-56503 "Leak Current Sense Circuit" filed by the applicant of the present application. .

FIG. 10 shows a circuit configuration of an embodiment of this leakage current sensing circuit. This leakage current sensing circuit is provided in the automatic refresh control section of the dynamic RAM, Ql to C4 are MOS transistors (insulated gate field effect transistors), C1, t> and C2 are first
, a second capacitor, which constitute a leak monitor circuit 110 and a precharge/discharge type inverter 120. That is, in the leak monitor circuit 110, the P channel MOS transistor Q
1, the source is connected to the vDD power supply, the drain and gate are connected to each other, and the N
Connected to the drain of channel MOS transistor Q2. One end of each of capacitors C1 and C2 is connected to the source of this transistor Q2. Here, the transistor Q2 and the capacitor CLC2 are configured to have characteristics equivalent to those of the memory cell in the dynamic type RA~1. In the inverter 120, the source of the P-channel MOS transistor Q3 for precharging is connected to the VDD power supply, and the drain is connected to the N for discharging.
The drain and gate of the channel MoS transistor C4 are connected to one end of each of the first and second capacitors CL C2, and the source of the 1-transistor Q4 is connected to the Ves power supply (II ground potential). Note that in FIG. 10, the drain of transistor Q2 is connected to the first node N.
1. The gate is connected to the second node N2, the source is connected to the third node N3, the other end of the first capacitor C1 is connected to the fourth node N4, and the other end of the second capacitor C2 is connected to the fifth node N5.
, the common drain of transistors Q3 and 04 is a sixth node N6, and the gate of transistor Q4 is a seventh node N7.

In the leakage current sensing circuit having such a configuration, a pulse signal is supplied to the gate of the transistor Q2, that is, the node N2 at a predetermined timing, and the third node N3 is supplied with an equivalent voltage VTP of the P-channel MOS transistor Q1, which is lower than the power supply vDD. A lower potential Voo-VTR (hereinafter referred to as potential vb) is applied to the first capacitor C.
By increasing the potential at the other end of the node N4, that is, the potential at the node N4, the potential at the node N3 is bootstrapped from vb to VC. Note that a constant potential, for example VC, is always supplied to the other end of the second capacitor C2, that is, the fifth node N5. After the potential of node N3 is bootstrapped, it is left in this state. At this time, the first and second
When the potential of the node N3 reaches a predetermined value or less due to leakage from the capacitors C1 and C2, the precharge/discharge type inverter 120 detects this, and the signal at the sixth node N6 is inverted from Vos to VDD.

Note that before this, the signal at node N7 was set to VDD at a predetermined timing in advance, and the N-channel MOS l in the precharge/discharge type inverter 120
~The transistor Q4 is turned on, and the signal at the node N6 is set to Vso.

Here, capacitors C1 and C2 of 2ala and two types of potential V
b and Vc determine the potential change ffi V Un at the node N3, which is the connection point between the second capacitor C2 and the transistors 1 to Q2, before and after the bootstrap, and its value is given by the following equation.

The potential given by the above equation 1 provides a refresh operation margin. This refresh operation margin is based on process changes and does not depend on fluctuations in the threshold voltage of MOS transistors, and is based on the monitor capacitors C1, C2 and two types of potential V.
It is possible to set the optimum value only by b and Vc. In this case, the optimum value is to set the monitor capacitor C so that the leak current sensing circuit can accurately sense the monitor time before the leak time in the actual memory cell.
1. This is the time required to charge C2.

[Problems of the Background Art] Incidentally, in the leakage current sensing circuit as shown in FIG. 10, the operation of the peripheral circuits that control the start or intermittent interval of the refresh operation is considered to be very important.

However, the application of Japanese Patent Application No. 60-56503 does not disclose specific circuits regarding these peripheral circuits. Peripheral circuits are essential in order to perform refresh control completely automatically.

[Purpose of the Invention] This invention was made in consideration of the above-mentioned circumstances, and its purpose is to be able to set the refresh operation margin to an optimal value without depending on process changes, and to improve the refresh operation margin. Automatic start and intermittent intervals]I11
An object of the present invention is to provide a leakage current sensing circuit with a control circuit for controlling the leakage current.

[Summary of the Invention] In order to achieve the above object, the present invention provides a leak monitor using a transfer gate and first and second capacitors to monitor the number of memory cells that require a refresh operation. configuring a circuit, and when the potential at the connection point between the transfer gate and the second capacitor in this leakage monitor circuit reaches a predetermined value, precharging the output end of the precharge/discharge type inverter according to this potential; A first control circuit generates a control signal for controlling the refresh operation of the memory cell based on the signal at the output end of the inverter,
A second control circuit controls the charging operation of the first and second capacitors based on the control signal, and a third control circuit controls the discharging operation of the inverter based on the first control signal. I have to.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of a leakage current sensing circuit according to the present invention.

In this embodiment circuit, as in the case of FIG. 10, the N-channel MOS transistor Q2 for the transfer gate is
a leak monitor circuit 11 consisting of a first capacitor C1 and a second capacitor C2, and a P-channel MoS transistor Q3.
and a precharge/discharge type inverter 12 consisting of an N-channel to IOS transistor Q4. The other circuit is the leak monitor circuit 11 mentioned above.
and precharge/discharge type inverter 12
These peripheral circuits control the operation of the circuit, and these peripheral circuits perform the following three functions.

(2) A control signal for starting refresh is generated from the output signal of the precharge/discharge type inverter 12.

(2) Based on the control signal (2), the capacitors C1 and C2 in the leak monitor circuit 11 are recharged so that the leak operation is started with the optimum operating margin.

■ Discharge the output of the precharge/discharge type inverter 12 to prepare for the next leak sense output.

The peripheral circuit that achieves the above-mentioned aspects (1) to (2) is constructed as follows. N6, which is the output node of the precharge/discharge type inverter 12, is connected to the input terminal of the CMOS inverter 21 and the P channel MOS transistor Q11.
connected to the drain of The output terminal of the inverter 21 is connected to the input terminal of the CMOS inverter 22 and the gate of the transistor Q11. The source of the transistor Q11 is connected to the Vool source. The output terminal of the inverter 22 is connected to the input terminal of a seven-band gate circuit 23 and the input terminal of a CMOS inverter 24.

Further, the output terminal of the inverter 24 is connected to the input terminal of the CMOS inverter 25, and the output terminal of this inverter 25 is connected to the CMOS inverter 25.
The input terminal of the OS inverter 2G and the node N11, which is the output terminal of the inverter 26, are connected to different input terminals of the AND gate circuit 23. That is, the inverter 21 and the P-channel MoS transistor Q11 constitute a latch circuit 27 that detects a slight change in the signal at the node N6 and latches the signal. The CMOS inverters 24 to 26 constitute a signal delay circuit 28 which delays the signal latched by the latch circuit 27 and further inverted by the inverter 22 by a time τ1. A refresh control signal, which is a timing signal for starting a refresh operation of a memory cell (not shown), is output from the output node N12 of the AND gate circuit 23.

The input end of the CMOS inverter 29 and one end between the source and drain of the N-channel MO5) transistor Q12 are connected to the node N12. The gate of this transistor Q12 is connected to the VDD power supply, and the thin end between the source and drain is connected to the leak monitor circuit 1.
It is connected to node N2 of the gate of N-channel MOS transistor Q2 in No. 1. The output end of the inverter 29 is connected to the input end of a CMOS inverter 30, and the output end of this inverter 30 is connected in parallel to the input ends of two CMOS inverters 31 and 32, respectively. The output terminal of the inverter 31 is connected to the input terminal of a CMOS inverter 33. As shown in FIG.
It is constructed by inserting a P-channel MOS transistor Q13 whose drain and gate are short-circuited in series between the P-channel MOS transistor Qp and the DD power supply with respect to a normal CMOS inverter consisting of an OS transistor Qn. The output terminal of this inverter 33 is connected to the node N1, which is the drain of the MOS transistor Q2 in the leak monitor circuit 11. Further, the output end of the inverter 32 is connected to the node N4, which is one end of the first capacitor C1 in the leak monitor circuit 11. That is, the two inverters 29 and 30 constitute a signal delay circuit 34 that delays the signal at the node N12 by a time τ2.

Also, the output end of the inverter 30 is connected to another CMOS
Connected to the input end of the inverter 35, this inverter 3
The output terminal of 5 is connected to the input terminal of CMOS inverter 36. That is, both the inverters 35 and 36 constitute a signal delay circuit 37 that further delays the output of the signal delay circuit 34 by a time τ3, and the node N13 which is the output terminal of the inverter 36 at the subsequent stage of this circuit 37 is It is connected to the input end of the NOR gate circuit 38. The inverter 26 is connected to a different input terminal of the NOR gate circuit 38.
The output terminal of this NOR gate circuit 38 is connected to the node N7, which is the gate of the P-channel MO3l to transistor Q4 in the precharge/discharge type inverter 12.

The operation of the circuit configured as described above will be explained with reference to the timing chart of FIG. First, in advance, the node N3
is a potential Vo o -V such that the potential is lower than the power supply potential VDD by the threshold voltage VTP of the P-channel MOS transistor Q13 and higher by the operating margin potential Vmqn.
Assume that T P +Vmgn is set. In this state, the potential of the node N3 decreases due to leakage from the first and second capacitors C1 and C2, and at time t1, the potential of the node N3 decreases to Voo-V
When TR is reached, P-channel MOS transistor Q3 in precharge/discharge type inverter 12 is turned on. If the output node N6 of the inverter 12 is previously discharged to the Vss level, when the transistor Q3 is turned on, the node N6 is precharged to the Voo level. When the signal at node N6 changes slightly due to this precharge, the latch circuit 27
This signal is detected by the inverter 22, and the output of the inverter 22 becomes V
Inverted to DD level. Then, the signal delay circuit 28 lowers the potential of the node N11 to the Vss level at time C4, which is delayed by the time τ1 from the time tl. Then, a pulse signal having a pulse width τ1 is generated from the output node N12 of the acid gate 23 based on the signals at the nodes N6 and N11. This signal is used as a control signal for starting refresh.

Note that the potential of node N3 is set to Voo-VTP+V+u in advance.
qn, the fluctuation in the threshold voltage VTP of the P-channel MO8 transistor Q3 in the precharge/discharge type inverter 12 is ignored. Since the potential of node N3 is set in advance to be lower than Voo by VTP, the potential of node N3 is V m
When the voltage decreases by an amount, the transistor Q3 is turned on regardless of the threshold voltage of the transistor Q3.

Next, the signal at the node N12 is delayed by the signal delay circuit 34 by the time 2, so that at time 2, which is delayed by the time τ2 from the time t1, the potential at the node N1 is lower than the power supply potential vDD of the P-channel MOS transistor. Q1
It is charged to a potential Voo-VTP lower by the threshold voltage VTP of 3. On the other hand, the gate node N2 of transistor Q2
is previously charged to VDD by the signal at node N12 via transistor Q12 at time t1. Therefore, when the drain node N1 of the transistor Q2 is charged to VDD-VTP at time t2, the potential of the node N2 is due to the coupling caused by the capacitor (not shown) that is parasitically generated between the drain and gate of the transistor Q2. is boosted to a sufficiently high potential. As a result, the potential of the node N1 is directly outputted to the node N3 via the transistor Q2. Moreover, at the above time t2,
Due to the output of the inverter 32, the potential of the node N4, which is one end of the first capacitor C1 in the leak monitor circuit 11, decreases to 8s, and at time t5, τ1 after this, the potential is VD.
It rises to D. At this time t5, the node N3 is booted by the coupling of the first capacitor C1,
The potential of node N3 after booting is Vo o as described above.
−VT p + Vmgn L5Q is determined. In this way, the monitoring capacitor is recharged to the optimum potential at time t5, after which leakage begins as described above. Note that the recharging start time (from time t2 to t5) is shorter than the time from the start of leakage to the time of leakage sensing, and leakage during that time can be ignored.

On the other hand, at time t3, which is delayed by the sum of the delay times in the signal delay circuits 34 and 37, τ2+τ3, after the potential at the node N12 rises to VDD, the signal at the output node N13 of the signal delay circuit 37 rises to VDD,
Thereafter, VDD is maintained until time t6. Therefore, the signal at the output node N7 of the NOR gate circuit 38 is maintained at VSS during the period from time t6 when the signal at the node N13 falls to Vss to time t7 when the signal at the node 11 rises to VDD.
o.

be made into During this period, the N-channel MOS transistor Q4 in the precharge-discharge type inverter 12 is turned on, and its output node N6 is discharged to Vss before the next recharge in the leak monitor circuit 11.

As described above, the leakage current sensing circuit of this embodiment can set the refresh operation margin to an optimum value without depending on process changes. Moreover, since it is accompanied by a control circuit that controls the initiation and intermittent interval of the refresh operation, complete automation of the operation can be achieved.

FIG. 4 is a circuit diagram showing the configuration of a second embodiment of the leakage current sensing circuit according to the present invention. This embodiment circuit is different from the embodiment circuit shown in FIG.
Among the monitor capacitors C1 and C2, the first capacitor C1 is connected from the source side to the drain side of the transformer transistor Q2. Accordingly, it is necessary to change the control circuit section that controls capacitor recharging and operation margin setting operations in the leak monitor circuit 11, and only the changed circuit section is extracted and shown in Section 4. It is a diagram. The input terminals of two CMOS inverters 41 and 42 and a 2-OR gate circuit 43 are connected to the node N12.
The input terminals of are connected in parallel. The above inverter 41
The output terminal of 1N is located at one end of the first capacitor C1.
It is connected to 4. The other end of this first kitobashita C1 is the Pji1T channel for the Toran and Zunoa gate ~10S [
- It is connected to the transistor Q2's side rARONO1ζN1. The output terminal of the inverter 42 is 0N1
It is connected to the pano 'J' 4fr of the 10S inverter 44. Both the inverters 42 and 44 are connected to a signal delay circuit 4 which delays the signal at the node N12 by a time τ5.
The output terminal of the inverter 44 is connected to different input terminals of the A agate circuit 43. The output terminal of this OR gate circuit 43 is connected to one end between the source and drain of an N-channel MOS transistor Q14 whose gate is connected to the VDD power supply, and the other end between the source and drain of this transistor Q14 is connected to the node N2.
It is connected to the. Furthermore, the output terminal of the OR gate circuit 43 is connected to the input terminal of an inverter 46. The output terminal of this inverter 46 is sequentially connected to the input terminal of a CMOS inverter 47, and the output terminal of this inverter 47 is sequentially connected to the input terminal of a CMOS inverter 48. A signal delay circuit 49 is configured to delay the signal by the time . The output terminal of the inverter 48 is connected to the input terminal of a CMOS inverter 50. Similar to the inverter 33, this inverter 50 is a P-channel MOS
In contrast to a normal CMOS inverter consisting of a transistor Qp and an N-channel MOS transistor Qn, a P-channel MoS transistor Q15 whose drain and gate are short-circuited is used as a P-channel MoS transistor Qp and ■DD.
It is configured by being inserted in series between the power supply and the power supply. The output terminal of the inverter 50 is connected to the leak monitor circuit 1.
MOS l in 1 - drain node N of transistor Q2
Connected to 1. Note that the signal delay circuit 37 is connected, for example, to the output terminal of the inverter 44.

FIG. 5 is a timing chart showing the operation of this embodiment circuit. First, the potential of node N3 is set to (7) Vo
o-VT P + Vmgn tfi et al. Vo o -V
This potential drop is detected by the precharge/discharge type inverter 12. As a result, when the signal on the node N12 rises to VDD at time t1, the gate node N2 of the transistor Q14 is charged to Voo via the OR gate circuit 43.

Also, at this time, the output signal of the inverter 41 is set to Vss, and the potential of the node N4 is set to Vss. Next, at time t2 after delay time τ4 in the signal delay circuit 49, the output of the inverter 50 causes the node N1 to become Vo o −VT
P is charged. Due to the charging of the node N1, the node N2 is booted to a sufficiently high potential due to the coupling due to the parasitic capacitor between the drain and gate of the transistor Q2, and as a result, the node N3 is boosted to the same potential as the node N1 via the transistor Q2, VDD-VTP. is charged to. Next, at time t3 when the signal at node N12 falls to Vss, the output of inverter 41 is applied to node N1.
2, the potential of the node N1 rises due to coupling by the first capacitor C1, and thereby the potential of the node N3 rises to Voo-VTP+Vun as in the above embodiment. Thereafter, a time t after a delay time τ5 in the signal delay circuit 45
4, the output of the NOR gate circuit 43 is lowered to Vss, and the potential of the node N2 is lowered via the transistor Q14, so that the transistor Q2 is turned off. The subsequent leak operation and discharge operation in the precharge/discharge type inverter 12 are the same as in the above embodiment.

FIG. 6 is a circuit diagram showing the configuration of a third embodiment of the invention. This embodiment circuit differs from the embodiment circuit of FIG. 1 in that it maintains the output node N3 of the leak monitor circuit 11 and the output node N6 of the precharge/discharge type inverter 12 at potential Vss for a predetermined period after power is turned on, and Thereafter, a refresh control signal is automatically generated. Therefore, in this embodiment circuit, first, the output node N3 of the leak monitor circuit 11 and the V
ssi! An N-channel MOS transistor Q2 is connected between the
1 is inserted, and a power-on pulse signal φ is supplied to the gate of this transistor Q21.
In the precharge/discharge type inverter 12, a P channel MOS transistor Q22 is newly inserted in series between the Voo power supply and the P channel MoS transistor Q3, and the nodes N11 and N13 are connected to the NOR gate circuit 38. Instead of connecting to the input terminal of , it is connected to the input terminal of an OR gate circuit 62, and the output terminal of this OR gate circuit 62 is connected to a different input terminal of a Nant gate circuit 63, one input terminal of which is supplied with the power-on pulse signal φ. The output terminal of this Nant gate circuit 63 is connected to the P-channel MOS transistor Q22 and the N-channel MO8t in the precharge/discharge type inverter 12.
- It is connected to node N7 which is the common gate of transistor Q4.

In such a circuit, as shown in the timing chart in FIG. 7, during the period when the pulse signal φ is set to Vss immediately after power is turned on, the transistor Q21 is turned on because the output of the inverter 61 is set to Voo. However, node N3 is set to Vss by this transistor Q21. Furthermore, during the period when the pulse signal φ is set to Ves, the output of the Nant gate circuit 63 is uniquely set to VDD, so that
N in precharge/discharge type inverter 12
Channel MO8t-transistor Q4 is turned on and P-channel MOS transistor Q22 is turned off. Therefore, output node N6 is set to Vss by transistor Q4.

Next, when the pulse signal φ is set to VDD, the output node N11 of the signal delay circuit 28 is set to VDD by the potential of the output node N6 of the precharge/discharge type inverter 12.
Since it is set to DD, the output of the Nant gate circuit 63 is inverted to Vss. As a result, in the precharge/discharge type inverter 12, the N-channel MOS transistor Q4 is turned off, and the P-channel MOS transistor Q2 is turned off.
2 turns on.

On the other hand, in the leak monitor circuit 11, the output node N3 is Vs
s, and in precharge/discharge type inverter 12, P channel MOS transistor Q3 is turned on, so output node N6 is precharged to vDD via both transistors Q22 and Q3. As a result, the output node N12 of the AND gate circuit 23 is set to VDD, and thereafter, after the signal delay time τ2 in the signal delay circuit 34 has elapsed, the node N1 is set to the VDD-VTP potential.

Thereafter, charging is performed in the leak monitor circuit 11 in the same manner as described above, and a refresh control signal is automatically generated.

Note that the N-channel M provided in this embodiment circuit
OS transistors Q23 and Q24 are connected to node N14.
And when N6 is floating, due to leakage,
This is to prevent nodes N14 and N6 from rising to VDD.

It goes without saying that the present invention is not limited to the above-mentioned practical examples and can be modified in various ways.

For example, in the embodiment circuit shown in FIG. 1, the signal delay circuit 28
We have explained the case in which the signal delay circuits 34 and 37 are configured with three inverters connected in cascade, and each of the signal delay circuits 34 and 37 is configured with two inverters connected in cascade. τ1〉τ2, τ3
If the following relationship holds true and the logic between input and output is the same as in the case of Figure 1, how many inverters should each be used?
The signal delay circuit may be constructed by connecting them in series, and furthermore, the signal delay circuit may be constructed using other means instead of an inverter.

[Effects of the Invention] As explained above, according to the present invention, the refresh operation margin can be set to an optimal value without depending on process changes, and the control circuit that controls the start and intermittent interval of the refresh operation is provided. A leakage current sensing circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the leakage current sensing circuit according to the present invention, FIG. 2 is a circuit diagram specifically showing a part of the circuit, and FIG. 3 is a timing diagram of the circuit of the above embodiment. 4 is a circuit diagram showing the configuration of the second embodiment of the present invention, FIG. 5 is a timing chart of the embodiment circuit of FIG. 4, and FIG. 6 is the configuration of the third embodiment of the present invention. 7 is a timing chart of the embodiment circuit of FIG. 6, FIG. 8 is a circuit diagram of a conventional automatic refresh circuit, FIG. 9 is a circuit diagram of an improved conventional automatic refresh control circuit, FIG. 10 is a circuit diagram of a further improved conventional leakage current sensing circuit. 11... Leak monitor circuit, 12... Precharge/discharge type inverter, 23... AND gate circuit, 28.34.37.45.49... Signal delay circuit, 32.33°41...・CMOS inverter, 3
8...Nor gate circuit, C2...N-channel MOS transistor for transfer gate, C12...M
OS transistor, C1゜C2...capacitor. Applicant's Representative Patent Attorney Takehiko Suzue Figure 1 Figure 2 tz ts Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 1, Case Indication Patent Application 1986- No. 179696 No. 2, Name of the invention Leak current sensing circuit 3, Relationship with the amended case Patent applicant (307) Toshiba Corporation 4, Agent 17th Mori Building, 1-26-5 Toranomon, Minato-ku, Tokyo
105 Telephone 03 (502) 3181 (main representative)
(8) Figure 4 of the drawings will be corrected as shown in the attached sheet. 7. Correction details (1) In page 18, lines 811 to 9, [P channel ~
10S transistor Q4J means "N channel MO3"
Correct it to I-transistor Q4J. (2) In the 13th line of page 19, the text "AND gate 23" is corrected to "AND gate circuit 23." (3) In the 13th line of page 23, [P channel MO8l-ransistor Q2j] is corrected to [N-channel MO3I-ransistor Q2J. (4) In the 10th line of page 24, the phrase "inverters 46 to 47" is corrected to "inverters 46 to 48." (5) In the 12th and 13th lines of page 25, correct the text "transistor Q14" to "transistor Q2J." (6) In the 11th and 12th lines of page 26, correct the text "NOR gate circuit 43". Corrected to "OR gate circuit 43." (7) Correct "φ" to "7" in line 9 of page 27, line 17 of page 28, line 5 of page 28, and line 17 of page 28. Figure 4

Claims (6)

[Claims] (1) A transfer gate and first and second capacitors are used to monitor leakage of memory cells that require a refresh operation, and the potential at one end of the first capacitor is increased at a predetermined timing. a leak monitor circuit whose output terminal is discharged in advance, and a transfer gate and a second
a precharge/discharge type inverter whose output terminal is precharged when the potential at the connection point with the capacitor reaches a predetermined value; and a refresh operation of the memory cell is controlled based on a signal at the output terminal of the inverter. a first control circuit that generates a control signal for controlling the first control circuit; a second control circuit that controls charging operations of the first and second capacitors based on the first control signal; A leak current sensing circuit comprising: a third control circuit that controls a discharge operation of the inverter based on a signal. (2) The first control circuit includes a first signal delay circuit that delays a signal at the output end of the inverter for a predetermined time, and is supplied with the output of the first signal delay circuit and the signal at the output end of the inverter. , a first gate circuit that generates a pulse signal of a predetermined length as the first control signal after the signal at the output end of the inverter is inverted, and the second control circuit a second signal delay circuit for delaying the output of the control circuit for a predetermined time; a means for supplying a potential corresponding to the output of the second signal delay circuit to one end of the transfer gate; and one end of the control terminal of the transfer gate. a MOS transistor connected to the MOS transistor and having the other end supplied with the output of the first control circuit, and a signal inverting means that inverts the output of the second signal delay circuit and supplies it to one end of the first capacitor. The third control circuit includes a third signal delay circuit that delays the output of the second signal delay circuit for a predetermined time, and a logical sum to which the outputs of the first and third signal delay circuits are supplied. 2. The leak current sense circuit according to claim 1, wherein the leak current sense circuit comprises a second gate circuit of the type second gate circuit. (3) The first control circuit includes a first signal delay circuit that delays a signal at the output end of the inverter for a predetermined time, and is supplied with the output of the first signal delay circuit and the signal at the output end of the inverter. , a first gate circuit that generates a pulse signal of a predetermined length as the first control signal after the signal at the output end of the inverter is inverted, and the second control circuit a second signal delay circuit that delays the output of the control circuit for a predetermined time; a second gate circuit of an OR type to which the output of the second signal delay circuit and the output of the first control circuit are supplied; a MOS transistor whose one end is connected to the control end of the transfer gate and whose other end is supplied with the output of the second gate circuit; and a third signal delay circuit that delays the signal of the second gate circuit for a predetermined time. , means for supplying a potential corresponding to the output of the third signal delay circuit to one end of the transfer gate; and a signal that inverts the output of the first signal delay circuit and supplies it to one end of the first capacitor. It consists of a reversing means,
The third control circuit includes a fourth signal delay circuit that delays the output of the second signal delay circuit for a predetermined period of time, and a logical OR type circuit to which the outputs of the first and fourth signal delay circuits are supplied. 3. The leakage current sense circuit according to claim 1, wherein the leakage current sense circuit is comprised of a gate circuit of No. 3. (4) The other end of the first capacitor and one end of the second capacitor in the leak monitor circuit are commonly connected to the other end of the transfer gate, and under the control of the second control circuit, 3. The leak current sensing circuit according to claim 2, wherein the potential at one end of the first capacitor is increased after the transfer gate is closed. (5) The other end of the first capacitor in the leak monitor circuit is connected to one end of the transfer gate, and the one end of the second capacitor is connected to the other end of the transfer gate, and the second capacitor is connected to the other end of the transfer gate. 4. The leakage current sensing circuit according to claim 3, wherein the transfer gate is closed after the potential at one end of the first capacitor is raised under control. (6) means for discharging the connection point between the second capacitor and the transfer gate in the leak monitor circuit in response to a pulse signal generated when power is turned on;
2. The leak current sensing circuit according to claim 1, further comprising means for causing said precharge/discharge type inverter to perform a discharge operation in response to said pulse signal.