JPS6242523A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6242523A
JPS6242523A JP18228985A JP18228985A JPS6242523A JP S6242523 A JPS6242523 A JP S6242523A JP 18228985 A JP18228985 A JP 18228985A JP 18228985 A JP18228985 A JP 18228985A JP S6242523 A JPS6242523 A JP S6242523A
Authority
JP
Japan
Prior art keywords
resist film
film
resist
hole
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18228985A
Other languages
Japanese (ja)
Inventor
Seiji Kawanako
川那子 誠二
Masao Kanazawa
金沢 政男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18228985A priority Critical patent/JPS6242523A/en
Publication of JPS6242523A publication Critical patent/JPS6242523A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the dimension control of a contact hole by a method wherein a hole is formed with isotropic etching, and after a resist film has been baked, a mask by means of the second resist film is formed on an opening section and etched. CONSTITUTION:An insulation film 12 and the first positive-type resist film 13 are formed on a substrate 11 in order, and the film 13 is patterned. Then, a hole 14a' is formed with the film 13 as a mask with isotropic etching. The film 13 is baked with irradiation of far ultra violet ray to increase the absorption ratio of ultra violet ray. After that, the same kind of a resist as the film 13 is coated so that the hole 14 is completely filled to form the second resist film 14. Then, it is exposed, developed, and etched with the section 14a of the film 14 remaining under the opening 13a as a mask until it reaches the substrate 11. With this method, the etching advances in accordance with the shape of the hole, thereby forming the contact hole, with favorably controlled its dimension and shape.

Description

【発明の詳細な説明】 〔概要〕 半導体装置の製造においてコンタクトホールを形成する
際に、コンタクトホールの寸法制御性を改善する方法で
ある。
DETAILED DESCRIPTION OF THE INVENTION [Summary] This is a method for improving the dimensional controllability of contact holes when forming contact holes in the manufacture of semiconductor devices.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法に関するもので、さらに
詳しく言えば、半導体基板表面に形成された絶縁膜にコ
ンタクトホールを形成しそこに電極を設けるに際して、
コンタクトホールを寸法制御性よく形成する方法に関す
るものである。
The present invention relates to a method for manufacturing a semiconductor device, and more specifically, when forming a contact hole in an insulating film formed on the surface of a semiconductor substrate and providing an electrode therein,
The present invention relates to a method for forming contact holes with good dimensional control.

〔従来の技術〕[Conventional technology]

半導体基板と接続(コンタクト)をとる方法を第2図を
参照して説明すると、同図(a)に示される如く半導体
基板21の表面に形成された絶縁膜22上にホトレジス
ト (以下レジストという)の膜23を形成し、レジス
ト膜23を図示の如くにパターニングして現像後に残っ
たレジストをマスクにして絶縁膜22の斜線を付した部
分をエツチングして除去するとコンタクトホール24が
形成される。次いで同図fb)に示される如くに[25
を被着し、コンタクトホール24をAlで埋めて基板と
のコンタクトをとる。コンタクトホールは平面図で見る
と直径が例えば1.5〜2.0μmの円形の穴である。
The method of making a connection (contact) with a semiconductor substrate will be explained with reference to FIG. 2. As shown in FIG. A contact hole 24 is formed by forming a film 23, patterning the resist film 23 as shown, and etching and removing the diagonally shaded portion of the insulating film 22 using the resist remaining after development as a mask. Then, as shown in fb) of the same figure, [25
The contact hole 24 is filled with Al to make contact with the substrate. The contact hole is a circular hole with a diameter of, for example, 1.5 to 2.0 μm when viewed in a plan view.

従って、第2図falに見てコンタクトホール24の横
方向寸法は1.5〜2.0μmのものとなる。
Accordingly, as seen in FIG. 2 fal, the lateral dimension of the contact hole 24 is 1.5 to 2.0 μm.

上記した絶縁膜22のエツチングは異方性エツチングで
あり、レジスト膜23のパターンの通りの真直ぐに立っ
たコンタクトホールが作られるのであるが、このような
コンタクトホールにAI!を被着すると、 Alは第2
図fb)に示されるように堆積し、部分25aで不連続
線が形成され、そこで断線するおそれがある。
The above-mentioned etching of the insulating film 22 is anisotropic etching, and a contact hole standing straight according to the pattern of the resist film 23 is created. When deposited, Al becomes the second
As shown in FIG.

このようなコンタクトホールにおける八2のカバレッジ
(密着性)の問題点を改善するために第3図に示される
コンタクトホールの形成方法が開発された。第3図を参
照すると、前記した場合と同様に半導体基板2I上の絶
縁膜22の上にレジスト膜23を形成しそれを同図(a
)に示す如くにパターニングし、最初等方性エツチング
で同図(b)に示す如く絶縁膜22の膜厚の半分程度を
エツチングし、次いで異方性エツチングで絶縁膜22の
残りの部分をエツチングすると、同図(C)に示される
如くレジスト11ffのパターンと同じ幅のコンタクト
ホールが形成され、レジストを除去しコンタクトホール
にAI!を被着すると、コンタクトホールは上方部分が
ゆるやかに1頃斜した形状であるので、第2図(blを
参照して説明した問題が解決され、A7!のカバレッジ
が良くなる。
In order to improve the coverage (adhesion) problem of contact holes, a method for forming contact holes as shown in FIG. 3 was developed. Referring to FIG. 3, a resist film 23 is formed on the insulating film 22 on the semiconductor substrate 2I in the same way as in the case described above.
), and first, about half of the thickness of the insulating film 22 is etched by isotropic etching as shown in FIG. As a result, a contact hole having the same width as the pattern of the resist 11ff is formed as shown in FIG. Since the upper part of the contact hole has a gently slanted shape, the problem explained with reference to FIG. 2 (bl) is solved and the coverage of A7! is improved.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前記した異方性エンチングは、露出される基板の表面を
削ってきれいにしAlとの良好なコンタクトがとりうる
ように、余分にエツチングされる(オーバーエツチング
)。かかるオーバーエツチングにおいて、絶縁膜22が
第3図(C)に矢印Iで示す方向にエツチングされ、そ
の結果、コンタクトホールが同図に矢印■で囲む範囲に
形成されなければならないのに、それが図に見て右また
は左にずれて、所定のコンタクトホールの径が例えば2
゜0μmであるべきところそれよりも大なる径のコンタ
クトホールが形成される問題がある。
In the above-mentioned anisotropic etching, the surface of the substrate to be exposed is scraped and cleaned so that good contact with Al can be made by excessively etching (over-etching). In such over-etching, the insulating film 22 is etched in the direction shown by arrow I in FIG. If the contact hole is shifted to the right or left as shown in the figure, the diameter of the predetermined contact hole is, for example, 2
There is a problem in that a contact hole that should have a diameter of 0 μm is formed with a diameter larger than that.

本発明はこのような点に鑑みて創作されたもので、コン
タクトホールを形状、寸法の制御性良く形成する方法を
提供することを目的とする。
The present invention was created in view of these points, and an object of the present invention is to provide a method for forming a contact hole with good controllability in shape and size.

〔問題点を解決するための手段〕[Means for solving problems]

第1図は本発明の方法を実施する工程における半導体装
置の要部すなわちコンタクトホール形成部分の断面図で
ある。
FIG. 1 is a sectional view of a main part of a semiconductor device, that is, a contact hole forming part, in a step of carrying out the method of the present invention.

第1図において、そのfa)に示される如く、半導体基
板11上の絶縁膜12の上にポジ型レジストで第1のレ
ジスト膜13を形成し、レジスト膜13をパターニング
して後にレジスト膜13をマスクに等方性エツチングで
絶縁膜12を部分的にエツチングし、次いで同図(b)
に矢印で示す如く遠紫外線を照射すると共にレジストを
ベークし、次に同図(C)に示される如く第1のレジス
ト膜と同種のレジストを全面に塗布して絶縁膜のエツチ
ングされた部分を完全に埋める第2のレジスト膜15を
塗布し、次いで同図(dlに矢印で示される如く近紫外
線を全面に照射してレジスト膜15を露光し、現像して
レジスト膜13のひさし状の開口部13aの下に第2の
レジスト膜部分15aを残しく第3図(e))、次いで
レジスト膜13とレジスト膜部分15aをマスクにして
異方性工・ノチングで絶縁膜12の残った部分をエツチ
ングする。
In FIG. 1, as shown in fa), a first resist film 13 is formed using a positive resist on an insulating film 12 on a semiconductor substrate 11, and the resist film 13 is patterned. The insulating film 12 is partially etched by isotropic etching using a mask, and then the insulating film 12 is etched as shown in FIG.
As shown by the arrow, the resist is irradiated with deep ultraviolet rays and baked, and then a resist of the same type as the first resist film is applied to the entire surface as shown in FIG. A second resist film 15 is applied to completely fill the area, and then the entire surface of the resist film 15 is exposed to near ultraviolet rays as shown by the arrow in dl in the same figure (dl), and developed to form an eave-shaped opening in the resist film 13. The second resist film portion 15a is left under the portion 13a (FIG. 3(e)), and then the remaining portion of the insulating film 12 is etched by anisotropic etching and notching using the resist film 13 and the resist film portion 15a as masks. etching.

〔作用〕[Effect]

ポジ型レジストはベークすると紫外線の吸収率が高くな
るので、第2のレジストのマスクになり、レジスト膜1
3のひさし状の開口部13aの下に第2のレジスト膜部
分15aが残り、見かけ上異方的なホールが形成され、
次いで異方性エツチングを行うと前記した異方的ホール
の形状どおりにエッチングが進行するので、コンタクト
ホールが寸法、形状ともに制御性よく形成されるのであ
る。
When a positive resist is baked, its absorption rate of ultraviolet rays increases, so it becomes a mask for the second resist, and the resist film 1
The second resist film portion 15a remains under the eave-shaped opening 13a of No. 3, and an apparently anisotropic hole is formed.
When anisotropic etching is then performed, the etching progresses in accordance with the shape of the anisotropic hole described above, so that the contact hole can be formed with good controllability in both size and shape.

〔実施例〕〔Example〕

以下、再び第1図を参照して本発明の実施例を詳細に説
明する。
Hereinafter, embodiments of the present invention will be described in detail with reference to FIG. 1 again.

第1図(al参照: 半導体基板11上に例えば燐・シリケート・ガラス(P
SG ’)で1μmの膜厚の絶縁膜12を形成し、その
上に1μmの厚さにポジ型レジスト(例えば東京応化■
の0FPR−800なる商品名のレジスト)を塗布して
第1のレジスト膜13を形成し、レジスト膜13をパタ
ーニングした後にレジスト膜13をマスクにして、絶縁
膜12を部分的に、等方性エツチングで例えばその最初
の膜厚の半分程度エツチングしてホール14aを形成す
る。それには、フン酸(HF)系のエッチャントを用い
るウェットエツチングか、CF4系のガスを用いるドラ
イエツチングによる。かかるエツチングによって絶縁P
t112は上下方向だけでなく横方向にもエツチングさ
れホール14aはなだらかな形状をとり、またレジスト
膜13の開口部13aの下の絶縁膜も除去されるので、
開口部13aはひさし状にオーバーハングする。
FIG. 1 (see al: For example, phosphorus silicate glass (P) is placed on the semiconductor substrate 11.
An insulating film 12 with a thickness of 1 μm is formed using SG'), and a positive resist (for example, Tokyo Ohka Chemical Co., Ltd.
A first resist film 13 is formed by applying a resist (trade name: 0FPR-800), and after patterning the resist film 13, the insulating film 12 is partially isotropically formed using the resist film 13 as a mask. The hole 14a is formed by etching, for example, about half the initial film thickness. This can be done by wet etching using a hydronic acid (HF) based etchant or by dry etching using a CF4 based gas. By such etching, the insulation P
Since t112 is etched not only in the vertical direction but also in the horizontal direction, the hole 14a has a gentle shape, and the insulating film under the opening 13a of the resist film 13 is also removed.
The opening 13a overhangs like a canopy.

第1図(b)参照: 次に図に矢印で示す如く全面的に遠紫外光を照射しなが
ら、約200°Cの温度でレジスト膜13をベークする
。ポジ型レジストは前記の温度でベータすると紫外線の
吸収率が高くなりマスク性がよくなる。
See FIG. 1(b): Next, the resist film 13 is baked at a temperature of about 200° C. while irradiating the entire surface with deep ultraviolet light as indicated by the arrow in the figure. When a positive resist is beta-aged at the above-mentioned temperature, its ultraviolet absorption rate increases and its maskability improves.

第1図(C)参照: 第1のレジスト膜と同じレジストをスピンコード法で塗
布しホール14aを埋めると、第1のレジスト膜13の
上方もレジスト膜15で薄く覆われる。
Refer to FIG. 1C: When the same resist as the first resist film is applied by the spin code method to fill the hole 14a, the upper part of the first resist film 13 is also thinly covered with the resist film 15.

レジスト膜15はスピンコード法で塗布し形成するので
、レジスト膜13のひさし状の開口部13aの下方も完
全に同じレジストで埋められる。なお、ホール14aを
ドライエツチングで形成したときは、第2のレジストの
塗布のときのぬれ性を良くするために、絶縁膜の表面を
例えば02プラズマでアッシングするとよい。
Since the resist film 15 is formed by coating by a spin code method, the lower part of the eave-shaped opening 13a of the resist film 13 is also completely filled with the same resist. Note that when the hole 14a is formed by dry etching, it is preferable to ash the surface of the insulating film using, for example, 02 plasma in order to improve the wettability when applying the second resist.

第1図(d)参照: 近紫外線を図に矢印で示す如く照射し、第2のレジスト
膜15を全面露光する。
Refer to FIG. 1(d): Near ultraviolet rays are irradiated as shown by the arrows in the figure to expose the entire surface of the second resist film 15.

第1図+e+参照: 次いで第2のレジスト膜15を現像する。レジスト膜1
3は前記した如くベークされ、紫外線の吸収率が高くな
っているので、第1図(d)を参照して説明した近紫外
線の照射においては、開口部13aの下方の第2のレジ
ストには近紫外線が透過していないので、開口部13a
の下には第2のレジスト膜部分15aが残り、見かけ上
異方的な第ルジスト膜13の開口と同じ形状、寸法のホ
ール14bが作られる。
See FIG. 1+e+: Next, the second resist film 15 is developed. Resist film 1
3 has been baked as described above and has a high absorption rate of ultraviolet rays, so in the near ultraviolet ray irradiation described with reference to FIG. 1(d), the second resist below the opening 13a is Since near ultraviolet rays are not transmitted, the opening 13a
A second resist film portion 15a remains below, and a hole 14b having the same shape and size as the apparently anisotropic opening of the resist film 13 is formed.

第1図(f)参照: 第ルジスト膜13と残った第2レジスト15aをマスク
にし異方性エツチングで、絶縁膜12の残った部分をエ
ツチングする。このエツチングはオーバーエツチングに
して基板11の表面をきれいにするが、ホール14bは
前記した如く所定の形状、寸法で作られているから、こ
のオーバーエツチングで最終的に形成されるコンタクト
ホール14は寸法、形状共に制御性よく作られる。続い
てレジストをすべて除去し、所定のi電極を形成する。
Refer to FIG. 1(f): Using the first resist film 13 and the remaining second resist 15a as a mask, the remaining portion of the insulating film 12 is etched by anisotropic etching. This etching cleans the surface of the substrate 11 by over-etching, but since the hole 14b is made with a predetermined shape and size as described above, the contact hole 14 finally formed by this over-etching has a certain size. Both shape and shape can be easily controlled. Subsequently, all the resist is removed and a predetermined i-electrode is formed.

本発明の他の実施例においては、第2のレジストに第1
のレジストとは異なった電子ビーム(EB)、遠紫外線
に感光するレジスト、例えばPMMAを用いる。その場
合の工程は前記実施例の場合と同様であるが、このレジ
ストは解像力が高いので、遠紫外線を用いる微細パター
ンの形成に有効である。
In other embodiments of the invention, the second resist includes a first resist.
A resist that is sensitive to electron beams (EB) and deep ultraviolet rays, such as PMMA, is used, which is different from the resist used in the above. The steps in this case are the same as those in the previous example, but since this resist has high resolution, it is effective in forming fine patterns using deep ultraviolet rays.

〔発明の効果〕〔Effect of the invention〕

以上性べてきたように、本発明によれば、コンタクトホ
ールが形状と寸法共に制御性よく形成され、コンタクト
ホールに作るi配線の断線のおそれがなくなり、またレ
ジストの種類を選ぶことにより微細なコンタクトホール
が形成されうる効果がある。
As described above, according to the present invention, a contact hole can be formed with good controllability in terms of shape and size, there is no risk of disconnection of the i-wire formed in the contact hole, and fine control can be achieved by selecting the type of resist. This has the effect that a contact hole can be formed.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)ないしくf)は本発明実施例の断面図、第
2図と第3図は従来例の断面図である。 第1図において、 11は半導体基板、 12は絶縁膜、 13は第1のレジスト膜、 13aは第1のレジスト膜の開口部、 14はコンタクトホール、 14aと14bはホール、 15は第2のレジスト膜、 15aは開口部の下に残る第2のレジスト膜部分である
。 奉イしe月 9ζ方話例1午1t7 巴9第1図
FIGS. 1(a) to 1(f) are sectional views of an embodiment of the present invention, and FIGS. 2 and 3 are sectional views of a conventional example. In FIG. 1, 11 is a semiconductor substrate, 12 is an insulating film, 13 is a first resist film, 13a is an opening in the first resist film, 14 is a contact hole, 14a and 14b are holes, and 15 is a second resist film. The resist film 15a is the second resist film portion remaining under the opening. Houishi e month 9ζ dialect example 1 no. 1t7 Tomoe 9 Fig. 1

Claims (1)

【特許請求の範囲】 半導体基板(11)上に絶縁膜(12)と第1のレジス
ト膜(13)を順に形成し、形成すべきコンタクトホー
ルに対応してパターニングした該レジスト膜(13)を
マスクにする等方性エッチングで絶縁膜(12)を部分
的にエッチングしてホール(14a)を形成する工程、 前記レジスト膜(13)を遠紫外線を照射しつつベーク
する工程、 前記レジスト膜(13)と同じ種類のレジストをホール
(14a)が完全に埋る程度に全面に塗布し第2のレジ
スト膜(15)を形成する工程、近紫外線を照射し第2
のレジスト膜(15)を全面露光する工程、および 第2のレジスト膜(15)を現像し、第1のレジスト膜
(13)と該レジスト膜(13)の開口部(13a)の
下に残った第2のレジスト膜部分(15a)をマスクに
絶縁膜(12)を基板(11)に達するまでエッチング
する工程を含むことを特徴とする半導体装置の製造方法
[Claims] An insulating film (12) and a first resist film (13) are sequentially formed on a semiconductor substrate (11), and the resist film (13) is patterned in correspondence with contact holes to be formed. a step of partially etching the insulating film (12) using isotropic etching using a mask to form a hole (14a); a step of baking the resist film (13) while irradiating it with deep ultraviolet rays; Step 13) of applying the same type of resist to the entire surface to completely fill the hole (14a) to form a second resist film (15);
A step of exposing the entire surface of the resist film (15) to light, and developing the second resist film (15) so that the resist film (15) remains under the first resist film (13) and the opening (13a) of the resist film (13). A method for manufacturing a semiconductor device, comprising the step of etching the insulating film (12) using the second resist film portion (15a) as a mask until it reaches the substrate (11).
JP18228985A 1985-08-20 1985-08-20 Manufacture of semiconductor device Pending JPS6242523A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18228985A JPS6242523A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18228985A JPS6242523A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6242523A true JPS6242523A (en) 1987-02-24

Family

ID=16115677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18228985A Pending JPS6242523A (en) 1985-08-20 1985-08-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6242523A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8007967B2 (en) * 2005-06-29 2011-08-30 Lg Display Co., Ltd. Shadow mask and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8007967B2 (en) * 2005-06-29 2011-08-30 Lg Display Co., Ltd. Shadow mask and manufacturing method thereof

Similar Documents

Publication Publication Date Title
US5023203A (en) Method of patterning fine line width semiconductor topology using a spacer
US4523976A (en) Method for forming semiconductor devices
JPH0588375A (en) Formation of resist pattern
US4362598A (en) Method of patterning a thick resist layer of polymeric plastic
EP0859400A3 (en) Improvements in or relating to integrated circuits
JPS6242523A (en) Manufacture of semiconductor device
JPH04348030A (en) Inclined etching method
JPH07105375B2 (en) Method for manufacturing thin conductor device
JPH06244156A (en) Formation of pattern
JP3119021B2 (en) Method for forming contact hole in semiconductor device
JPH0467333B2 (en)
JPH0774087A (en) MLR pattern forming method
JPS6236827A (en) Method for selective etching
KR100359787B1 (en) Method for fabricating of pattern
JPH0670954B2 (en) Method for manufacturing semiconductor device
JPS6035821B2 (en) Manufacturing method of semiconductor device
JPH038338A (en) Manufacture of multilayer wiring structure
JPH0348424A (en) Manufacture of semiconductor device
JPS62200732A (en) Manufacture of semiconductor device
JPS6154629A (en) Forming process of photoresist pattern
JPS6276723A (en) Forming method for resist pattern on substrate
JPS63292649A (en) Manufacture of semiconductor device
JPS6236828A (en) Method for selective etching
JPH0225251B2 (en)
JPH03108314A (en) Manufacture of semiconductor element