JPS6242531B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mismatch circuit that outputs a mismatch signal only when the phases of two input signals that repeatedly change are complementary to each other.

Conventionally, an exclusive OR circuit is typically known as this type of mismatch circuit.

However, in this exclusive OR circuit, when the two input signals are repetitive signals with a predetermined period,
When one of the input signals is fixed to logic "1" or logic "0", or even when it is fixed to the opposite state, a mismatch signal corresponding to the repetition period of the other input signal is generated. will be output. Therefore, by using such an exclusive OR circuit, a command signal is output to orbit equipment, etc. only when the two input signals are both repetitive signals and their phases are complementary to each other. The mismatch circuit has the disadvantage that even though one of the input signals is abnormal, an incorrect command signal (mismatch signal) is output, making it impossible to ensure the safe operation status of track equipment, etc. have. That is, it has a drawback that fail-safe properties cannot be ensured.

The present invention has been made to solve these drawbacks, and is designed to ensure fail-safe performance not only when two input signals that repeatedly change in a complementary relationship are abnormal, but also when a circuit element in a mismatched circuit breaks down. The object of the present invention is to provide a mismatch circuit that can be ensured.

Hereinafter, the present invention will be explained in detail based on illustrated embodiments.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, 1 voltage-double rectifies two input signals S ₁ and S ₂ that share a common potential point such as a ground circuit and repeat changes in a complementary relationship with each other.
A voltage doubler rectifier circuit that outputs a positive voltage +Vc and a negative voltage -Vg with the common terminal COM as a reference,
It consists of diodes D ₁ , D ₂ and capacitors C ₁ , C ₂ .

2 is an oscillation circuit that outputs an oscillation signal F of a predetermined frequency only when both a positive voltage +Vc and a negative voltage -Vg are output from the voltage doubler rectifier circuit 1 to the common terminal COM, and 3 rectifies the oscillation signal F. , whose rectified output is the mismatch signal S ₃ of the two complementary input signals S ₁ and S ₂
A rectifier circuit that outputs a transformer T,
It consists of a diode _D3 and a capacitor _C3 .

Here, the oscillation circuit 2 is, for example, a field effect transistor, as shown in the part surrounded by the dashed line in FIG.
Consists of a phase-shifted oscillation circuit using FETs. Third
In the figure, R _D is a drain resistance, R ₄ is a gate bias resistance, and a portion consisting of resistors R ₁ to R ₃ , capacitors C ₄ to _{C 7} , and field effect transistor FET constitutes a CR phase shift oscillator. The oscillation signal obtained from the drain output of the field effect transistor FET is amplified by the transistor Q to drive the transformer T. In such a configuration, the operating characteristics of the field effect transistor FET are that, as shown in Fig. 4, it oscillates at operating point B only when the positive voltage +Vc and the negative voltage -Vg are both predetermined values, and when the negative voltage -Vg is If it is not a predetermined value, the operating point A is reached, the field effect transistor FET is saturated, and oscillation is stopped. Therefore, such an oscillation circuit 2 outputs an oscillation signal of a predetermined frequency only when the positive voltage +Vc and the negative voltage -Vg are both predetermined values.

The oscillation signal F from the oscillation circuit 2 is supplied to the diode _D3 via the transformer T.
The collector of transistor Q in oscillation circuit 2
This is to prevent a short-circuit failure between the emitters and supplying logic "1" (+Vc) to the diode _D3 .

The operation of the mismatch circuit configured as described above will be explained using the time chart shown in FIG.

First, as shown in section T _A in FIG. 2, if the input signals S ₁ and S ₂ whose return paths are connected to the common potential are not together, neither the positive voltage +Vc nor the negative voltage -Vg will be generated. Therefore, the oscillation signal F is not generated, and the mismatch signal output _S3 of the rectifier circuit 3 becomes logic "0".

However, in the interval T _B , the input signals S ₁ and S ₂ repeat changes in a complementary relationship with each other, so a positive voltage +Vc and a negative voltage -Vg are both generated, and the oscillation circuit 2 oscillates at a predetermined frequency. Outputs signal F. As a result, the mismatch signal output _S3 of the rectifier circuit 3 becomes logic "1" in the interval _T.sub.B. That is, since the phases of the input signals S ₁ and S ₂ that repeatedly change are completely complementary, a mismatch signal S ₃ of logic "1" is output.

Next, in the section T _c , the phase relationships in which the input signals S ₁ and S ₂ repeat changes are the same. Therefore, neither the positive voltage +Vc nor the negative voltage -Vg is generated, and the mismatch signal output _S3 becomes logic "0" as in the case of the section T _A.

However, in Fuma _TD , only the input signal _S1 is repeatedly input, and the input signal _S2 is at logic "0". Therefore, a positive voltage +Vc is generated, but
Negative voltage -Vg is not generated. Therefore, the oscillation operation of the oscillation circuit 2 is stopped. As a result, the mismatch signal output _S3 becomes logic "0".

In _the interval T _E , the input signal is
Only S ₂ is input repeatedly. Therefore, only negative voltage -Vg is generated, and positive voltage +Vc is not generated. Therefore, the oscillation signal F is not generated and the mismatch signal output _S3 becomes logic "0". Additionally, the input signal
S ₁ is “0”, the same signal S ₂ is “1”, or the input signal
Even if _S1 is fixed to "1" and the signal _S2 is fixed to "0", the oscillation signal F is not generated and the mismatch signal output _S3 becomes "0". In this way, in this embodiment, only when both the input signals S ₁ and S ₂ are repeatedly input and the phases of the repeated changes are complementary to each other,
A mismatch signal _S3 of logic "1" is output. Also,
If an element of each circuit fails, the oscillation signal F is no longer output, so the mismatch signal _S3 becomes logic "0", ensuring fail-safety.

FIG. 5 is a circuit diagram showing another embodiment of the oscillation circuit 2. In FIG. In the figure, transistors Q ₁ , Q ₂ ,
Resistance RC ₁ , RC ₂ , RB ₁ , RB ₂ , Capacitor CC ₁ ,
CC ₂ constitutes a complementary self-propelled multivibrator.

This circuit is basically the same as a collector-coupled free-running multivibrator, but its feature is that it is configured in a complementary type by using an NPN transistor for _Q1 and a PNP transistor for _Q2 .
Therefore, in this circuit, transistor Q ₁
It oscillates only when a positive voltage +Vc is applied to the transistor Q2 and a negative voltage -Vg is applied to the transistor _Q2 .

With this, the same effect as in the case of FIG. 3 can be obtained. In particular, this case has the advantage of reducing the number of parts. Note that the transistors Q ₃ and RE ₁ in FIG. 5 correspond to Q and R ₅ in FIG. 3.

As is clear from the above description, according to the present invention, fail-safe performance is always ensured, not only when two input signals that repeat changes in a complementary relationship with each other are abnormal, but also when the circuit elements of the mismatching circuit itself fail. can. Therefore, if applied to orbital equipment, etc., it will exhibit extremely effective effects.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a time chart to explain its operation,
FIG. 3 is a circuit diagram showing a detailed configuration example of the oscillation circuit, FIG. 4 is a diagram showing its operating characteristics, and FIG. 5 is a circuit diagram showing another embodiment of the oscillation circuit. 1...Voltage doubler rectifier circuit, 2...Oscillation circuit, 3...
...rectifier circuit.

Claims (1)

[Claims] 1 A voltage doubler rectifier circuit that doubles and rectifies two input signals that share a common potential and repeat changes in a complementary relationship to each other and outputs a positive voltage and a negative voltage with a common terminal as a reference, and a voltage doubler rectifier circuit that outputs a positive voltage and a negative voltage with the common terminal as a reference, and An oscillation circuit that outputs an oscillation signal only when both are output to a common terminal, and a rectifier circuit that rectifies the oscillation signal via a transformer and outputs the rectified output as a mismatch signal between the two input signals. A mismatched circuit characterized by: