JPS6242536B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a receiving device using a phase combining diversity method. Conventionally, a phase combining type space diversity receiving apparatus is constructed as shown in the block diagram of FIG. That is, one of the signals received from the two antennas 1 and 2 placed at a predetermined interval is adjusted in phase by the phase control section 3, and combined with the other received signal by the hybrid 4 and sent to the output terminal 8. Output. At this time, a constant phase modulation is applied to the received signal by a phase modulator 6 for detecting phase fluctuations. When this phase-modulated received signal is combined with another received signal, amplitude fluctuations occur due to the difference in phase vectors. This vibration fluctuation is detected by the amplitude detector 5, and the rotary phase shifter 7 is controlled so that the amplitude modulation component is minimized. The received signals combined in this way are controlled to be in phase. Since the phase modulator 6 and rotary phase shifter 7 used here both provide phase changes, it is uneconomical to use two phase controllers. Further, the mechanical rotary phase shifter 7 rotated using a conventional motor has a problem of low reliability and slow response speed. Furthermore, an electrical endless phase shifter that electrically controls the phase using a digital circuit is described in 1971, Proceedings of the Four Electrical Engineers of Japan, No. 2353 (hereinafter referred to as the document). In this case, since the error voltage corresponding to the phase difference is digitized and used as the control voltage, this A/D converter and a D/A converter that converts the trigonometric function are required, making the overall configuration complicated. I was getting used to it. SUMMARY OF THE INVENTION An object of the present invention is to provide a phase synthesis space diversity receiver in which a single phase modulator performs phase modulation and phase shifting operations. Another object of the present invention is to provide a phase synthesis space diversity receiving device that achieves high reliability and high speed by solid-state electronic circuitry using simplified digital circuits. According to the present invention, one of the signals received from two antennas installed at a predetermined interval has a predetermined angle of 360°/N (where N is a natural number) corresponding to a predetermined digital control value. A phase shift circuit that performs a phase shift by an integer multiple, a signal synthesis circuit that synthesizes the output of this phase shift circuit and the output of the received signal that is not input to this phase shift circuit, and a phase fluctuation of the output of this signal synthesis circuit. includes an amplitude detector that detects the amplitude fluctuation value as an amplitude fluctuation value, and a phase shift control circuit that forms a predetermined digital control value according to the output of the amplitude detector. A frequency divider that divides the clock to generate an up-down signal with the same up and down periods, and a phase-amplitude detector synchronized with the period of this up-down signal, which is received from two antennas. A phase detector that detects the match or mismatch in phase of each signal as a polarity, a pulse control circuit that controls a predetermined input clock or up-down signal in accordance with this polarity, and creates a counting signal and an up-down control signal, and an up-down control It is composed of an N-ary up-down counter that counts up or down the counting signal according to the signal and outputs a predetermined digital control value, and the pulse control circuit is configured as an up-down counter so that the phase fluctuation of the output of the signal synthesis circuit is reduced. A phase synthesis type space diversity receiving device is obtained, which is characterized by controlling the counting of . The present invention will be explained in detail below with reference to the drawings. FIG. 2 is a block diagram of an embodiment of the invention. In the figure, 101 indicates memories 25, 26, D/A converters 27, 28, balanced modulators 29, 30, and
This is a phase shift circuit consisting of a 90° hybrid 31.
102 is a phase shift control circuit consisting of a pulse generator 20, a frequency divider 21, a pulse control circuit 22, an up/down counter 23, and a phase detector 24. 1
0 is an input terminal for the RF signal, 11 is an output terminal for the RF signal, and 12 is an input terminal for the demodulated amplitude modulation component. First, pulses are generated by the pulse generator 20 with a repetition frequency of about 1 KHz based on the response speed of the phase control system. This pulse is divided into two parts, one of which is divided by the frequency divider 21, resulting in a waveform with a duty of 50%.The up-down counter 23 (for example, a hexadecimal counter) switches between up-counting and down-counting. Connected to input U/D. This counter 23 performs up-counting and down-counting alternately for equal periods of time (see FIG. 3a). The other pulse from the pulse generator 20 passes through the pulse control circuit 22 to the clock input CL of the counter 23 (repetition frequency 1KHz).
becomes. The output pulse of this pulse control circuit 22 is synchronized with the output of the frequency divider 21, and if the phases of the two synthesized waves match, the output from the phase detector 24 becomes zero, so as shown in FIG. As shown in a,
Clock pulses equal to both the up-count and down-count periods are supplied to the counter 23. The output of the up-down counter 23 (for example,
0101=5) is connected to the memories 25 and 26, respectively, and 90 corresponds to this count number (for example, 5).
Outputs each weighted with a sine wave shifted by 0.0 degrees are read out, and these outputs are sent to the D/A converter 27,
28, each is converted into an analog quantity. Balanced modulators 29, 30 according to these analog signals
The branched received signals are amplitude modulated.
These modulation signals are generated by a 90° hybrid 31
By combining the signals with a phase shift of 90 degrees, a phase modulated signal according to the analog signal is output to the received signal. This principle of operation is explained in the aforementioned documents. The contents of the memories 25 and 26 correspond to the output of the N-ary up-down counter 23, and the output amplitude of the output signal is constant and the phase divides the circumference into N equal parts.
As shown in the figure, as the value of N increases to 0, 1, and 2, the phase also corresponds to change to points 0, 1, and 2 on the circumference. For example, when N=16, the phase can be controlled every 22.5 degrees, and the relationship in this case is shown, for example, in Table 1.

[Table] This table shows the memory 2 corresponding to the counter output.
5 indicates a cosine wave output value, and memory 26 stores a sine wave output value shifted by 90 degrees from the cosine wave output value. According to this table, for example, when the counter output is "0101 (=5)", this "5"
In response to this, the memory 25 reads "-0.4",
Memory 26 reads "0.9" and D/A converters 27 and 28 convert these numbers into analog voltages. When the received signal is subjected to amplitude modulation corresponding to "-0.4" and "0.9" by the balanced modulators 29 and 30 using these analog voltages, the received output synthesized by the 90° hybrid 31 is "112.5" relative to the received signal. This shows that a phase shift of 1.5° is generated. Furthermore, if the phases of the two synthesized waves do not match, the phase detector 24 outputs a positive or negative voltage according to the phase shift. Depending on whether the output voltage of the phase detector 24 is positive or negative, the pulse control circuit 22 generates one extra clock pulse during the up-count or down-count period, as shown by the dotted line in FIG. 3b or 3c. occurs.
This inserted pulse can be created, for example, by inserting a pulse delay circuit into the corresponding period of up-counting or down-counting. With this configuration, when the two combined received waves are in phase and the output of the phase detector 24 is zero, the counter 23 repeats up-counting and down-counting an equal number of times. That is, since the output of the counter 23 changes as 0 → 1 → 2 → 1 → 0, the phase change for this also changes in the same way at points 0, 1, and 2 in FIG. A phase modulation of ±360°/N is applied to the signal. This modulation frequency is equal to the frequency of the counter 23. This phase modulation also includes a sensing operation to detect a phase shift after synthesis. When one of the two waves being combined causes a phase fluctuation due to fading or the like, this phase modulation component appears as an amplitude modulation component, is demodulated, and is fed back to the phase detector 24. While the phase is out of phase, the phase detector 24 controls the pulse control circuit 22, and if the phase of the RF output is delayed with respect to the other signal, the phase detector 24 controls the pulse control circuit 22.
By inserting an extra clock pulse during the up-count period, the number of up-counts is greater than the number of down-counts. In this way, the phase in the RF output is 1 as it moves back and forth on the circumference.
Advance in steps (e.g. 22.5°). That is, rotational phase rotation is performed while undergoing constant phase modulation, and the phase rotation stops when the phases of the two waves match. The operation is similar when the phase is leading. FIG. 5 is a block diagram of a phase control section according to another embodiment of the present invention. This embodiment uses a pulse control circuit 22 that controls the number of pulses in the embodiment of FIG.
Instead, a phase shift control circuit 103 using a pulse control circuit 32 that controls the width of the output of the dividing period 21 is used, and the counter 23 counts up and down the number of clock pulses input at a constant period. Therefore, when the phases of the two synthesized waves are equal, up-counting and down-counting are repeated at equal intervals as shown in FIG. Then, the pulse width control circuit 32 controls the output waveform of the frequency divider 21 to increase or decrease the up-count and down-count widths as shown in FIG. 6b or 6c, thereby increasing or decreasing the count of the counter 23. However, in this embodiment, for example, the count in FIG. 6b is "0→
1 → 2 → 3 → 2'' → 3 → 4..., so the response speed increases by 2 steps in one up-down period. Therefore, this embodiment has a faster response speed than the embodiment shown in FIG. It gets faster. The above embodiment has been explained using a balanced modulator as a phase shifter, but instead of this phase shifter,
47-29375, the configuration of the present application can also be applied to a phase shifter using a circulator and a variable attenuator. As described above, according to the present invention, by using one phase modulator, phase modulation for sensing and rotational phase shifting can be performed, and a large number of expensive modulators are not required. In addition, the points on the circumference are set digitally, providing the necessary precision, and since the phase shift is performed electronically, it is fast, highly reliable, and has low power consumption. It also has the advantage of being smaller. In addition, the loss of the phase shift circuit is larger than that of the conventional motor-based system, but
Nowadays, low-noise amplification can be easily performed, so placing this low-noise amplifier before the phase shift circuit eliminates the problem.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional phase synthesis diversity receiver, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 a, b, and c are input waveform diagrams of an up-down counter, and FIG. An explanatory diagram of the phase states corresponding to the output of the up-down counter, FIG. 5 is a block diagram of the phase control section of the second embodiment of the present invention, and FIG. 6 a, b, and c are the counter inputs of FIG. 5. FIG. In the figure, 1, 2... antenna, 3... phase shift control section, 4... hybrid, 5... amplitude detector, 6... phase modulator, 7... rotation phase shifter, 8...
...Composition output terminal, 10...RF input terminal, 11...
...RF output terminal, 12...AM input terminal, 20...
... Pulse generator, 21 ... Frequency divider, 22 ... Pulse control circuit, 23 ... Up-down counter, 2
4... Phase detector, 25, 26... Memory, 2
7, 28... D/A converter, 29, 30...
Balanced modulator, 31...90° hybrid, 32...
... Pulse control circuit, 101 ... Phase shift circuit, 10
2,103... Phase shift control circuit.

Claims (1)

[Claims] 1. A predetermined angle of 360°/N (where N is a natural number) corresponding to a predetermined digital control value for one of the signals received from two antennas installed at a predetermined interval. a phase shift circuit that performs a phase shift by an integral multiple of , and a signal synthesis circuit that synthesizes the output of the phase shift circuit and the output of the received signal that is not input to the phase shift circuit;
an amplitude detector that detects phase fluctuations in the output of the signal synthesis circuit as an amplitude fluctuation value; and a phase shift control circuit that forms the predetermined digital control value in accordance with the output of the amplitude detector; The circuit is
a frequency divider that takes a predetermined clock as an input and divides the frequency of the predetermined input clock to generate an up-down signal with the same up period and down period; and an output of the phase amplitude detector that is synchronized with the period of the up-down signal. a phase detector that detects the matching or mismatching of the phases of the respective signals received from the two antennas as a polarity; It is composed of a pulse control circuit that generates a control signal, and an N-ary up-down counter that counts up or down the count signal according to the up-down control signal and outputs the predetermined digital control value. A phase synthesis type space diversity receiving device, wherein the pulse control circuit controls counting of the up-down counter so that phase fluctuations are reduced. 2. Claims in which the pulse control circuit is configured to receive the predetermined clock as an input and form the count signal with a clock inserted within the up period or down period according to the output of the phase detector. 2. The phase-synthesizing space diversity receiving device according to claim 1. 3. The pulse control circuit receives the up-down signal as an input and forms the up-down control signal in which the interval between the up period and the down period is increased or decreased according to the output of the phase detector. The phase combining type space diversity receiving device as described in 2.