JPS6242547B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dual system transmission control circuit, and more specifically, a common control circuit including one microprocessor in a terminal that transmits data to a central control center via a transmission line. The invention relates to a duplex transmission control circuit that is installed in duplex between the common control unit and the transmission line to control data transmission between the common control unit and the transmission line, and in particular, This is intended to realize a duplex system using the same transmission control circuit by automatically selecting the transmission control circuit connected to the transmission line of the transmission control circuits.

As a conventional example, first, a transmission control circuit in a single system is shown in FIG. In Figure 1, 1 is a microprocessor (hereinafter referred to as MPU), 2 is a memory, and 3 is a direct memory access (hereinafter referred to as DMA).
4 is an advanced data link (hereinafter abbreviated as ADL) controller, 5 is a level conversion circuit, 6 is a receive data service request (hereinafter abbreviated as RDSR) signal, and 7 is a transmit data service request (hereinafter abbreviated as TDSR). Signal 8 is
A DMA request signal, 9 a DMA permission signal, 10 a data path, 11 an address bus, and 16 a transmission line. Upon receiving the reception start flag, the ADL controller 4 outputs an RDSR signal 6, which is a request signal for transferring data to the memory 2 using the DMA method, and sends it to the DMA controller 3. The DMA controller 3 accepts this RDSR signal 6 and
A DMA request signal 8 is output to the MPU 1 to obtain bus exclusive rights. When the MPU 1 receives this signal, it sets the data bus 10 and address bus 11 to high impedance and outputs a DMA permission signal 9, which is a signal for passing the bus to the DMA controller 3. The DMA controller 3 now becomes the master and starts DMA transfer to transfer data from the ADL controller 4 to the memory 2. When the data transfer is completed, the ADL controller 4 sends the RDSR signal 6
, and then the DMA controller 3 drops the DMA request signal 8. The bus exclusive right then returns from the DMA controller 3 to the MPU 1. The MPU 1, which has become the master, performs certain processing using the data in the memory 2 that has just been transferred, and activates the ADL controller 4 in order to respond to the host computer side. Activation from the MPU 1 to the ADL controller 4 is generally performed using the data bus 10 and address bus 11 by setting a specific bit in a control register (not shown) in the ADL controller 4. The activated ADL controller 4 sets the transfer mode display signal 13 (described later) to a low level in FIG.
Outputs TDSR signal 7 for transfer. In response to this signal, the DMA controller 3 sends a DMA request signal 8 to the MPU 1, and the MPU 1 returns a DMA permission signal 9. Then, the DMA controller 3 transfers the data from the memory 2 to the ADL controller 4, and sends the data to the transmission line 16 via the level conversion circuit 5.

If we consider the case where a single transmission control system as shown in Figure 1 is duplicated as a duplex transmission control circuit, (1) MPU 1 determines which of the two transmission control circuits is connected to the line. (2) It is necessary to activate the circuit connected to the line to transmit and receive, and (3) This causes problems such as the complexity of the program.

An object of the present invention is to solve the above problems, simplify the microprogram without distinguishing between single system and dual system, and use two identical transmission control cards to
An object of the present invention is to provide a duplex transmission control circuit that enables duplex transmission.

An embodiment of the present invention will be described below with reference to FIGS. 2 and 3. FIG. 2 is a circuit diagram, and FIG. 3 is a time chart of various signals for explaining its operation. Second
In Fig. 3, 12 indicates flag detection (hereinafter referred to as
(abbreviated as FD) signal, 13 is transfer mode display (hereinafter referred to as
(abbreviated as RST) signal, 14 is a flip-flop for flag detection, 15 is a gate, and the others are the same as in the case of FIG. Here, the flip-flop 14 is an edge trigger flip-flop with a set input, and the D input is grounded (GD).
When a signal is applied to the set input terminal S (signal line 1
2 is forcibly set to LOW level) (Q output “1”), and the T input (signal line 13) goes LOW→
It is designed to be reset (Q output "0") at HIGH. Note that the dual systems are distinguished by A and B. The circuit in Figure 2 differs from the circuit in Figure 1 in that the transmission control circuits are duplicated, and each transmission control circuit has one flip-flop and two gates.
This means that more than 100 people have been added. Hereinafter, the differences will be explained with reference to the time chart in FIG. 3, focusing on the differences. FIG. 3A shows the operation of the A-system circuit, and B shows the operation of the B-system circuit.

In data transmission using the polling selection method, a terminal starts a series of transfers with reception and ends with transmission. In the dual system shown in FIG. 2, it is assumed that the transmission line 16 is now connected to system A.

When the ADL controller 4A receives the reception start flag, it sends out an RDSR signal 6A and an FD signal 12A. This FD signal 12A brings the flip-flop 14A into a set state. In other words, this indicates that the line is connected to the A-system circuit. Therefore DMA
The request signal 8 is output only from the A-system circuit, and the DMA
The permission signal 9 is also input only to the A-system circuit, and DMA is executed in the same way as in the circuit of FIG.

Next, a case will be described in which memory data is sent to the transmission line 16 via the ADL controller 4A by DMA transfer. The MPU 1 uses the same addressing to transmit data to the transmission line 16.
Activates both transmission control circuits in the system. ADL controllers 4A, 4B are TDSR signals 7A, 7B and
Outputs RTS signals 13A and 13B. here,
A-system circuit uses flip-flop 14A to perform DMA
Since the gate of request signal 8A is enabled, it is sent onto the bus. However, in the B-system circuit, flip-flop 14B is not in the set state, so
DMA request signal 8B is not sent onto the bus.
When the DMA permission signal 9 is returned from the MPU 1, it is similarly input only to the A system. Therefore, only the A-system circuit
Perform DMA transfer. When the transfer is completed, the ADL controller 4A drops the TDSR signal 7A,
The DMA controller 3A drops the DMA request signal 8A, and the MPU 1 recovers the exclusive right to the bus. MPU1
The ADL controllers 4A and 4B use the same addressing to switch the transmit mode to the receive mode.
is set to receive mode and RTS signals 13A and 13B are set to high level. Therefore, flip-flop 14
A and 14B are reset to close the gates of the DMA request signal 8 and DMA grant signal 9. In this case, in the B-system circuit, the flip-flop 14B is in the reset state, so the gates 15-1B and 15-2 are in the reset state.
B remains closed. Therefore, the A-system circuit and the B-system circuit become ready for reception.

In the above explanation, the case where the transmission line 16 is connected to the A-system circuit has been described, but the operation is exactly the same when it is connected to the B-system circuit, only that the A-system circuit and the B-system circuit are interchanged. Regarding which of the A-system circuit and the B-system circuit should be connected to the transmission line, if both are normal, the A-system circuit is connected, and if the A-system circuit is abnormal, the B-system circuit is connected. Although it is possible to switch the switch automatically, an embodiment in which the switch is switched manually is shown here.

As explained above, according to the present invention, by preparing two cards having the same transmission control circuit, it is possible to easily convert a single system into a dual system by simply adding cards. , and the program is
Activation can be performed using the same addressing without distinguishing whether the system is a single system or a dual system.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the conventional transmission control circuit including a microprocessor using a single system, FIG. 2 is a diagram of an embodiment of the present invention, and FIG.
This is an operation time chart of the B-system circuit. 1...Microprocessor, 2...Memory, 3...
DMA controller, 4...ADL controller, 5
...Level conversion circuit, 6...RDSR signal, 7...TDSR
signal, 8...DMA request signal, 9...DMA permission signal,
10...Data bus, 11...Address bus, 12...
Flag detection signal, 13...transfer mode display signal,
14...Flip-flop, 15...Gate, 16...
transmission line.

Claims (1)

[Claims] 1. A duplex system that is installed in duplex form between the transmission line and a common control unit including one microprocessor in a terminal that transmits data to the central control center via the transmission line to control data transmission. In the transmission control circuit, one of the transmission control circuits forming the duplex transmission control circuit is connected to the transmission line via a changeover switch, and each transmission control circuit is connected to the transmission line via a changeover switch, and each transmission control circuit is connected to the transmission line through a changeover switch, and each transmission control circuit is connected to the transmission line through a changeover switch. The flip-flop is placed in the set state by the start flag and is reset upon completion of the transmission operation to the transmission line, and the flip-flop is set and reset to enable and disable transmission and reception of transmission control signals with the common control unit. A dual system transmission control circuit characterized by having a gate circuit that performs the following operations.