JPS6242548A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6242548A
JPS6242548A JP60182268A JP18226885A JPS6242548A JP S6242548 A JPS6242548 A JP S6242548A JP 60182268 A JP60182268 A JP 60182268A JP 18226885 A JP18226885 A JP 18226885A JP S6242548 A JPS6242548 A JP S6242548A
Authority
JP
Japan
Prior art keywords
pinch
notch
bases
bars
broken
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60182268A
Other languages
Japanese (ja)
Inventor
Yoshiaki Sano
義昭 佐野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60182268A priority Critical patent/JPS6242548A/en
Publication of JPS6242548A publication Critical patent/JPS6242548A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To increase isolation voltage by forming a notch section to a molding resin and breaking a pinch bar along the inner wall section of the notch section. CONSTITUTION:Notch sections 17 are shaped to a molding resin 11 in the upper section of a pinch bar 14a on the side to be broken so that the molding resin is exposed in some length. Such notch sections 17 are limited by inner wall surfaces 18 on the side reverse to end surfaces, bases 19 just under the exposed pinch bars 14a and side wall surfaces 20 vertical to the bases, and the bases 19 run parallel with a mounting surface such as the surface of a radiator plate 21. The longitudinal length of the bars 14a for the bases 19 is made wider than the width of the bars 14a. On the other hand, V grooves are cut to sections to be broken in the bars 14a and break lines 16 are shaped previously. A creeping distance (d) up to the surface of the radiator plate 21 from the broken-out section of the bar 14a is h+b obtained by adding the longitudinal length (b) of the base 19 to height (h) from the surface of the radiator plate of the bar 14a, thus increasing isolation voltage.

Description

【発明の詳細な説明】 〔概要〕 ピンチバー破断部が樹脂端面より内側に位置する如く形
成されたモールド型半導体装置である。DETAILED DESCRIPTION OF THE INVENTION [Summary] This is a molded semiconductor device formed such that a pinch bar fracture portion is located inside a resin end surface.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置に関するもので、さらに詳しく言え
ば、絶縁耐圧を高めるためピンチバーの破断部がモール
ド樹脂の端面から内側に引込んだ部分に位置するモール
ド成型された半導体パッケージに関するものである。The present invention relates to a semiconductor device, and more specifically, to a molded semiconductor package in which the fractured portion of the pinch bar is located at a portion recessed inward from the end surface of the mold resin in order to increase dielectric strength.

〔従来の技術〕[Conventional technology]

第４図の側断面図に示されるモールド型半導体装置（半
導体パンケージともいう）は知られたものであり、同図
において、１１はモールド樹脂、１２は半導体チップ（
以下単にチップという）、１３はリード、１４はピンチ
バー、１５はリード１３とチップのパッド（電極）とを
接続するワイヤを示す。The molded semiconductor device (also referred to as a semiconductor pancage) shown in the side cross-sectional view of FIG. 4 is a known one.
13 is a lead, 14 is a pinch bar, and 15 is a wire connecting the lead 13 and a pad (electrode) of the chip.

第４図のパッケージは第５図の平面図に示されるリード
フレームを樹脂封止することによって形成され、図にお
いて、１５はチップ１２が接着されるダイステージを示
し、同図において、右のピンチバー１４ａは左のピンチ
バー１４ｂと共にダイステージを支持する部材であるが
、右のピンチパー１４ａはモールド成型後破断線１６に
沿って破断され、チップ１２にトランジスタが形成され
ている場合、リード１３ａはベース電極、リード１３ｂ
はエミッタ電極にワイヤ１５によって接続され、ピンチ
パー１４ｂはコレクタに接続された状態にあり、リード
とピンチパーはそれぞれ外部回路に接続される。The package shown in FIG. 4 is formed by resin-sealing the lead frame shown in the plan view of FIG. 14a is a member that supports the die stage together with the left pinch bar 14b, but the right pinch bar 14a is broken along the break line 16 after molding, and when a transistor is formed on the chip 12, the lead 13a is a base electrode. , lead 13b
is connected to the emitter electrode by a wire 15, the pinch pin 14b is connected to the collector, and the lead and the pinch pin are each connected to an external circuit.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前記したピンチパー１４ｂはモールド樹脂１１の端面に
おいて切断されているが、トランジスタの場合、チップ
付けしたダイステージ（基板）とピンチパーとが一体化
されているので、半導体装置をテレビとかラジオの如き
セット本体に組み込んだ場合、セット本体と逆電位とな
りショートすることがある。そこで第６図に示される如
くセット本体の放熱板２１の壁２２からｔの距離をとる
かまたはなんらかの方法で絶縁処理をしなければならな
い。The pincher 14b described above is cut at the end face of the molded resin 11, but in the case of transistors, the die stage (substrate) on which the chip is attached and the pincher are integrated, so the semiconductor device can be attached to a set body such as a television or radio. If it is installed in a set, the potential will be opposite to that of the set itself, which may cause a short circuit. Therefore, as shown in FIG. 6, it is necessary to maintain a distance t from the wall 22 of the heat sink 21 of the set main body, or to insulate it by some method.

一般に１ｆｌの距離で１００ＯＶ程度の耐圧がとれるの
であるが、更に高い電圧（２０００Ｖ〜３０００Ｖ　’
）を要求される場合距離ｔを大きくとれば、耐圧は向上
するがパッケージの規格化、セットの小型化等から実施
できない状況にあり放熱板との間に放電が発生ずること
があった。それ故に、モールド型パッケージの組み込み
に十分注意しなければならないし、パンケージを壁２２
に接して組み込まなければならない場合には特別の絶縁
処理をなす必要がある。Generally, a withstand voltage of about 100OV can be obtained at a distance of 1fl, but even higher voltages (2000V to 3000V'
) If distance t is required, the withstand voltage will be improved by increasing the distance t, but this is not possible due to package standardization, set miniaturization, etc., and discharge may occur between the heat sink and the heat sink. Therefore, great care must be taken in assembling the molded package, and the pancage must be mounted on the wall 22.
If it must be installed in contact with

本発明はこのような点に鑑みて創作されたもので、絶縁
耐圧に優れた例えばセット本体に接した状態で組み込ん
だときに放電などの発生することのないモールド型パッ
ケージを提供することを目的とする。The present invention was created in view of these points, and an object of the present invention is to provide a molded package that has excellent dielectric strength and does not cause discharge when it is assembled in contact with a set body, for example. shall be.

〔問題点を解決するための手段〕[Means for solving problems]

第１図と第２図は本発明実施例の断面図と斜視図である
。1 and 2 are a sectional view and a perspective view of an embodiment of the present invention.

第１図と第２図において、モールド樹脂１１には外部回
路に接続されることなく切断されるピンチパー１４ａが
、その幅の２〜５倍の長さ露出するように切欠部１７が
形成され、切欠部の内壁面１８に沿ってピンチパーが切
断され、かつ切欠部１７の底面１９は取付は面（例えば
放熱板）と対向面とすることにより沿面距離を長くとる
。In FIGS. 1 and 2, a notch 17 is formed in the molded resin 11 so that a length of 2 to 5 times the width of the pinch par 14a, which is to be cut without being connected to an external circuit, is exposed. The pincher is cut along the inner wall surface 18 of the notch, and the bottom surface 19 of the notch 17 is mounted opposite a surface (for example, a heat sink) to increase the creepage distance.

〔作用〕[Effect]

本発明実施例においては、切欠部が設けられその内壁面
１８に沿ってピンチパーが破断されるので破断面から放
熱板までの距離（ｄ）は、放熱板から切欠部底面までの
高さくｈ）に底面のピンチパーの長さ方向の距％３ｔｉ
　（ｂ）を加えた長さくｔ＋ｈ）となり、対放熱板の関
係で沿面距離はｂだけ増加し、またセット本体の壁面２
２に対する関係ではｂの距離が破断面と壁面との間に存
在するので、その分だけ絶縁耐圧が高められるものであ
る。In the embodiment of the present invention, a notch is provided and the pinch par is broken along its inner wall surface 18, so the distance (d) from the broken surface to the heat sink is equal to the height h) from the heat sink to the bottom of the notch. The lengthwise distance of the bottom pinch par is %3ti
(b) is added to the length t + h), and the creepage distance increases by b due to the heat sink, and the wall surface of the set body 2
In the relationship with respect to 2, since a distance b exists between the fracture surface and the wall surface, the dielectric strength voltage is increased by that amount.

〔実施例〕〔Example〕

以下、図面を参照して本発明実施例を詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.

従来例のモールド樹脂１１は、リードフレームの平面の
第４図に見て上下対称台形部分が合体した形状に形成さ
れていたのに対し、本発明実施例においては、破断され
る方のピンチパー１４ａの上方のモールド樹脂にそれが
ある長さ露出するように切欠部１７が形成される。かか
る切欠部１７は、樹脂封止用のモールド金型の上型に切
欠部１７に対応する突出部を設けることによって形成さ
れる。かかる切欠部】７は、端面とは反対側の内壁面１
８と、露出したピンチパー１４ａの直下の底面１９と、
底面に垂直な側壁面２０とによって限定され、底面１９
は取付は面（例えば放熱板２１の面）に平行になる（対
向面となる）。もっとも側壁面２０は無くとも効果は出
る。底面１９のピンチパーの長手方向の長さは、ピンチ
パーの幅の２〜５倍に設定する。The mold resin 11 of the conventional example was formed in a shape in which upper and lower symmetrical trapezoidal parts were combined when viewed from the plane of the lead frame in FIG. A notch 17 is formed in the mold resin above the mold resin so that a certain length thereof is exposed. The notch 17 is formed by providing a protrusion corresponding to the notch 17 on the upper die of a mold for resin sealing. Such a notch] 7 is the inner wall surface 1 on the opposite side from the end surface.
8, and the bottom surface 19 directly below the exposed pinch par 14a,
The bottom surface 19 is defined by a side wall surface 20 perpendicular to the bottom surface.
The mounting is parallel to the surface (for example, the surface of the heat sink 21) (the surface is opposite to the surface). However, the effect can be obtained even without the side wall surface 20. The length of the pinch par on the bottom surface 19 in the longitudinal direction is set to be 2 to 5 times the width of the pinch par.

他方、ピンチパー１４ａには、破断すべき部分に■溝を
切って破断線１６を形成しておく。このＶ溝は、リード
フレームをプレス加工によって形成するときプレスによ
って形成する。従来の技術によってピンチパー１４ａを
強く引っ張ると、ピンチパー１４８は■溝（破断線１６
）に沿って破断される（第２図）。On the other hand, in the pinch parser 14a, a break line 16 is formed by cutting a groove in the part to be broken. This V-groove is formed by pressing when forming the lead frame by pressing. When the pinch parr 14a is strongly pulled using the conventional technique, the pinch parr 148 forms a groove (broken line 16).
) (Fig. 2).

第１図を参照すると、ピンチパー１４ａの破断面から取
付は面である放熱Ｆｉ２１の表面までの沿面距離（ｄ）
は、ピンチパー１４ａの放熱板表面からの高さくｈ）に
、底面１９の長手方向の長さくｂ）を加えた長さくｈ＋
ｂ）であるので、第６図に示した従来例の沿面距離がｈ
であったのに比べ長さｂの分だけ絶縁耐圧が高くなる。Referring to FIG. 1, the creepage distance (d) from the fracture surface of the pinch parser 14a to the surface of the heat radiation Fi 21, which is mounted on a surface.
is the length h+ which is the sum of the height h) of the pinch par 14a from the heat sink surface and the length b) in the longitudinal direction of the bottom surface 19.
b), so the creepage distance of the conventional example shown in Fig. 6 is h.
The dielectric strength is increased by the length b.

また、第１図のパッケージが取付は部材の壁２２の図に
符号２２ａを付し破線で示す壁面に接して取り付けられ
る場合、従来例では沿面距離はほとんどＯに近いもので
あったのに対し、第１図の実施例ではｂの沿面距離がと
られているから、壁面に対する関係での絶縁耐圧は大幅
に向上される。Furthermore, when the package shown in Fig. 1 is mounted in contact with the wall surface of the member wall 22 indicated by the reference numeral 22a and the dashed line, the creepage distance is almost O in the conventional example. In the embodiment shown in FIG. 1, the creepage distance b is taken, so that the dielectric strength with respect to the wall surface is greatly improved.

第２図には第５図に示されたピンチパー１４ａが２本あ
るリードフレームのために切欠部１７が２つ設けられた
実施例を示したが、ピンチパー１４ａが１本の場合には
第３図に示す如く切欠部１７は１つだけ設ける。FIG. 2 shows an embodiment in which two notches 17 are provided for the lead frame with two pinch pars 14a shown in FIG. As shown in the figure, only one notch 17 is provided.

なお、以上はトランジスタを例に参照したが、本発明の
通用範囲はその場合に限定されるものでなく、サイリス
ク、さらにはリード１３が多数形成されたＩＣパフケー
ジの場合にも及ぶものである。Although the above example refers to a transistor, the scope of the present invention is not limited to that case, but also extends to the case of an IC puff cage in which a large number of leads 13 are formed.

また、側壁面２０が無くても、同一効果を発揮できる。Furthermore, the same effect can be achieved even without the side wall surface 20.

〔発明の効果〕〔Effect of the invention〕

以上述べてきたように本発明によれば、チップが接着さ
れたダイステージを含むリードフレームをモールド成型
して形成される半導体装置（パッケージ）において、ピ
ンチパーの破断面がモールド樹脂の端面の内部に位置す
るため、半導体装置をセット本体に取り付けた場合の絶
縁耐圧が向上し、パッケージの応用範囲が拡げられる効
果がある。As described above, according to the present invention, in a semiconductor device (package) formed by molding a lead frame including a die stage to which a chip is bonded, the fracture surface of the pinch par is inside the end surface of the mold resin. This has the effect of improving the dielectric strength when the semiconductor device is attached to the set body, and expanding the range of applications of the package.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明実施例の断面図、 第２図と第３図は本発明実施例の斜視図、第４図は従来
例の断面図、 第５図は従来例の平面図、 第６図は従来例の取付けを示す断面図である・第１図な
いし第６図において、 １１はモールド樹脂、 １２は半導体チップ、 １３、　１３ａ、　　１３ｂはリード、１４、１４ａ、
　１４ｂはピンチパー、１５はダイステージ、 １６は破断線、 １７は切欠部、 １８は内壁面、 １９は底面、 ２０は側壁面、 ２１は放熱板、 ２２は壁である。 冬発Ｔ３１４喫炙Ｉ°」鵬■ 第１図 本発朗資砲ψ１制匁函 第２図 ８発＠史党卆癩氏 第３図 玖９１欽面図 慎　７１図 第５図FIG. 1 is a cross-sectional view of an embodiment of the present invention, FIGS. 2 and 3 are perspective views of an embodiment of the present invention, FIG. 4 is a cross-sectional view of a conventional example, FIG. 5 is a plan view of a conventional example, and FIG. The figure is a sectional view showing a conventional installation. In Figures 1 to 6, 11 is a mold resin, 12 is a semiconductor chip, 13, 13a, 13b are leads, 14, 14a,
14b is a pinch par, 15 is a die stage, 16 is a breaking line, 17 is a notch, 18 is an inner wall surface, 19 is a bottom surface, 20 is a side wall surface, 21 is a heat sink, and 22 is a wall. Winter-departed T314 burnt I°'' Peng■ Figure 1 Book-launched gun ψ1 scale Momme box Figure 2 8-shot @ Shi Party Manhuan Figure 3 Ku91 Qinmian Zushin 71 Figure 5

Claims (1)

【特許請求の範囲】 半導体チップ（１２）が接着されピンチバー（１４）に
より支持されたダイステージ（１５）を含むリードフレ
ームを樹脂封止してなる半導体装置において、 破断されるべきピンチバー（１４ａ）の位置する上方部
分のモールド樹脂にはピンチバー（１４ａ）の長手方向
にピンチバーの幅より広い幅の切欠部（１７）が形成さ
れ、 ピンチバー（１４ａ）は切欠部のモールド樹脂端面から
最も遠い内壁面（１８）に沿って破断されていることを
特徴とする半導体装置。[Claims] In a semiconductor device formed by resin-sealing a lead frame including a die stage (15) to which a semiconductor chip (12) is adhered and supported by a pinch bar (14), a pinch bar (14a) to be broken is provided. A notch (17) wider than the width of the pinch bar is formed in the upper part of the mold resin where the pinch bar (14a) is located in the longitudinal direction, and the pinch bar (14a) is located on the inner wall surface furthest from the mold resin end surface of the notch. (18) A semiconductor device characterized by being fractured along the line (18).
JP60182268A 1985-08-20 1985-08-20 Semiconductor device Pending JPS6242548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60182268A JPS6242548A (en) 1985-08-20 1985-08-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60182268A JPS6242548A (en) 1985-08-20 1985-08-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6242548A true JPS6242548A (en) 1987-02-24

Family

ID=16115284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60182268A Pending JPS6242548A (en) 1985-08-20 1985-08-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6242548A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6453426A (en) * 1987-05-11 1989-03-01 Sanken Electric Co Ltd Manufacture of resin sealed semiconductor device
US4855807A (en) * 1986-12-26 1989-08-08 Kabushiki Kaisha Toshiba Semiconductor device
GB2451189A (en) * 2007-07-18 2009-01-21 Deepstream Technologies Ltd An electrical circuit that contains apertures that allow supporting tie bars to be cut

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855807A (en) * 1986-12-26 1989-08-08 Kabushiki Kaisha Toshiba Semiconductor device
JPS6453426A (en) * 1987-05-11 1989-03-01 Sanken Electric Co Ltd Manufacture of resin sealed semiconductor device
GB2451189A (en) * 2007-07-18 2009-01-21 Deepstream Technologies Ltd An electrical circuit that contains apertures that allow supporting tie bars to be cut

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