JPS6242567A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To obtain an FET with excellent high frequency characteristics by a method wherein an N-type layer is provided in an Si substrate and ions are implanted through an insulating layer to form the second N-type layer and a recessed part which reaches the first N-type layer through the second N-type layer is formed and a gate electrode is provided in that recessed part. CONSTITUTION:An SiO2 film 13 is formed on the surface of a GaAs substrate 11 in which an N-type layer 12 is provided. An element isolation region is covered with a photoresist 14 and an N<+> type layer 15, shallower than the N-type layer 12, is formed by implantation of Si ions. After annealing, a source electrode 16 and a drain electrode 17 are formed and a recessed part, which pierces through the N<+> type layer 15, is formed at the gate part and a gate electrode 18 is formed in it. With this constitution, an FET with reduced parasitic resistance of a source, a small gate capacitance and excellent high frequency characteristics can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing field effect transistors used in the microwave band.

2. Description of the Related Art GaAs'/Jotsky gate field effect transistors (hereinafter abbreviated as GaAsFETs) are capable of high-speed operation and are widely applied as microwave band devices.

FIG. 2 shows an example of a FET manufactured using 81 ion implantation. In the figure, 21 is an n-type active layer, 22 is a semi-insulating GaAs substrate, and 23 is an n+ layer, which are a source region and a drain region, respectively. 24 is a source electrode, 2
5 is a drain electrode, and 26 is a gate electrode. where n
The shaped active layer 21 is desirably designed to have a steep profile and to be relatively thin.

Problems to be Solved by the Invention In the FET shown in FIG. 2, the impurity concentration of the active layer 21 between the source electrode 24 and the gate electrode 26 is low and the thickness is thin, so the sheet resistance is high and this causes source parasitic This acts as a resistance and significantly reduces the mutual conductance gm of the FET. For this reason, FET using ion implantation
Therefore, it has been difficult to manufacture a low-noise FET with excellent characteristics.

The present invention has been made in view of the above problems, and provides a method for reducing the sheet resistance of the active layer without impairing the steepness of the impurity profile of the n-type active layer.

Means for Solving the Problems In order to solve the above problems, the field effect transistor of the present invention includes a step of forming an insulating film on a semiconductor layer of one conductivity type, and a step of forming an insulating film on the insulating film. a step of ion-implanting a conductivity type impurity to a depth reaching the semiconductor layer to form a high concentration; a step of forming a recess with a depth penetrating the high concentration layer in a part of the high concentration layer; The method also includes a step of forming a gate electrode at the bottom of the recess.

Function: With this configuration, the impurity concentration on the surface of the active layer is increased, and as a result, a good FET with reduced sheet resistance and low source parasitic resistance can be obtained.

Embodiment FIG. 1 is a diagram showing an embodiment of the present invention.
It shows the manufacturing process of T.

A 3102 film 13 is formed on the surface of the GaAs substrate 110 on which the n-type layer 12 is formed as shown in FIG. 1a (FIG. 1b).

Thereafter, after covering the element isolation region with a photoresist 14, a high concentration of Sl is ion-implanted, and the Sl is injected into the GaAg through the Sio2 film to form an n+ layer 16 (FIG. 1C). At this time, by appropriately setting the Si ion acceleration voltage, the thickness of the n layer can be made thinner than the n layer. In the present invention, since the n-layer is formed by implantation through the SiO2 film, there is no need to lower the accelerating voltage extremely, and the thickness of the n-layer can easily be made thinner than the n-layer. Thereafter, a heat treatment for activating the implanted impurities is performed to form source and drain electrodes 1e and 1a. Next, a recess penetrating the n-layer is provided in the gate portion, and then a gate electrode 18 is formed (FIG. 1d).

As is clear from the above embodiments, according to the method for manufacturing a field effect transistor of the present invention, n#
1975, the source parasitic resistance can be reduced, and since the gate electrode is formed in a recess penetrating the n-layer, the gate capacitance is small, and a good FET is formed.

In this example, an S102 film was used as the insulating film, but the insulating film is not limited to this, and a 513N4 film or a PS film may also be used.
A G film or the like may also be used.

Effects of the Invention As described above, the present invention includes forming a second layer of one conductivity type by ion-implanting impurities of the same conductivity type into a semiconductor substrate having a first layer of one conductivity type through an insulating film, and then forming a second layer of one conductivity type. By providing a recess that penetrates the second one-conductivity type layer and reaching the first one-conductivity type layer, and forming a gate electrode in the recess, it has excellent high-frequency characteristics with low parasitic resistance and gate capacitance. Field effect transistors can be manufactured, and their practical effects are impressive.

[Brief explanation of drawings]

FIG. 1 is a process cross-sectional view showing a method for manufacturing a field effect transistor according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing an example of an FET manufactured using a conventional manufacturing method. 12...n type layer, 13...5IO2 film, 15...curved n layer, 1e...source, 17...river/drain, 18...gate .

Claims (1)

[Claims] a step of forming an insulating film on a semiconductor layer of one conductivity type; and a step of ion-implanting impurities of the one conductivity type from above the insulating film to a depth reaching the semiconductor layer to form a highly concentrated layer. , manufacturing a field effect transistor, comprising the steps of: forming a recess with a depth penetrating the high concentration layer in a part of the high concentration layer; and forming a gate electrode at the bottom of the recess. Method.