JPS6246352A - Microprocessor operation analysis method and device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method and apparatus for analyzing the operation of a microprocessor. More specifically, it relates to an emulator for debugging microprocessors. In particular, the present invention relates to an emulator used for debugging the hardware and software of a microprocessor that performs a brief fetch operation.

[Prior art], 11...1°? −107°t ′V”i: *G H@L b Gf
6” K 9 f, 10 Brosetuna hardware and software TTL debugging.
An emulator is used to
1.1 This emulator has an address bus connected to the microprocessor under test to be debugged.

Signals from a data bus and a control bus (hereinafter referred to as bus) are stored in a storage device in the main body of the emulator, and the stored contents are displayed for operation analysis.

, :(Dt<l(.,, 211 II O, IU. A. Yatsuga 5A; 1□-Input the program to the microprocessor under test. :1' The signal to read or write from the attached memory is transmitted. The signals are sequentially fetched into the emulator and analyzed according to the order in which the signals are transmitted. , 1 However, if the microprocessor under test performs prefetch operation,
A read cycle of the next instruction is inserted between the read of an instruction by the microprocessor under test and the memory read or write cycle caused by executing that instruction.

Furthermore, if the addresses read by the instruction are not consecutive,
Because of the brief fetch operation (instructions that do not need to be executed are also read, this is also carried on the bus and sent to the main body of the emulator).

Here, a briftetch operation refers to a microprocessor not performing a series of operations, such as reading or writing a memory resulting from reading an instruction and then executing that instruction. This refers to performing the operation of reading the next instruction in parallel while the instruction is being executed.

Therefore, the briefetch operation increases processing speed. In particular, many 16-bit microprocessors are capable of performing briefetch operations.

[Problems to be solved by the invention] Microbuf Of? that performs such a briefetch operation +, □8□□7, Yu93. Yo, R1'? = (7)Hm
I-&・□”・The conventional method of displaying the state of the bus in the order in which it is transmitted on the bus because the read of the next instruction occurs between the memory read or write caused by the execution of that instruction. In emulators, it is difficult to understand the interrelationship between reading an instruction and reading or writing to memory caused by the execution of that instruction.

Furthermore, if the addresses to be read by the instructions are not consecutive, instructions that do not need to be executed due to the brief fetch operation will also be read, and this will also be sent to the main body of the emulator on the bus j. Can it be done?
Since the main unit 1 collects and displays data including unnecessary data ' and 1', it is difficult to perform a rough analysis of the operation.

[Means for Solving the Problems] The present invention has been made to solve these problems, and even when the microprocessor under test performs a brief fetch operation, the memory generated by reading and executing instructions is By changing the order, the reading of the next instruction entered between the reading or writing of the instruction comes after the reading or writing of the memory caused by the reading and execution of the instruction.

Also, if the addresses read by the instruction are not consecutive,
Prevents reading of instructions that do not need to be executed from being sent to the main body of the emulator. In order to achieve this, signals on a bus are written into and read out from a memory circuit having two addresses using control signals.

[Operation] As a result, information is sent to the main body of the emulator in the order of instructions, and instructions that do not need to be executed are not sent. Therefore, only the necessary information is sent to the main body of the emulator in the order of instructions. This enables quick and accurate operation analysis.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention, and will be explained using this diagram.

In FIG. 1, reference numeral 5 denotes a microprocessor under test which is a measurement target included in the system under test, and 6I: reads and writes instructions to be executed and data resulting from execution upon access by the microprocessor under test 5. This is the memory for.

11 is connected to the microprocessor 5 to be measured.
゛□An input circuit for extracting access signals and data signals (hereinafter referred to as bus contents) of the address bus, data bus, and control bus (hereinafter referred to as buses); When reading from the memory 6, it is important to know whether the reading is reading an instruction (this is called a program reference), and whether the data generated as a result of executing that instruction is being read from the memory 6 or transferred to the memory 6. Write (this,
Pro ・, 1 graph 6° 7 y Ii>2 (D case 1 graph 6° 7 y).

A program/reference separation circuit 13 is used to output the access signal P, and 13 is an operation code that detects the first word (opcode) of an instruction executed by the microprocessor 5, such as an instruction consisting of three words, and outputs whether or not it has been detected. Detection circuit 14 is used when the microprocessor 5 reads an instruction from the memory 6 (program reference)
, a continuity detection circuit that detects whether the address containing the instruction is consecutive to the address containing the previously read instruction upon receiving the program reference signal P; 15A is a program reference separation circuit; When the program reference signal P from 12 is output,
Of the contents of the bus output from the input circuit 11, the opcode and operand (from the second word of the instruction) are written to one address, and if the program reference signal P is not output, the data signal is written to the other address. Memory circuit with two addresses for writing and storing, 18A is program reference signal @P and opcode detection circuit 1
A memory control circuit 19 receives the outputs of 11 to 14.3 and the output of the continuity detection circuit 14 and outputs the write address WA and read address RA of the memory circuit 15A. T5A, 1
Book containing 8A 1□)'', 1' Emulator characterizing the motion analysis device according to the invention
]i::' -ta unit part. 20 is the micro to be measured
``In order to trace the operating state of the processor 5, the secondary storage circuit 1 .
To display the contents of the bus sent from 17
11. Therefore, one built-in memory is used instead of the memory 6 for monitoring. □□□I,%'e')6(Dr'
M (DI) Emulator main body with a display section for correcting I meter bugs (Reference materials: For example, Iwatsu Technical Report 1.
Personal Emulator 5L-4802, Publisher: Iwasaki Tsushinki Co., Ltd., June 30, 1980, Vo
l, 23, No. 1.11-19),
[Integrated with 1 emulator unit section 19]
[i□14° constitutes a motion analysis device.
[1. (,; [11. Here, an example of the internal configuration of the memory 6 is shown in FIG.
(II). Each instruction has, for example, l>13 words,
．． The first word is opa・□.

[;, i 6°-1・2aci-ff3'7-Fill ", t
< 7 ”, / t' t h
f,). Many types of instructions (...M-
1, M, 1M+1...) and each operand are stored at successive addresses in the memory 6 in the order shown.

FIG. 2 shows an example where the microprocessor 5 under test performs a brief fetch operation and the instructions are consecutive. When a read instruction is read from the memory 6 and executed, the microprocessor 5 connected to the It shows how the contents of the bus are sent from the emulator unit section 19 to the emulator body section 20.

In FIG. 2(a), the input to the memory circuit 15A is for a period T1 because the contents of the bus to which the microprocessor under test 5 is connected are directly sent via the input circuit 11.
The first word (opcode) of instruction 1 is “
'A brief fetch operation is performed between the obe code of instruction 1 and the "operand of instruction 1" which is the second word (operand) of instruction 1 shown in period T3.
“Memo from previous instruction” which is data read from memory 6 (or data written to memory 6) that occurred due to execution of an instruction read earlier
1gel-su-read'' is inserted in period T2.
In general, during period T5, a memory read by instruction 1, which occurs after executing instruction 1, is on the bus connected to microprocessor 5 under test.
;, 1°, in period T4, before the instruction 1
The read state of the opcode of instruction 2 to be executed next )ゝ;・1″.

Ru.
,,, ;The memory circuit 15A shown in FIG. 2(a)
No.8 ``“□also＼ If the power is, the emulator book will be in the same order.
□′i:1′(,II If sent to the body 20 and displayed, they are
;Due to the 2° briefetch operation, the instructions are not in the correct order, making it difficult to analyze the operation. , 'Here, Figure 2 (a
), rearrange the instructions according to the order of the instructions, and then install the micro-meter to be measured □.

Figures 2(b) to 2(b) show how the contents of the bus connected to the processor 5 are transferred to the emulator main unit 20.
.

This will be explained using (h).

During period T1, the bus to which the microprocessor under test 5 is connected is in a state where the "opcode of instruction 1" is read out, and the opcode of instruction 1 is read out from the input circuit 11.
The signal is sent to a storage circuit 15A, a program/reference separation circuit 12, an operation code detection circuit 13, and a continuity detection circuit 14 through the memory circuit 15A.

The program reference separation circuit 12 detects an opcode or operand and outputs a program reference signal "P" (Fig. 2 (b)), or detects a memory read by an instruction and determines that it is a data reference. does not output the program reference signal ``P'' (indicated by D in FIG. 2(b)), but during the period T1
is in the program reference state since it is in the state of reading the "opcode of instruction 1", and outputs the program reference signal "P" as shown in (b). As a result, the "operation code of instruction 1" is written into the memory port (path 15Ak-) in place of the "operation code of the previous instruction" which has already been written and is the content of the memory circuit 15A.
When the 1lil opcode detection circuit 13 detects the opcode, its output becomes "'H" (level),
When no opcode is detected, the output becomes "L" (level). During period T1, the output of the operation code detection circuit 13 becomes "H" (FIG. 2(C)).

Continuous detection 0 path 116 years 0 people ° 1 address 0 continuity
In the circuit that examines ill, the memory containing the instruction in the presence of 10g° reference signal, 1 "P"-i':.

When the addresses in 6 (see Figure 5) are consecutive
1;, : outputs a "continuous"signal; when discontinuous, it outputs a "discrete" signal.

Continuous” signal output and data reference (instruction)
1・:il：Rei 8 fruit”″′Rui 1st grade Ut;:9-1(7)%f! J6′
”) (7) Ill read or memory 6
i″′l=,′:
5. Don't force yourself. Therefore, in period T1, period T
l.

The period before instruction 1 is the operand of the instruction before instruction 1.
Since there is □ (not shown), the instruction 1 o :,, [) □ ped 1- is continuous (see Figure 5).
1. I: As shown in (d), the output of the detection circuit 14 is "continuous 9m +,:.

becomes.

When the program reference signal "P" is being output, the memory control circuit 18A changes the write address and read address to the memory circuit 15A from the state in which "P" was previously output.As a result, the period before T1 The two addresses are exchanged, the write address becomes address 0, and the read address becomes address 1 (FIG. 2(e)).
The input of A is written to address 0 (Fig. 2 (f)), and the "operand of the previous instruction" stored at address 1 (Fig. 2 (f)) is written to address 0 (Fig. 2 (f)).
g)) is read out and becomes the output of the memory circuit 15A (second
Figure (h)).

Similarly, during period T2, the data reference is detected from the program/reference separation circuit 12, so the program reference signal "P" is not output ("D" and "D" are not output in FIG. 2(b)). ), the output of the opcode detection circuit 13 is L'. Since it is not a program reference, there is no output from the continuity detection circuit 14. Since the data reference has been detected, the storage control circuit 18A does not change its output read address RA and writes write address WA@read address RA&1''']
L;l'jl! IC! ! 16 (@2'$ (eゝゝ・
Z (D,,!.

t-9・1′! “[lf'15A17)A”ゞ1”0-
1"#(7) t: 1sec, ha"t-+>-
t>-b'' *1mtacw-n゛H・21 are simultaneously read from address 1 and output from the memory circuit 15A.

Similarly, during period T3, the program reference signal "P" is output from the program reference separation circuit 12, and the operation code ! The output of the detection circuit 13 is “Yes”, and the continuous detection time 1
The output of path 14 is "continuous" and the program path 14 is
L/>14MN"2""out"';an-cri゛;bt
=a・8self Clear, memory control circuit 18A is written as shown in FIG. 2(e).

Save the read address WA and read address RA from the previous program.
1 change v6 of the opposite value to the reference period T1)
・001・Memory 0 path 1590 manual input “operand of instruction 1” applied to ili is written to address 1 and 0・
Period T1''''0 address 1-zat:''' command
'1. The operation code '1' is read out and stored in the memory circuit 15.
Output from A.

During period T4, the program reference signal "P" is output from the program reference separation circuit 12, the output of the operation code detection circuit 13 is "Htt", and the output of the continuity detection circuit 14 is "continuous". Since the program reference signal "P" is being output, the storage control circuit 18A changes the write address WA and read address RA from the previous program reference time (period T
3), the operand of instruction 2 applied to the memory circuit 15A is written to address 0, and the operand of instruction 1 written to address 1 in period T3 is written to address 0 (Fig. 2(e)). '' is read out and used as the output of the memory circuit 15A (FIG. 2(h)).

During the period T5, the program reference signal "P" is not output from the program reference separation circuit 12 because it is a data reference. The output of the operation code detection circuit 13 is "L fT" and is not a program reference, so the continuous detection circuit 14
There is no output. Program reference signal “P is not output [・0°゛b゛6゛i;t!f
f1u[]tlj18A°'imA7t'L/IW
,.

A(Drip@'az L/T, ram 7t
'L/2 RA hno CV 1;.

Ru. As a result, the "instruction" applied to the memory circuit 15A
1.1 Memory read by instruction 1 is written to address 1, 1'□ is read from address 1 at the same time,
This becomes the output of the memory circuit 15A.

During the period T6, the program reference separation circuit 12 does not output the program reference signal "P". Opcode detection circuit 13″1°゛“1″T″″
′・! 1ull 14 (7)l) li.

'a''1''''r'y'a・7'0''＞Ao") 7?
L/> 2 'r Since there is 1 page, the memory control circuit 18A writes the write address l1WA &@
m 7 t' L/:l, RA 8@0 (7) 7 D
'j7 A,') l”i'□ 1゛2702 hours (period T4) and (in contrast to Fig. 2)
tlj(e)), writes the "operand of instruction 2" applied to the memory circuit 15A to address 1, and writes 01 in period T4.
．． Read the “opcode of instruction 2” written at address 1
1j11.1 and output from the memory circuit 15A.
1. As is clear from the above operations, Fig. 2 (
a) Comparing 11(4° and (h>), the “opcode of instruction 1” becomes “instruction 1” in period T1 of (a) due to the brief fetch operation
What was entered before the memory read '' by the previous instruction is switched in order with the 'memory read ' by the previous instruction in the period T3 of FIG. 2(h) and is transferred to the memory circuit 15.
A signal is sent to the emulator main unit 20 in accordance with the order of the commands.

. Similarly, the "opcode of instruction 2" that appeared before the "memory read by instruction 1" in period T4 of FIG. 2(a) is output from the 15A storage circuit in period T6 of FIG. 2(h), Signals are sent to the emulator main body 20 in the order of the instructions.

The display on the emulator main unit 20 is continuous from the reading of an instruction to its execution, making it easy to analyze the operation.

Next, FIG. 3(a) shows BRA (abbreviation for Branch AlwaysS, one of the jump-related operations of a microprocessor) among the one-word jump-related instructions.Reference: Motorola M68000 16/32-BIT
MICROPROCE 'U'1,.

11. 5SOR, Proqrammers Refe
,.

rence Manual 771 4th edition, 1
111・゛9844-E-・1°-7? fR'r"rゝ"*58n
6jii Connected bar of the microprocessor 5 under test at 71°: -:,:'□.

An example of the content of the jump is shown below.
1・□i・1 Lines are written to the emulator main unit 20, excluding unnecessary instructions.
Figures 3 (b) to (h) show how ijl is sent.
J:! ;1 In Figure 3, a jump command is a specified
(,: This is an instruction to jump to the address of memory 6, jump 1'' [・The nib destination instruction is the instruction to jump to the address of memory 6 specified by the jump instruction.
;:j・: Refers to the instruction stored at the address.
g□3□a) k knee q j yo 1, measured ¥
,stomach,. A. The contents of the bus to which the 1 nitrocessor 5 is connected are input to the memory circuit 15A via the input circuit 11, and in period T1, the operation code of jump instruction 1 is input, and in period T2, the operation code of jump instruction 1 is input to the storage circuit 15A. There is a "memory i'read".In period T3, there is actually an "actual i;11 read".
−.

Since the instruction that is skipped by the jump and does not need to be executed is written in the memory 6 immediately after the jump instruction 1, it is applied to the input of the storage circuit 15Δ by the prefetch operation. In period T4, the "operand of instruction 3" is applied, in period T5, the operand of instruction 3, which is the operand of the jump destination instruction 3, is applied, and in period T6, the "opcode of instruction 4" is applied.゛′ is applied.

During the period T1, since the "operation code of jump instruction 1" is applied to the program reference separation circuit 12, the program reference signal "P" is applied as shown in FIG. 3(b), as in the case of FIG. ” is output.

When the operation code detection circuit 13 detects an operation code during period T1, it outputs H99 as shown in (C). The operation code of jump instruction 1 in (a) is period T.
Since the "operand of the previous instruction" (not shown) in the period before 1 (see period T1 in (q)) and the address stored in the memory 6 are consecutive, the continuity detection circuit 14
outputs the "continuous" signal No. 11 as shown in (d). When the program reference signal 'P' is output, the storage control circuit 18A outputs the write address WA and the read address R[ .

A is the opposite of the previous program reference.
; The value is 1.1, and the input of the memory circuit 15A is the jump command.
Opcode number 11 is written to address 0, then address 1, or 1...ゎ(7)* @ (7) O, Ura...5□
8.211:;1 This is the output of the circuit 15A (Fig. 3(h)).
111QfDT2 cabzxo"・7°"6°"
) 7? 17 ”, / 1.□ Space separation circuit 12
The data reference is ・′:@ka. circle. ,a. Tsu A,') '7? Uayu 143
'1゛P'' is not output.Opcode detection circuit 1
3°1 output '1"L"' is present. Since the data reference is detected at 5°, there is no output from the continuous detection circuit 14, and since it is a data reference, only the write address WA is inverted. Same as read address □,. . ,1,1□15AO11f
T! ! 1 car. 8-1 “Memory read by previous instruction”
is written and output;

During period T3, the program reference signal "P" is output from the program reference separation circuit 12, and the output of the operation code detection circuit 13 is H".

Since the jump instruction 1 and the unexecuted instruction 2 are stored in consecutive addresses in the memory 6, the output of the continuity detection circuit 14 is "continuous".Since it is a program reference, the storage control circuit 18A , change the write address WA and read address RA to values opposite to those at the previous program reference time (period T1).
e)), writes the operation code of “unexecuted instruction 2” applied to the memory circuit 15A to address 1, and continues for a period T1.
“Jump instruction 1 opcode” written to address 0 in
The memory circuit 15A outputs.

During period T4, the program reference signal 'P'' is not output from the program reference separation circuit 12. The output of the operation code detection circuit 13 is H°'. The jump destination instruction 3 is stored in the memory 6. Since the current address is not continuous with the address of instruction 2 which is not executed, the continuity detection circuit 14 outputs "discontinuous" at 1::. j・1:: Even if the program reference signal “pto” is received,
At the same time, the memory control circuit 18 to which “discontinuity” was applied
A “Previous command (order applied during period T3G”)
, 1/instruction (i.e., "opcode of instruction 2 that is not executed"), and if it is an opcode, do not change the write address WA and read address RA.
', l・i. Therefore, “” written at address 1 during period T3
fruit"";! t'L%(/'''''?s 2 (7):
t<°-H"t"tiHi6n"1.・"This becomes the opcode of the jump destination instruction 3, and the output of the memory 11 circuit 15A continues from period T3:
1 "Operation code of jump instruction 1" is output.
:1 Even if it is "discontinuous", if the previous instruction (instruction applied in period :3) is not an opcode, ;If it is 1 or "continuous", memory control circuit 1 white A will not operate. Then write address WA and read address locations c and t. a. , j56. , wow, tsuyu. Oh, yo. II□・1 Value is changed.

Due to this operation, the "operation of instruction 2 which is not executed" does not become an output of the memory circuit 15A.

During period T5, the program reference signal "'P°" is output from the program reference separation circuit 12. The output of the operation code detection circuit 13 is "L". 3
Since the opcode and the address in the memory 6 are consecutive (see FIG. 5), the continuity detection circuit 14 outputs "continuous", and since the program reference signal "P" is output, the memory \1i111 circuit 18A Change the write address WA and read address RA to the opposite values from the previous program reference (period T4), and write “
Writes the operand of instruction 3, and from address 1, period T4
“Operation code of jump destination instruction 3” written in
Read and output.

During period T6, the program reference signal "P'' is output from the program reference separation circuit 12. The output of the operation code detection circuit 13 is "H''
It is. Since instruction 4 is continuous with instruction 3, the output of the continuity detection circuit 14 is "continuous".Similarly to period T5, the input "operation code of instruction 4" is written to address h<1, From address 0, the "operand of instruction 3" written in period T5 is output.

In this way, the "opcode of unexecuted instruction 2" generated by the BRA operation in the brief fetch operation on the bus connected to the microprocessor 5 under test is not outputted from the storage circuit 15A, but is sent to the emulator main unit 20. Since there is no such thing, operation analysis becomes easy.

The operations shown in FIGS. 2 and 3 will now be explained with reference to the flowchart in FIG. 4.

The program reference separation circuit 12 determines whether the signal on the bus connected to the microprocessor under test 5, which is an input to the storage circuit 15A, is a program reference that is an opcode or an operand of an instruction (ST
EP91).

If it is determined that it is a program reference (ST
EP91Y), the program reference signal P is output from the program reference separation circuit 12.

If it is not a program reference (STEP 9)
1N>, it is determined to be a data reference, and the program
Reference signal P is not output from program/reference separation circuit 12.

If it is determined to be a program reference (STEP 9)
1Y), the continuity detection circuit 14 determines whether the program reference is continuous or not. 5TEP92), continuous 6 (
STEP92Y), m-7 address WA and read address R
The storage control circuit 18A makes changes to A from the previous program reference. (STEP 95). If it is discontinuous (STEP92N), determine whether the previous instruction is an opcode (5TEP94), and if it is not an opcode (
STEP94N) Write address WA and read address RA
is changed to a value opposite to that when the program reference was detected last time (STEP 95).

Examine the previous instruction and if it was an opcode (
STEP94Y), write address WA and read address RA are not changed (STEP96).

Day 9°'J7yL, t'''1ffi'' detection a h t
= s match 11: (STEP 91 Symphony), change only the write address WA and make it the same value as the read address RA (STEP 93).
:Next, the memory circuit 15A indicated by the write address WA
:,). 8 degrees, 8 degrees, 9
□, 1, and reads and outputs the contents of the address of the memory circuit 15A indicated by the read address RA (STEP 98).

8′! 1”15A,?)”Jj”antt<),(Dr
@G“6: Emulator main unit 2 in the order of commands
0 (STEP 99).

Therefore, we will analyze the contents of the next bus and explain the above.
: The specified action is repeated.
:□ [Effect of the invention] As is clear from the above explanation, the order of signals on the bus is adjusted to the order of instructions by the brief fetch operation, so that F h < i
'6, *t;-・'Rh"f'*')*@tf
i @ * hT° The effects of the present invention are extremely large, since the operation analysis is facilitated and the hardware and software of the microprocessor can be quickly debugged.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of the design of the present invention, Figs. 2 and 3 are explanatory diagrams of the operation of the device shown in Fig. 1, and Fig. 4 is a procedure for processing signals in the device. FIG. 5 is a flowchart showing the internal structure of the memory 6. 5... Microprocessor under test 6... Memory 11... Input circuit 12.
・Program/reference separation circuit 13 ・Operation code detection circuit 14 ・Continuity detection circuit 15A ・Storage circuit 18
A...Storage control circuit 19...Emulator unit section 20...Emulator main body.

Claims (2)

[Claims] (1) Among bus signals that are access signals and data signals that access the memory to be accessed by the microprocessor under test from the bus connected to the microprocessor under test, the operation code and operand in which instructions are written are When either the opcode or operand is detected by the program reference for detecting either, the address in the memory where the detected opcode and operand are written is the instruction before the instruction. It is determined whether or not the addresses in the memory to which the data is written are consecutive, and if they are consecutive, there are two addresses that can be used as both the write address and the read address. The write address and read address of the memory circuit are changed to those obtained by swapping the write address and read address when either the opcode or operand was previously detected by the program reference, and the bus signal is changed to the one after the change. writes to the write address, reads the already written information from the changed read address, and when neither an opcode nor an operand is detected by the program reference, changes the write address of the memory circuit; Write the bus signal to the changed write address, making it the same as the read address, read the written information from the read address, which is the same as the write address, and determine whether or not it is continuous. If it is determined that the instruction is discontinuous, it is checked whether the previous instruction was an opcode or an operand, and if it is an opcode, the write address is changed without changing the write address and read address in the memory circuit. , reads the information already written from the read address, checks whether the previous instruction was an opcode or an operand, and if the result is an operand, the write address of the memory circuit and A microprocessor operation analysis method comprising changing a read address, writing the bus signal applied to the changed write address, and reading already written information from the changed read address. (2) To extract, from the bus connected to the microprocessor under test, a bus signal containing an operation code, an operand, and a data signal in which an instruction for accessing the memory to be accessed by the microprocessor under test is written. input means, and program reference separation means for outputting a program reference signal when detecting either the opcode or the operand;
an operation code detection means for detecting the operation code; and whether the address in the memory where the instruction is written is continuous or discontinuous with the address in the memory where the instruction before the instruction is written. continuous detection means for detecting continuous signals and outputting continuous signals and discontinuous signals; and writing the output of the input means to the write address specified by the write address signal and to the read address specified by the read address signal. a storage means having two addresses that can be used as both the write address and the read address for reading the stored information; and when receiving the program reference signal and the continuous signal, The write address signal and the read address signal for changing the write address and read address in the opposite direction from when the previous program reference was detected are output, and when the program reference signal is not received, the write address signal and the read address signal are output. outputting the write address signal and read address signal for changing the write address to make it the same as the read address; receiving the program reference signal and the discontinuous signal; If an operation code is detected at , the write address signal and the read address signal are outputted so as not to change the write address and the read address, the program reference signal and the discontinuous signal are received, and the program reference signal and the discontinuous signal are received. If the opcode detection means has not detected an opcode in the previous instruction, the write address signal and the read address are used to change the write address and read address to the opposite from when the previous program reference was detected. A microcomputer comprising: an emulator unit section including a storage control means for outputting a signal; and an emulator main body section for receiving and displaying an output of the storage means included in the emulator unit section. Processor behavior analysis device.