JPS6247190A - Manufacture of flat surface laminate body for multilayer circuit board - Google Patents
Manufacture of flat surface laminate body for multilayer circuit boardInfo
- Publication number
- JPS6247190A JPS6247190A JP18807885A JP18807885A JPS6247190A JP S6247190 A JPS6247190 A JP S6247190A JP 18807885 A JP18807885 A JP 18807885A JP 18807885 A JP18807885 A JP 18807885A JP S6247190 A JPS6247190 A JP S6247190A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- sulfuric acid
- copper
- inner layer
- concentrated sulfuric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 9
- 239000011889 copper foil Substances 0.000 claims description 7
- 239000003822 epoxy resin Substances 0.000 claims description 5
- 229920000647 polyepoxide Polymers 0.000 claims description 5
- 238000010306 acid treatment Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 238000005507 spraying Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000007598 dipping method Methods 0.000 claims 1
- 239000005416 organic matter Substances 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000007654 immersion Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、多層印刷配線板用内層回路板の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method of manufacturing an inner layer circuit board for a multilayer printed wiring board.
〈従来技術〉
従来、多層印刷配線板を製造する際に、銅張積層板を使
用して内層回路板を製造する。その内層回路板の製造は
、先づ銅張積層板の銅箔表面をブラシ及びパフ研磨し、
感光性レジストフィルムを積層し、回路パターンの焼付
、現像、エツチング、剥離の作業を行ない、その後に回
路パターンの外観検査を行なう。<Prior Art> Conventionally, when manufacturing a multilayer printed wiring board, a copper clad laminate is used to manufacture an inner layer circuit board. The inner layer circuit board is manufactured by first brushing and puff polishing the copper foil surface of the copper clad laminate.
Photosensitive resist films are laminated, and the circuit pattern is printed, developed, etched, and peeled off, and then the appearance of the circuit pattern is inspected.
〈発明が解決しようとする問題点〉
前記の内層回路板の製造において、使用する鉛箔積層板
の銅箔表向上に付着するエポキシ樹脂及びその他樹脂の
汚れは、ブラシ及びパフによる研磨作業で除去不可能で
ある。さらに、その汚ｎＨＨの状態で積層作業以降の回
路加工を行なうと、回路パターンのエツチング作業にお
いて不要な銅箔部分における銅残り即ち残銅ショートが
発生し、外観検査で銅残り部分の除去作業を行なう結果
となり、多層印刷配線板に悪影響を及ぼす。<Problems to be Solved by the Invention> In manufacturing the above-mentioned inner layer circuit board, stains of epoxy resin and other resins adhering to the surface of the copper foil of the lead foil laminate used are removed by polishing with a brush and puff. It's impossible. Furthermore, if circuit processing after lamination work is carried out in the contaminated nHH state, copper residue, that is, a short circuit will occur in unnecessary copper foil parts during circuit pattern etching work, and removal of the remaining copper part will be required during visual inspection. This results in an adverse effect on the multilayer printed wiring board.
〈問題点を解決するための手段〉
以上の問題点全解決するための手段として、本発明は、
銅張積層板全使用して内層用回路盤を製造する際に、先
づ銅張積層板を！ｌｌ硫酸に浸漬して表面の有機物を除
去する、すなわち表面に付着したエポキシ樹脂温ｎその
他樹脂等の有機物全除去する。その後、銅箔表面をブラ
シ及びパフ研磨し、感光性レジストフィルムの積ノー回
路パターンの焼付、現像、エツチング、剥離の作業をす
る。<Means for solving the problems> As a means for solving all the above problems, the present invention provides the following:
When manufacturing an inner layer circuit board using all copper-clad laminates, use copper-clad laminates first! Immerse in sulfuric acid to remove organic matter on the surface, that is, remove all organic matter such as epoxy resin and other resins adhering to the surface. Thereafter, the surface of the copper foil is polished with a brush and puff, and the circuit pattern of the photosensitive resist film is printed, developed, etched, and peeled off.
本発明の要点である濃硫酸処理をさらに具体的に説明す
ると、７５〜９８％濃度の硫酸を使用し、その浸漬温度
を１０〜３５℃、浸漬時間を１０秒以上１０分以内とす
る。この方法によると、銅箔表面に伺着したエポキシ樹
脂その他の有機物は完全に除去さｎる。To explain the concentrated sulfuric acid treatment, which is the gist of the present invention, in more detail, sulfuric acid with a concentration of 75 to 98% is used, the immersion temperature is 10 to 35°C, and the immersion time is 10 seconds to 10 minutes. According to this method, epoxy resin and other organic substances adhering to the surface of the copper foil are completely removed.
有機物を完全除去した後、研磨することが重要である。It is important to polish after completely removing organic matter.
濃硫酸処理の方法としては、濃硫酸に浸漬する方法以外
に！Ｉ硫酸をスプレー噴射する方法でも良い。硫酸の濃
度計測は、比重耐酸るいは電導度測定による。There are other methods of concentrated sulfuric acid treatment other than immersion in concentrated sulfuric acid! A method of spraying I sulfuric acid may also be used. The concentration of sulfuric acid is measured by specific gravity acid resistance or conductivity measurement.
硫酸全入２’Ｌ、有機物４が付着した銅張積層板全浸漬
する。Fully immerse the copper clad laminate with 4 sulfuric acid adhering to it in 2'L of sulfuric acid.
〈発明の効果〉
本発明の銅張積層板を濃硫酸処理する方法によって、銅
箔表面に付着したエポキシ樹脂温ｎ及びその他樹脂等の
有機物は完全に除去さγし、さらに回路パターンのエツ
チング作業において不要な銅箔部分への銅残りがなくな
り、従来性なわγしていた銅残り部分の除去作業が不要
となった。<Effects of the Invention> By the method of treating a copper-clad laminate with concentrated sulfuric acid of the present invention, organic matter such as epoxy resin and other resins adhering to the surface of the copper foil can be completely removed, and furthermore, the etching process of circuit patterns can be easily performed. In this process, there is no longer any copper residue on unnecessary copper foil parts, and there is no longer a need to remove the copper residue, which was a problem in the conventional method.
状態を示す説明断面図である。It is an explanatory sectional view showing a state.
１・・・・・・処理槽、 ２・・・・・・濃硫酸５
・・・・・・銅張積層板、４・・・・・・付着有機物。1... Processing tank, 2... Concentrated sulfuric acid 5
......Copper-clad laminate, 4...Adhesive organic matter.
Claims (1)
銅張積層板の銅箔表面上に付着したエポキシ樹脂スポッ
ト及びその他の有機物を濃硫酸処理して完全除去した後
、その銅箔表面の研磨を行なうことを特徴とする多層印
刷配線板用内層回路板の製造方法。 ２、濃硫酸処理条件を、７５〜９８％濃硫酸、温度１０
〜３５℃、処理時間１０秒〜１０分とし、浸漬又はスプ
レー噴射によることを特徴とする特許請求の範囲第１項
記載の多層印刷配線板用内層回路板の製造方法。[Claims] 1. Epoxy resin spots and other organic substances adhering to the copper foil surface of a copper-clad laminate for inner layer circuits used in manufacturing multilayer printed wiring boards are completely removed by treatment with concentrated sulfuric acid. 1. A method for producing an inner layer circuit board for a multilayer printed wiring board, the method comprising: thereafter polishing the surface of the copper foil. 2.Concentrated sulfuric acid treatment conditions: 75-98% concentrated sulfuric acid, temperature 10
The method for manufacturing an inner layer circuit board for a multilayer printed wiring board according to claim 1, characterized in that the temperature is 35° C. and the processing time is 10 seconds to 10 minutes, and the method is carried out by dipping or spraying.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18807885A JPS6247190A (en) | 1985-08-27 | 1985-08-27 | Manufacture of flat surface laminate body for multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18807885A JPS6247190A (en) | 1985-08-27 | 1985-08-27 | Manufacture of flat surface laminate body for multilayer circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6247190A true JPS6247190A (en) | 1987-02-28 |
Family
ID=16217317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18807885A Pending JPS6247190A (en) | 1985-08-27 | 1985-08-27 | Manufacture of flat surface laminate body for multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6247190A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02299287A (en) * | 1989-05-15 | 1990-12-11 | Shin Etsu Chem Co Ltd | How to clean printed circuit boards |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5125770A (en) * | 1974-08-27 | 1976-03-02 | Fujitsu Ltd | Tasopurintobanno kagakusenjohoho |
| JPS5466457A (en) * | 1977-11-07 | 1979-05-29 | Ibm | Method of treating substrate with circuit pattern |
| JPS54144968A (en) * | 1978-05-04 | 1979-11-12 | Fujitsu Ltd | Method of producing multilayer printed board |
| JPS6032393A (en) * | 1983-08-01 | 1985-02-19 | 松下電工株式会社 | Method of producing multilayer circuit board |
-
1985
- 1985-08-27 JP JP18807885A patent/JPS6247190A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5125770A (en) * | 1974-08-27 | 1976-03-02 | Fujitsu Ltd | Tasopurintobanno kagakusenjohoho |
| JPS5466457A (en) * | 1977-11-07 | 1979-05-29 | Ibm | Method of treating substrate with circuit pattern |
| JPS54144968A (en) * | 1978-05-04 | 1979-11-12 | Fujitsu Ltd | Method of producing multilayer printed board |
| JPS6032393A (en) * | 1983-08-01 | 1985-02-19 | 松下電工株式会社 | Method of producing multilayer circuit board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02299287A (en) * | 1989-05-15 | 1990-12-11 | Shin Etsu Chem Co Ltd | How to clean printed circuit boards |
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