JPS6247377B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a relock circuit for a sampling quadlock circuit.

Here, the sampling quartz lock circuit will be briefly explained with reference to FIG.

Reference numeral 1 denotes a local oscillator of the FM receiver, and a variable capacitance diode _D1 is connected in parallel with a variable capacitor (paricon) Vc within the local oscillator. 2 is an oscillator that includes a crystal oscillator 3 and generates a reference oscillation signal of, for example, 6.4 MHz; 4 is a frequency divider that divides the frequency of the oscillation signal from the oscillator to 1/64 to generate a 100 KHz control signal. 5 is an amplifier that amplifies the signal from the local oscillator 1; 6 is a phase comparator that compares the phase of the local oscillation signal from the amplifier with the 100KHz control signal from the frequency divider 4; 7 is a phase comparator 6 The DC control voltage from the low-pass filter 7 is supplied to the variable capacitance diode _D1 of the local oscillator 1. The output side of the phase comparator 6 has an FM local oscillation signal and 100K
A difference component of the Hz control signal, that is, a beat signal of usually 0 to 50 KHz is generated. That is, if the beat frequency is 0, the FM local oscillation frequency is an integer multiple of 100KHz, otherwise the FM local oscillation frequency is
Indicates that the beat frequency deviates from an integer multiple of 100KHz.

The variable condenser is now trying to receive the desired broadcast wave.
When the VC is operated, the beat signal from the phase comparator 6 is applied to the low-pass filter 7, rectified, and converted into a DC voltage when separated, and this DC voltage is applied to the variable capacitance diode _D1 of the local oscillator 1. This DC voltage goes up and down depending on the oscillation frequency of the local oscillator 1, but when the oscillation frequency of the local oscillator 1 approaches a desired frequency that is an integral multiple of 100 KHz and falls within a predetermined frequency range from the desired frequency, the local oscillator 1 Locked to frequency.

Here, phase comparator 6 → low-pass filter 7 → voltage-controlled local oscillator 1 → amplifier 5 → phase comparator 6
The maximum frequency width at which the loop converges at a predetermined frequency that is an integral multiple of 100 KHz is called the capture range, and is determined by the cutoff frequency of the low-pass filter 7. On the other hand, when the once locked loop is varied by varying the elements other than the variable capacitance diode _D1 of the local oscillator 1, the frequency width immediately before the lock is released is called the lock range. Generally, the capture range is selected to be about ±5 to 10 KHz, and the lock range is selected to be about 100 to 200 KHz (however, this varies depending on the channel separation). The reason why the ratio between the start range and the lock range is set so large is to lock at the center of the lock range as much as possible during channel selection, and to alleviate temperature drift conditions of the local oscillator 1.

That is, this is to prevent the lock from being easily lost even if the local oscillation frequency is shifted due to temperature changes, for example.

When the variable capacitor VC is operated in this manner during channel selection, the oscillation frequency of the local oscillator 1 changes in steps at intervals of 100 KHz.

The above is an overview of the sampling quartzlock circuit.In such a sampling quartzlock, when the function selector switch is changed or the power is turned OFF and then ON again, the oscillation frequency of the local oscillator changes to the desired frequency. There were times when the camera would no longer lock.

In view of these points, the present invention has been developed to prevent the oscillation frequency from falling out of the capture range due to some accident such as when switching the function selector switch or when turning on the power again.
This invention relates to a relock circuit that pulls the oscillation frequency into the capture range and locks it without reselecting a station, and one embodiment of the present invention will be described below with reference to FIGS. 2 and 3.

In FIG. 2, OP ₁ is the first voltage comparator (operational amplifier) constituting the active low-pass filter 7, and the first voltage comparator has an inverting input terminal (input terminal) I ₁ and a resistor R _{1 .} via phase comparator 6
The output signal from the non-inverting input terminal (
A reference voltage is applied to the input terminal ( _I2 ) from the power supply line l via the variable resistor VR. R ₂ , C ₁ are the inverting input terminal I ₁ of the first voltage comparator OP ₁ and the ground E
Resistor and capacitor connected in series between R ₃ and C ₂
is a resistor and a capacitor connected in parallel between the output terminal 8 of the first voltage comparator OP ₁ and the inverting input terminal I ₁ , and R ₄ has one end connected to the output terminal 8 of the first voltage comparator OP ₁ . The other end of the resistor is a variable capacitance diode that constitutes the voltage controlled local oscillator 1.
Connected to D ₁ . C ₃ is the other end of resistor R ₄ and ground E
This is the capacitor connected between the two.

OP ₂ is a second voltage comparator (operational amplifier), and the non-inverting input terminal (input terminal) I ₂ ' of the second voltage comparator is connected to an FM detection circuit (for example, a quadrature detection circuit) via a resistor R ₅ . A constant reference DC voltage V ₁ shown in FIG. 3A is applied from a voltage source (not shown). Also, a resistor is connected to the inverting input terminal (input terminal) I ₁ ′.
FM from the FM detection circuit via _R6 as shown in Figure 3A.
A variable DC voltage V ₂ that changes around a constant reference DC voltage V ₁ is applied to the demodulated output, ie, the tuning deviation from the tuning center point.

9 and 10 are first and second control circuits connected to the output side of the second voltage comparator _OP2 . The first control circuit 9 has a base connected to the output terminal 11 of the second voltage comparator OP ₂ via a resistor R ₇ , an emitter connected to the power supply line l, and a resistor R ₈ connected between the emitter and the base. The collector is connected through a resistor
A PNP transistor Q ₁ is connected to earth E through R ₉ and a resistor is connected to the collector of the transistor.
a first inverter IN ₁ connected via R ₁₀ ;
It is composed of a second inverter _IN2 connected to the first inverter via a resistor _R11 , and a diode _D2 whose cathode is connected to the second inverter via a resistor _R12 . The second control circuit 10 has a base connected to the output terminal 11 of the second voltage comparator OP 2 via a resistor R ₁₃ , a collector connected to the power supply line l via a resistor R ₁₄ , and an emitter connected to the output terminal 11 of the second voltage comparator OP ₂ . is connected to earth E, and the base and emitter (earth) are connected through a resistor _R15.An NPN transistor _Q2 is connected to the earth E, and a diode _D3 whose anode is connected to the collector of the transistor through a resistor _R16 . It is made up of.

Q ₃ is a gate transistor composed of a field effect transistor FET, whose drain electrode d (input terminal) is connected to the output terminal 12 of the first and second control circuits 9 and 10, and whose source electrode S ( The output terminal (output terminal) is connected to the connection point 13 between the resistor R ₂ and the capacitor C ₁ , and the gate electrode g (control terminal) is connected to the ground E via the resistor R ₁₇ and diode D ₄ connected in parallel. A capacitor C ₄ and a resistor R ₁₈ are connected in series between the gate electrode and the power supply line 1, and a movable terminal 15 is connected to the earth E through a resistor R ₁₉ at the connection point 14 between the capacitor and the resistor. Switch _S1 is connected. Q ₄ is a transistor whose base is connected through a resistor R ₂₀
A transistor connected to the gate electrode of Q ₃ , whose emitter is connected to the earth E, and whose collector is connected to the power supply line l via the resistor R ₂₁ , D ₅ is connected to the collector of the transistor Q ₄ and the transistor Q ₃
This is a diode connected between the drain electrode of the

The operation of the circuit shown in FIG. 2 constructed in this manner will now be described.

Now consider the case where transistor Q ₃ is turned on.

The reference DC voltage V ₁ in Figure 3 A is applied to the non-inverting input terminal I ₂ ' of the second voltage comparator OP ₂ , and the inverting input terminal
When the variable DC voltage V ₂ shown in Figure 3 A is added to I ₁ ', the output of the second voltage comparator OP ₂ becomes a high level (hereinafter referred to as "H") between A and C as shown in Figure 3 B. ),
It becomes a low level (hereinafter referred to as "L") between CE and E. Therefore, when the output of the second voltage comparator _OP2 is "H" between A and C, the input of the first inverter _IN1 is "L" because the transistor _Q1 is OFF, and the input of the second inverter _IN2 is "L". The output becomes "L". At this time, diode _D2 is forward biased and turned on, and gate transistor _Q3 is also turned on, so
The first component that constitutes the active low-pass filter
The potential at the inverting input terminal _I1 of the first voltage comparator _OP1 decreases, and the output voltage of the first voltage comparator _OP1 increases.
As a result, the voltage applied to the variable capacitance diode D1 that constitutes the voltage controlled local oscillator ₁ increases, so
The capacitance value of the variable capacitance diode decreases and the oscillation frequency of the local oscillator 1 increases. That is, when the tuning point is point B in FIG. 3A, it moves in the direction of the tuning center point (point C) and enters the capture range (however, in the case of the upper heterodyne system). On the other hand, transistor _Q2 is turned on because the base potential is "H",
Since the output (potential of the collector) of the transistor becomes "L", the diode _D3 becomes reverse biased and is cut off.

Next, when the output of the second voltage comparator OP ₂ is "L" between CE and E, the transistor Q ₂ is OFF and its output becomes "H". At this time, diode D ₃ is forward biased and gate transistor Q ₃ is also turned on.
, the potential of the inverting input terminal _I1 of the first voltage comparator _OP1 increases, and the potential of the first voltage comparator OP1 increases.
The output voltage of OP ₁ drops.

As a result, the voltage applied to the variable capacitance diode D1 constituting the voltage controlled local oscillator ₁ decreases, so the capacitance value of the variable capacitance diode increases and the oscillation frequency of the local oscillator 1 decreases. That is, in Figure 3A, when the tuning point is point D, the tuning center point (C
point) and enter the capture range. On the other hand, the transistor _Q1 is turned on when the base potential is "L", and the output of the second inverter _IN2 is "H", so the diode _D2 is cut off.

Furthermore, the two input terminals of the second voltage comparator OP ₂
When the potentials applied to I ₁ ′ and I ₂ ′ are the same potential, that is, at point C in Figure 3 A during complete tuning, the first voltage comparator
Bias resistors R ₇ , R ₈ , R ₁₃ , R are set so that the potential of the output terminal 11 of OP ₂ is the same as the potential of the input terminals I _{1 ′} , I ₂ ′, and both transistors Q 1 and Q ₂ are turned on. ₁₅
is selected, the output of the second inverter IN ₂ is “H”, the output of the transistor Q ₂ is “L”, and
Both diodes D ₂ and D ₃ are cut off.

The above operation is the operation when gate transistor Q ₃ is ON, and when gate transistor Q ₃ is OFF.
In this case, the above operation is not performed.

The gate transistor _Q3 is turned on and off by the switch _S1 . This switch _S1 is a switch linked to, for example, a function changeover switch, and is configured to close when receiving an FM broadcast, for example, when receiving an AM broadcast, or when operating a phono, and to open when receiving an FM broadcast.

Therefore, from an operating state other than when receiving FM broadcasts,
When switching to the FM operating state, a charging current flows from the power supply line l through the resistor _R18 , and a bias voltage is applied to the gate electrode of the gate transistor _Q3 , so that the gate transistor _Q3 is activated only during this charging period.
is turned on, and the relock operation as described above is performed depending on the synchronization point.

In addition, the charging time of capacitor C ₄ is determined by resistor R ₁₇ ,
It is determined by R ₁₈ , R ₂₀ , capacitor C ₄ , etc.
Also, the transistor _Q4 is ON during the period when charging current flows through the capacitor _C4 , and the diode _D5 is cut off, but during other periods, the transistor
Q ₄ is turned off, diode D ₅ is turned on, and a predetermined potential is applied from the power supply line l to the drain electrode d of the gate transistor Q ₃ via the resistor R ₂₁ and the diode D ₅ , and the gate electrode of the gate transistor Q ₃ is turned on. The gate transistor _Q3 is reliably turned off when the potential is 0.

In addition to when switching the function changeover switch, for example, if you want to perform a relock operation when the power is turned on again, it is possible to operate in conjunction with the power switch (not shown).
Closes when the power switch is OFF;
If a switch S ₁ ' that opens when turned on is provided, the above-mentioned relocking operation will be performed when the power switch is turned on from off.

As described above, according to the relock circuit of the sampling/quartz lock circuit according to the present invention, the oscillation frequency is forcibly pulled into the capture range when the function changeover switch is switched or when the power is turned on again. Therefore, there is no need to perform reselection operations, and the troublesome operation can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a sampling/quartz lock circuit, FIG. 2 is a circuit diagram showing a relock circuit of the sampling/quartz lock circuit according to the present invention, and FIG. 3 is a block diagram showing a relock circuit of the sampling/quartz lock circuit according to the present invention. 2 is an input/output waveform diagram of voltage comparator No. 2. FIG. OP ₁ , OP ₂ ... first and second voltage comparators, Q ₃ ... gate transistor, C ₄ ... capacitor, 9, 10...
control circuit.

Claims (1)

[Claims] 1 The output terminal of the gate element is connected to one input terminal of the first voltage comparator constituting the low-pass filter, and the tuning Two systems of control circuits that generate outputs at opposite levels in response to deviation from the center point are connected to the input terminal of the gate element, and the control terminal of the gate element is connected to a switch such as a function changeover switch or a power switch. A relock circuit for a sampling quartz lock circuit comprising a capacitor connected thereto which is charged at the time of switching and makes the gate element conductive during the charging period.